diff options
Diffstat (limited to 'include')
22 files changed, 252 insertions, 1726 deletions
diff --git a/include/asm-arm/arch-mx25/mmc.h b/include/asm-arm/arch-mx25/mmc.h deleted file mode 100644 index 5f12934..0000000 --- a/include/asm-arm/arch-mx25/mmc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * linux/drivers/mmc/mmc.h - * - * Author: Vladimir Shebordaev, Igor Oblakov - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __MMC_MX25_3STACK_H__ -#define __MMC_MX25_3STACK_H__ - -#endif /* __MMC_MX51_3STACK_H__ */ diff --git a/include/asm-arm/arch-mx25/sdhc.h b/include/asm-arm/arch-mx25/sdhc.h deleted file mode 100644 index 5514ad4..0000000 --- a/include/asm-arm/arch-mx25/sdhc.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef SDHC_H -#define SDHC_H - -#include <linux/types.h> - -#define ESDHC_SOFTWARE_RESET_DATA ((u32)0x04000000) -#define ESDHC_SOFTWARE_RESET_CMD ((u32)0x02000000) -#define ESDHC_SOFTWARE_RESET ((u32)0x01000000) -#define ESDHC_CMD_INHIBIT 0x00000003 -#define ESDHC_SYSCTL_INITA ((u32)0x08000000) -#define ESDHC_LITTLE_ENDIAN_MODE ((u32)0x00000020) -#define ESDHC_HW_BIG_ENDIAN_MODE ((u32)0x00000010) -#define ESDHC_BIG_ENDIAN_MODE ((u32)0x00000000) -#define ESDHC_ONE_BIT_SUPPORT ((u32)0x00000000) -#define ESDHC_FOUR_BIT_SUPPORT ((u32)0x00000002) -#define ESDHC_EIGHT_BIT_SUPPORT ((u32)0x00000004) -#define ESDHC_CLOCK_ENABLE 0x00000007 -#define ESDHC_FREQ_MASK 0xffff0007 -#define ESDHC_SYSCTL_FREQ_MASK ((u32)0x000FFFF0) -#define ESDHC_SYSCTL_IDENT_FREQ_TO1 ((u32)0x0000800e) -#define ESDHC_SYSCTL_OPERT_FREQ_TO1 ((u32)0x00000200) -#define ESDHC_SYSCTL_IDENT_FREQ_TO2 ((u32)0x00002040) -#define ESDHC_SYSCTL_OPERT_FREQ_TO2 ((u32)0x00000050) -#define ESDHC_INTERRUPT_ENABLE ((u32)0x007f0133) -#define ESDHC_CLEAR_INTERRUPT ((u32)0x117f01ff) -#define ESDHC_SYSCTL_DTOCV_VAL ((u32)0x000E0000) -#define ESDHC_IRQSTATEN_DTOESEN ((u32)0x00100000) -#define ESDHC_ENDIAN_MODE_MASK ((u32)0x00000030) -#define ESDHC_SYSCTRL_RSTC ((u32)0x02000000) -#define ESDHC_SYSCTRL_RSTD ((u32)0x04000000) -#define ESDHC_CONFIG_BLOCK 0x00010200 -#define ESDHC_OPER_TIMEOUT (96 * 100) -#define ESDHC_ACMD41_TIMEOUT (32000) -#define ESDHC_CMD1_TIMEOUT (32000) -#define ESDHC_BLOCK_SHIFT (16) -#define ESDHC_CARD_INIT_TIMEOUT (64) - -#define ESDHC_SYSCTL_SDCLKEN_MASK ((u32)0x00000008) -#define ESDHC_PRSSTAT_SDSTB_BIT ((u32)0x00000008) -#define ESDHC_SYSCTL_INPUT_CLOCK_MASK ((u32)0x00000007) - -#define ESDHC_BUS_WIDTH_MASK ((u32)0x00000006) -#define ESDHC_DATA_TRANSFER_SHIFT (4) -#define ESDHC_RESPONSE_FORMAT_SHIFT (16) -#define ESDHC_DATA_PRESENT_SHIFT (21) -#define ESDHC_CRC_CHECK_SHIFT (19) -#define ESDHC_CMD_INDEX_CHECK_SHIFT (20) -#define ESDHC_CMD_INDEX_SHIFT (24) -#define ESDHC_BLOCK_COUNT_ENABLE_SHIFT (1) -#define ESDHC_MULTI_SINGLE_BLOCK_SELECT_SHIFT (5) -#define BLK_LEN (512) -#define ESDHC_READ_WATER_MARK_LEVEL_BL_4 ((u32)0x00000001) -#define ESDHC_READ_WATER_MARK_LEVEL_BL_8 ((u32)0x00000002) -#define ESDHC_READ_WATER_MARK_LEVEL_BL_16 ((u32)0x00000004) -#define ESDHC_READ_WATER_MARK_LEVEL_BL_64 ((u32)0x00000010) -#define ESDHC_READ_WATER_MARK_LEVEL_BL_512 ((u32)0x00000080) - -#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_4 ((u32)0x00010000) -#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_8 ((u32)0x00020000) -#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_16 ((u32)0x00040000) -#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_64 ((u32)0x00100000) -#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_512 ((u32)0x00800000) - -#define WRITE_READ_WATER_MARK_LEVEL 0x00800080 - -/* Present State register bit masks */ -#define ESDHC_PRESENT_STATE_CIHB ((u32)0x00000001) -#define ESDHC_PRESENT_STATE_CDIHB ((u32)0x00000002) -#define ONE (1) -#define ESDHC_FIFO_SIZE (128) - -#define ESDHC_STATUS_END_CMD_RESP_MSK ((u32)0x00000001) -#define ESDHC_STATUS_END_CMD_RESP_TIME_MSK ((u32)0x000F0001) -#define ESDHC_STATUS_TIME_OUT_RESP_MSK ((u32)0x00010000) -#define ESDHC_STATUS_RESP_CRC_ERR_MSK ((u32)0x00020000) -#define ESDHC_STATUS_RESP_CMD_INDEX_ERR_MSK ((u32)0x00080000) -#define ESDHC_STATUS_BUF_READ_RDY_MSK ((u32)0x00000020) -#define ESDHC_STATUS_BUF_WRITE_RDY_MSK ((u32)0x00000010) -#define ESDHC_STATUS_TRANSFER_COMPLETE_MSK ((u32)0x00000002) -#define ESDHC_STATUS_DATA_RW_MSK ((u32)0x00700002) -#define ESDHC_STATUS_TRANSFER_COMPLETE_MSK ((u32)0x00000002) -#define ESDHC_STATUS_TIME_OUT_READ_MASK ((u32)0x00100000) -#define ESDHC_STATUS_READ_CRC_ERR_MSK ((u32)0x00200000) -#define ESDHC_STATUS_RESP_CMD_END_BIT_ERR_MSK ((u32)0x00040000) -#define ESDHC_STATUS_RW_DATA_END_BIT_ERR_MSK ((u32)0x00400000) - -#define ESDHC_STATUS_TIME_OUT_READ (3200) -#define ESDHC_READ_DATA_TIME_OUT (3200) -#define ESDHC_WRITE_DATA_TIME_OUT (8000) - -#define ESDHC_CONFIG_BLOCK_512 ((u32)0x00000200) -#define ESDHC_CONFIG_BLOCK_64 ((u32)0x00000040) -#define ESDHC_CONFIG_BLOCK_8 ((u32)0x00000008) -#define ESDHC_CONFIG_BLOCK_4 ((u32)0x00000004) - -#define ESDHC_MAX_BLOCK_COUNT ((u32)0x0000ffff) - -typedef enum { - ESDHC1, - ESDHC2, - ESDHC3 -} esdhc_num_t; - -typedef enum { - WRITE, - READ, -} xfer_type_t; - -typedef enum { - RESPONSE_NONE, - RESPONSE_136, - RESPONSE_48, - RESPONSE_48_CHECK_BUSY -} response_format_t; - - -typedef enum { - DATA_PRESENT_NONE, - DATA_PRESENT -} data_present_select; - -typedef enum { - DISABLE, - ENABLE -} crc_check_enable, cmdindex_check_enable, block_count_enable; - -typedef enum { - SINGLE, - MULTIPLE -} multi_single_block_select; - -typedef struct { - u32 command; - u32 arg; - xfer_type_t data_transfer; - response_format_t response_format; - data_present_select data_present; - crc_check_enable crc_check; - cmdindex_check_enable cmdindex_check; - block_count_enable block_count_enable_check; - multi_single_block_select multi_single_block; -} esdhc_cmd_t; - -typedef struct { - response_format_t format; - u32 cmd_rsp0; - u32 cmd_rsp1; - u32 cmd_rsp2; - u32 cmd_rsp3; -} esdhc_resp_t; - -typedef enum { - BIG_ENDIAN, - HALF_WORD_BIG_ENDIAN, - LITTLE_ENDIAN -} endian_mode_t; - -typedef enum { - OPERATING_FREQ = 20000, /* in kHz */ - IDENTIFICATION_FREQ = 400 /* in kHz */ -} sdhc_freq_t; - -enum esdhc_data_status { - ESDHC_DATA_ERR = 3, - ESDHC_DATA_OK = 4 -}; - -enum esdhc_int_cntr_val { - ESDHC_INT_CNTR_END_CD_RESP = 0x4, - ESDHC_INT_CNTR_BUF_WR_RDY = 0x8 -}; - -enum esdhc_reset_status { - ESDHC_WRONG_RESET = 0, - ESDHC_CORRECT_RESET = 1 -}; - -typedef enum { - WEAK = 0, - STRONG = 1 -} esdhc_pullup_t; - -extern u32 interface_reset(void); -extern void interface_configure_clock(sdhc_freq_t); -extern void interface_read_response(esdhc_resp_t *); -extern u32 interface_send_cmd_wait_resp(esdhc_cmd_t *); -extern u32 interface_data_read(u32 *, u32); -extern void interface_config_block_info(u32, u32, u32); -extern u32 interface_data_write(u32 *, u32); -extern void interface_clear_interrupt(void); -extern void interface_initialization_active(void); -extern void esdhc_set_cmd_pullup(esdhc_pullup_t pull_up); -extern void esdhc_soft_reset(u32 mask); -extern u32 interface_set_bus_width(u32 bus_width); -/*================================================================================================*/ -#endif /* ESDHC_H */ diff --git a/include/asm-arm/arch-mx35/mmc.h b/include/asm-arm/arch-mx35/mmc.h deleted file mode 100644 index 8699f40..0000000 --- a/include/asm-arm/arch-mx35/mmc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * linux/drivers/mmc/mmc.h - * - * Author: Vladimir Shebordaev, Igor Oblakov - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __MMC_MX35_3STACK_H__ -#define __MMC_MX35_3STACK_H__ - -#endif /* __MMC_MX35_3STACK_H__ */ diff --git a/include/asm-arm/arch-mx35/mx35.h b/include/asm-arm/arch-mx35/mx35.h index 9d1ae54..45ddc0f 100644 --- a/include/asm-arm/arch-mx35/mx35.h +++ b/include/asm-arm/arch-mx35/mx35.h @@ -232,14 +232,47 @@ #ifndef __ASSEMBLER__ + enum mxc_clock { MXC_ARM_CLK = 0, MXC_AHB_CLK, MXC_IPG_CLK, MXC_IPG_PERCLK, MXC_UART_CLK, +MXC_ESDHC_CLK, +MXC_USB_CLK, +}; + +enum plls { + MCU_PLL = CCM_BASE_ADDR + CLKCTL_MPCTL, + PER_PLL = CCM_BASE_ADDR + CLKCTL_PPCTL, }; +enum mxc_main_clocks { + CPU_CLK, + AHB_CLK, + IPG_CLK, + IPG_PER_CLK, + NFC_CLK, + USB_CLK, + HSP_CLK, +}; + +enum mxc_peri_clocks { + UART1_BAUD, + UART2_BAUD, + UART3_BAUD, + SSI1_BAUD, + SSI2_BAUD, + CSI_BAUD, + MSHC_CLK, + ESDHC1_CLK, + ESDHC2_CLK, + ESDHC3_CLK, + SPDIF_CLK, + SPI1_CLK, + SPI2_CLK, +}; /*! * NFMS bit in RCSR register for pagesize of nandflash */ diff --git a/include/asm-arm/arch-mx35/sdhc.h b/include/asm-arm/arch-mx35/sdhc.h deleted file mode 100644 index 5514ad4..0000000 --- a/include/asm-arm/arch-mx35/sdhc.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef SDHC_H -#define SDHC_H - -#include <linux/types.h> - -#define ESDHC_SOFTWARE_RESET_DATA ((u32)0x04000000) -#define ESDHC_SOFTWARE_RESET_CMD ((u32)0x02000000) -#define ESDHC_SOFTWARE_RESET ((u32)0x01000000) -#define ESDHC_CMD_INHIBIT 0x00000003 -#define ESDHC_SYSCTL_INITA ((u32)0x08000000) -#define ESDHC_LITTLE_ENDIAN_MODE ((u32)0x00000020) -#define ESDHC_HW_BIG_ENDIAN_MODE ((u32)0x00000010) -#define ESDHC_BIG_ENDIAN_MODE ((u32)0x00000000) -#define ESDHC_ONE_BIT_SUPPORT ((u32)0x00000000) -#define ESDHC_FOUR_BIT_SUPPORT ((u32)0x00000002) -#define ESDHC_EIGHT_BIT_SUPPORT ((u32)0x00000004) -#define ESDHC_CLOCK_ENABLE 0x00000007 -#define ESDHC_FREQ_MASK 0xffff0007 -#define ESDHC_SYSCTL_FREQ_MASK ((u32)0x000FFFF0) -#define ESDHC_SYSCTL_IDENT_FREQ_TO1 ((u32)0x0000800e) -#define ESDHC_SYSCTL_OPERT_FREQ_TO1 ((u32)0x00000200) -#define ESDHC_SYSCTL_IDENT_FREQ_TO2 ((u32)0x00002040) -#define ESDHC_SYSCTL_OPERT_FREQ_TO2 ((u32)0x00000050) -#define ESDHC_INTERRUPT_ENABLE ((u32)0x007f0133) -#define ESDHC_CLEAR_INTERRUPT ((u32)0x117f01ff) -#define ESDHC_SYSCTL_DTOCV_VAL ((u32)0x000E0000) -#define ESDHC_IRQSTATEN_DTOESEN ((u32)0x00100000) -#define ESDHC_ENDIAN_MODE_MASK ((u32)0x00000030) -#define ESDHC_SYSCTRL_RSTC ((u32)0x02000000) -#define ESDHC_SYSCTRL_RSTD ((u32)0x04000000) -#define ESDHC_CONFIG_BLOCK 0x00010200 -#define ESDHC_OPER_TIMEOUT (96 * 100) -#define ESDHC_ACMD41_TIMEOUT (32000) -#define ESDHC_CMD1_TIMEOUT (32000) -#define ESDHC_BLOCK_SHIFT (16) -#define ESDHC_CARD_INIT_TIMEOUT (64) - -#define ESDHC_SYSCTL_SDCLKEN_MASK ((u32)0x00000008) -#define ESDHC_PRSSTAT_SDSTB_BIT ((u32)0x00000008) -#define ESDHC_SYSCTL_INPUT_CLOCK_MASK ((u32)0x00000007) - -#define ESDHC_BUS_WIDTH_MASK ((u32)0x00000006) -#define ESDHC_DATA_TRANSFER_SHIFT (4) -#define ESDHC_RESPONSE_FORMAT_SHIFT (16) -#define ESDHC_DATA_PRESENT_SHIFT (21) -#define ESDHC_CRC_CHECK_SHIFT (19) -#define ESDHC_CMD_INDEX_CHECK_SHIFT (20) -#define ESDHC_CMD_INDEX_SHIFT (24) -#define ESDHC_BLOCK_COUNT_ENABLE_SHIFT (1) -#define ESDHC_MULTI_SINGLE_BLOCK_SELECT_SHIFT (5) -#define BLK_LEN (512) -#define ESDHC_READ_WATER_MARK_LEVEL_BL_4 ((u32)0x00000001) -#define ESDHC_READ_WATER_MARK_LEVEL_BL_8 ((u32)0x00000002) -#define ESDHC_READ_WATER_MARK_LEVEL_BL_16 ((u32)0x00000004) -#define ESDHC_READ_WATER_MARK_LEVEL_BL_64 ((u32)0x00000010) -#define ESDHC_READ_WATER_MARK_LEVEL_BL_512 ((u32)0x00000080) - -#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_4 ((u32)0x00010000) -#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_8 ((u32)0x00020000) -#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_16 ((u32)0x00040000) -#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_64 ((u32)0x00100000) -#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_512 ((u32)0x00800000) - -#define WRITE_READ_WATER_MARK_LEVEL 0x00800080 - -/* Present State register bit masks */ -#define ESDHC_PRESENT_STATE_CIHB ((u32)0x00000001) -#define ESDHC_PRESENT_STATE_CDIHB ((u32)0x00000002) -#define ONE (1) -#define ESDHC_FIFO_SIZE (128) - -#define ESDHC_STATUS_END_CMD_RESP_MSK ((u32)0x00000001) -#define ESDHC_STATUS_END_CMD_RESP_TIME_MSK ((u32)0x000F0001) -#define ESDHC_STATUS_TIME_OUT_RESP_MSK ((u32)0x00010000) -#define ESDHC_STATUS_RESP_CRC_ERR_MSK ((u32)0x00020000) -#define ESDHC_STATUS_RESP_CMD_INDEX_ERR_MSK ((u32)0x00080000) -#define ESDHC_STATUS_BUF_READ_RDY_MSK ((u32)0x00000020) -#define ESDHC_STATUS_BUF_WRITE_RDY_MSK ((u32)0x00000010) -#define ESDHC_STATUS_TRANSFER_COMPLETE_MSK ((u32)0x00000002) -#define ESDHC_STATUS_DATA_RW_MSK ((u32)0x00700002) -#define ESDHC_STATUS_TRANSFER_COMPLETE_MSK ((u32)0x00000002) -#define ESDHC_STATUS_TIME_OUT_READ_MASK ((u32)0x00100000) -#define ESDHC_STATUS_READ_CRC_ERR_MSK ((u32)0x00200000) -#define ESDHC_STATUS_RESP_CMD_END_BIT_ERR_MSK ((u32)0x00040000) -#define ESDHC_STATUS_RW_DATA_END_BIT_ERR_MSK ((u32)0x00400000) - -#define ESDHC_STATUS_TIME_OUT_READ (3200) -#define ESDHC_READ_DATA_TIME_OUT (3200) -#define ESDHC_WRITE_DATA_TIME_OUT (8000) - -#define ESDHC_CONFIG_BLOCK_512 ((u32)0x00000200) -#define ESDHC_CONFIG_BLOCK_64 ((u32)0x00000040) -#define ESDHC_CONFIG_BLOCK_8 ((u32)0x00000008) -#define ESDHC_CONFIG_BLOCK_4 ((u32)0x00000004) - -#define ESDHC_MAX_BLOCK_COUNT ((u32)0x0000ffff) - -typedef enum { - ESDHC1, - ESDHC2, - ESDHC3 -} esdhc_num_t; - -typedef enum { - WRITE, - READ, -} xfer_type_t; - -typedef enum { - RESPONSE_NONE, - RESPONSE_136, - RESPONSE_48, - RESPONSE_48_CHECK_BUSY -} response_format_t; - - -typedef enum { - DATA_PRESENT_NONE, - DATA_PRESENT -} data_present_select; - -typedef enum { - DISABLE, - ENABLE -} crc_check_enable, cmdindex_check_enable, block_count_enable; - -typedef enum { - SINGLE, - MULTIPLE -} multi_single_block_select; - -typedef struct { - u32 command; - u32 arg; - xfer_type_t data_transfer; - response_format_t response_format; - data_present_select data_present; - crc_check_enable crc_check; - cmdindex_check_enable cmdindex_check; - block_count_enable block_count_enable_check; - multi_single_block_select multi_single_block; -} esdhc_cmd_t; - -typedef struct { - response_format_t format; - u32 cmd_rsp0; - u32 cmd_rsp1; - u32 cmd_rsp2; - u32 cmd_rsp3; -} esdhc_resp_t; - -typedef enum { - BIG_ENDIAN, - HALF_WORD_BIG_ENDIAN, - LITTLE_ENDIAN -} endian_mode_t; - -typedef enum { - OPERATING_FREQ = 20000, /* in kHz */ - IDENTIFICATION_FREQ = 400 /* in kHz */ -} sdhc_freq_t; - -enum esdhc_data_status { - ESDHC_DATA_ERR = 3, - ESDHC_DATA_OK = 4 -}; - -enum esdhc_int_cntr_val { - ESDHC_INT_CNTR_END_CD_RESP = 0x4, - ESDHC_INT_CNTR_BUF_WR_RDY = 0x8 -}; - -enum esdhc_reset_status { - ESDHC_WRONG_RESET = 0, - ESDHC_CORRECT_RESET = 1 -}; - -typedef enum { - WEAK = 0, - STRONG = 1 -} esdhc_pullup_t; - -extern u32 interface_reset(void); -extern void interface_configure_clock(sdhc_freq_t); -extern void interface_read_response(esdhc_resp_t *); -extern u32 interface_send_cmd_wait_resp(esdhc_cmd_t *); -extern u32 interface_data_read(u32 *, u32); -extern void interface_config_block_info(u32, u32, u32); -extern u32 interface_data_write(u32 *, u32); -extern void interface_clear_interrupt(void); -extern void interface_initialization_active(void); -extern void esdhc_set_cmd_pullup(esdhc_pullup_t pull_up); -extern void esdhc_soft_reset(u32 mask); -extern u32 interface_set_bus_width(u32 bus_width); -/*================================================================================================*/ -#endif /* ESDHC_H */ diff --git a/include/asm-arm/arch-mx51/mmc.h b/include/asm-arm/arch-mx51/mmc.h deleted file mode 100644 index 062c568..0000000 --- a/include/asm-arm/arch-mx51/mmc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * linux/drivers/mmc/mmc.h - * - * Author: Vladimir Shebordaev, Igor Oblakov - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __MMC_MX51_3STACK_H__ -#define __MMC_MX51_3STACK_H__ - -#endif /* __MMC_MX51_3STACK_H__ */ diff --git a/include/asm-arm/arch-mx51/mx51.h b/include/asm-arm/arch-mx51/mx51.h index 533919a..1014d41 100644 --- a/include/asm-arm/arch-mx51/mx51.h +++ b/include/asm-arm/arch-mx51/mx51.h @@ -407,6 +407,32 @@ MXC_IPG_PERCLK, MXC_UART_CLK, MXC_CSPI_CLK, MXC_FEC_CLK, +MXC_ESDHC_CLK, +}; + +/* +enum mxc_main_clocks { + MXC_CPU_CLK, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PER_CLK, + MXC_DDR_CLK, + MXC_NFC_CLK, + MXC_USB_CLK, +}; +*/ + +enum mxc_peri_clocks { + MXC_UART1_BAUD, + MXC_UART2_BAUD, + MXC_UART3_BAUD, + MXC_SSI1_BAUD, + MXC_SSI2_BAUD, + MXC_CSI_BAUD, + MXC_MSTICK1_CLK, + MXC_MSTICK2_CLK, + MXC_SPI1_CLK, + MXC_SPI2_CLK, }; extern unsigned int mxc_get_clock(enum mxc_clock clk); diff --git a/include/asm-arm/arch-mx51/sdhc.h b/include/asm-arm/arch-mx51/sdhc.h deleted file mode 100644 index 5514ad4..0000000 --- a/include/asm-arm/arch-mx51/sdhc.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef SDHC_H -#define SDHC_H - -#include <linux/types.h> - -#define ESDHC_SOFTWARE_RESET_DATA ((u32)0x04000000) -#define ESDHC_SOFTWARE_RESET_CMD ((u32)0x02000000) -#define ESDHC_SOFTWARE_RESET ((u32)0x01000000) -#define ESDHC_CMD_INHIBIT 0x00000003 -#define ESDHC_SYSCTL_INITA ((u32)0x08000000) -#define ESDHC_LITTLE_ENDIAN_MODE ((u32)0x00000020) -#define ESDHC_HW_BIG_ENDIAN_MODE ((u32)0x00000010) -#define ESDHC_BIG_ENDIAN_MODE ((u32)0x00000000) -#define ESDHC_ONE_BIT_SUPPORT ((u32)0x00000000) -#define ESDHC_FOUR_BIT_SUPPORT ((u32)0x00000002) -#define ESDHC_EIGHT_BIT_SUPPORT ((u32)0x00000004) -#define ESDHC_CLOCK_ENABLE 0x00000007 -#define ESDHC_FREQ_MASK 0xffff0007 -#define ESDHC_SYSCTL_FREQ_MASK ((u32)0x000FFFF0) -#define ESDHC_SYSCTL_IDENT_FREQ_TO1 ((u32)0x0000800e) -#define ESDHC_SYSCTL_OPERT_FREQ_TO1 ((u32)0x00000200) -#define ESDHC_SYSCTL_IDENT_FREQ_TO2 ((u32)0x00002040) -#define ESDHC_SYSCTL_OPERT_FREQ_TO2 ((u32)0x00000050) -#define ESDHC_INTERRUPT_ENABLE ((u32)0x007f0133) -#define ESDHC_CLEAR_INTERRUPT ((u32)0x117f01ff) -#define ESDHC_SYSCTL_DTOCV_VAL ((u32)0x000E0000) -#define ESDHC_IRQSTATEN_DTOESEN ((u32)0x00100000) -#define ESDHC_ENDIAN_MODE_MASK ((u32)0x00000030) -#define ESDHC_SYSCTRL_RSTC ((u32)0x02000000) -#define ESDHC_SYSCTRL_RSTD ((u32)0x04000000) -#define ESDHC_CONFIG_BLOCK 0x00010200 -#define ESDHC_OPER_TIMEOUT (96 * 100) -#define ESDHC_ACMD41_TIMEOUT (32000) -#define ESDHC_CMD1_TIMEOUT (32000) -#define ESDHC_BLOCK_SHIFT (16) -#define ESDHC_CARD_INIT_TIMEOUT (64) - -#define ESDHC_SYSCTL_SDCLKEN_MASK ((u32)0x00000008) -#define ESDHC_PRSSTAT_SDSTB_BIT ((u32)0x00000008) -#define ESDHC_SYSCTL_INPUT_CLOCK_MASK ((u32)0x00000007) - -#define ESDHC_BUS_WIDTH_MASK ((u32)0x00000006) -#define ESDHC_DATA_TRANSFER_SHIFT (4) -#define ESDHC_RESPONSE_FORMAT_SHIFT (16) -#define ESDHC_DATA_PRESENT_SHIFT (21) -#define ESDHC_CRC_CHECK_SHIFT (19) -#define ESDHC_CMD_INDEX_CHECK_SHIFT (20) -#define ESDHC_CMD_INDEX_SHIFT (24) -#define ESDHC_BLOCK_COUNT_ENABLE_SHIFT (1) -#define ESDHC_MULTI_SINGLE_BLOCK_SELECT_SHIFT (5) -#define BLK_LEN (512) -#define ESDHC_READ_WATER_MARK_LEVEL_BL_4 ((u32)0x00000001) -#define ESDHC_READ_WATER_MARK_LEVEL_BL_8 ((u32)0x00000002) -#define ESDHC_READ_WATER_MARK_LEVEL_BL_16 ((u32)0x00000004) -#define ESDHC_READ_WATER_MARK_LEVEL_BL_64 ((u32)0x00000010) -#define ESDHC_READ_WATER_MARK_LEVEL_BL_512 ((u32)0x00000080) - -#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_4 ((u32)0x00010000) -#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_8 ((u32)0x00020000) -#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_16 ((u32)0x00040000) -#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_64 ((u32)0x00100000) -#define ESDHC_WRITE_WATER_MARK_LEVEL_BL_512 ((u32)0x00800000) - -#define WRITE_READ_WATER_MARK_LEVEL 0x00800080 - -/* Present State register bit masks */ -#define ESDHC_PRESENT_STATE_CIHB ((u32)0x00000001) -#define ESDHC_PRESENT_STATE_CDIHB ((u32)0x00000002) -#define ONE (1) -#define ESDHC_FIFO_SIZE (128) - -#define ESDHC_STATUS_END_CMD_RESP_MSK ((u32)0x00000001) -#define ESDHC_STATUS_END_CMD_RESP_TIME_MSK ((u32)0x000F0001) -#define ESDHC_STATUS_TIME_OUT_RESP_MSK ((u32)0x00010000) -#define ESDHC_STATUS_RESP_CRC_ERR_MSK ((u32)0x00020000) -#define ESDHC_STATUS_RESP_CMD_INDEX_ERR_MSK ((u32)0x00080000) -#define ESDHC_STATUS_BUF_READ_RDY_MSK ((u32)0x00000020) -#define ESDHC_STATUS_BUF_WRITE_RDY_MSK ((u32)0x00000010) -#define ESDHC_STATUS_TRANSFER_COMPLETE_MSK ((u32)0x00000002) -#define ESDHC_STATUS_DATA_RW_MSK ((u32)0x00700002) -#define ESDHC_STATUS_TRANSFER_COMPLETE_MSK ((u32)0x00000002) -#define ESDHC_STATUS_TIME_OUT_READ_MASK ((u32)0x00100000) -#define ESDHC_STATUS_READ_CRC_ERR_MSK ((u32)0x00200000) -#define ESDHC_STATUS_RESP_CMD_END_BIT_ERR_MSK ((u32)0x00040000) -#define ESDHC_STATUS_RW_DATA_END_BIT_ERR_MSK ((u32)0x00400000) - -#define ESDHC_STATUS_TIME_OUT_READ (3200) -#define ESDHC_READ_DATA_TIME_OUT (3200) -#define ESDHC_WRITE_DATA_TIME_OUT (8000) - -#define ESDHC_CONFIG_BLOCK_512 ((u32)0x00000200) -#define ESDHC_CONFIG_BLOCK_64 ((u32)0x00000040) -#define ESDHC_CONFIG_BLOCK_8 ((u32)0x00000008) -#define ESDHC_CONFIG_BLOCK_4 ((u32)0x00000004) - -#define ESDHC_MAX_BLOCK_COUNT ((u32)0x0000ffff) - -typedef enum { - ESDHC1, - ESDHC2, - ESDHC3 -} esdhc_num_t; - -typedef enum { - WRITE, - READ, -} xfer_type_t; - -typedef enum { - RESPONSE_NONE, - RESPONSE_136, - RESPONSE_48, - RESPONSE_48_CHECK_BUSY -} response_format_t; - - -typedef enum { - DATA_PRESENT_NONE, - DATA_PRESENT -} data_present_select; - -typedef enum { - DISABLE, - ENABLE -} crc_check_enable, cmdindex_check_enable, block_count_enable; - -typedef enum { - SINGLE, - MULTIPLE -} multi_single_block_select; - -typedef struct { - u32 command; - u32 arg; - xfer_type_t data_transfer; - response_format_t response_format; - data_present_select data_present; - crc_check_enable crc_check; - cmdindex_check_enable cmdindex_check; - block_count_enable block_count_enable_check; - multi_single_block_select multi_single_block; -} esdhc_cmd_t; - -typedef struct { - response_format_t format; - u32 cmd_rsp0; - u32 cmd_rsp1; - u32 cmd_rsp2; - u32 cmd_rsp3; -} esdhc_resp_t; - -typedef enum { - BIG_ENDIAN, - HALF_WORD_BIG_ENDIAN, - LITTLE_ENDIAN -} endian_mode_t; - -typedef enum { - OPERATING_FREQ = 20000, /* in kHz */ - IDENTIFICATION_FREQ = 400 /* in kHz */ -} sdhc_freq_t; - -enum esdhc_data_status { - ESDHC_DATA_ERR = 3, - ESDHC_DATA_OK = 4 -}; - -enum esdhc_int_cntr_val { - ESDHC_INT_CNTR_END_CD_RESP = 0x4, - ESDHC_INT_CNTR_BUF_WR_RDY = 0x8 -}; - -enum esdhc_reset_status { - ESDHC_WRONG_RESET = 0, - ESDHC_CORRECT_RESET = 1 -}; - -typedef enum { - WEAK = 0, - STRONG = 1 -} esdhc_pullup_t; - -extern u32 interface_reset(void); -extern void interface_configure_clock(sdhc_freq_t); -extern void interface_read_response(esdhc_resp_t *); -extern u32 interface_send_cmd_wait_resp(esdhc_cmd_t *); -extern u32 interface_data_read(u32 *, u32); -extern void interface_config_block_info(u32, u32, u32); -extern u32 interface_data_write(u32 *, u32); -extern void interface_clear_interrupt(void); -extern void interface_initialization_active(void); -extern void esdhc_set_cmd_pullup(esdhc_pullup_t pull_up); -extern void esdhc_soft_reset(u32 mask); -extern u32 interface_set_bus_width(u32 bus_width); -/*================================================================================================*/ -#endif /* ESDHC_H */ diff --git a/include/configs/mx25_3stack.h b/include/configs/mx25_3stack.h index 93e4b9a..2943479 100644 --- a/include/configs/mx25_3stack.h +++ b/include/configs/mx25_3stack.h @@ -96,17 +96,21 @@ /* #define CONFIG_CMD_SPI */ /* #define CONFIG_CMD_DATE */ #define CONFIG_CMD_NAND +/* #define CONFIG_CMD_MMC */ /* * MMC Configs * */ /* -#define CONFIG_FSL_MMC -#define CONFIG_MMC -#define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_FAT -#define CONFIG_MMC_BASE 0x0 */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_MMC_BASE 0x0 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 +#endif +*/ /* Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require * that CONFIG_NO_FLASH is undefined). @@ -128,9 +132,9 @@ "tftpboot 0x81000000 uImage; bootm\0" /*Support LAN9217*/ -/*#define CONFIG_DRIVER_SMC911X 1 -#define CONFIG_DRIVER_SMC911X_16_BIT 1 -#define CONFIG_DRIVER_SMC911X_BASE CS5_BASE*/ +/*#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE CS5_BASE*/ /*#define CONFIG_HAS_ETH1*/ #define CONFIG_CMD_NET @@ -189,13 +193,8 @@ #endif /* Monitor at beginning of flash */ -#if defined(CONFIG_FSL_SF) - #define CONFIG_FSL_ENV_IN_SF -#elif defined(CONFIG_FSL_MMC) - #define CONFIG_FSL_ENV_IN_MMC -#elif defined(CONFIG_CMD_NAND) - #define CONFIG_FSL_ENV_IN_NAND -#endif +/* #define CONFIG_FSL_ENV_IN_MMC */ +#define CONFIG_FSL_ENV_IN_NAND /*----------------------------------------------------------------------- * FLASH and environment organization @@ -206,10 +205,6 @@ #elif defined(CONFIG_FSL_ENV_IN_MMC) #define CONFIG_ENV_IS_IN_MMC 1 #define CONFIG_ENV_OFFSET (768 * 1024) -#elif defined(CONFIG_FSL_ENV_IN_SF) - #define CONFIG_ENV_IS_IN_SPI_FLASH 1 - #define CONFIG_ENV_SPI_CS 1 - #define CONFIG_ENV_OFFSET (768 * 1024) #else #define CONFIG_ENV_IS_NOWHERE 1 #endif diff --git a/include/configs/mx31_3stack.h b/include/configs/mx31_3stack.h index e7b6f89..d7629b2 100644 --- a/include/configs/mx31_3stack.h +++ b/include/configs/mx31_3stack.h @@ -50,9 +50,8 @@ /* * Hardware drivers */ - -#define CONFIG_MX31_UART 1 -#define CONFIG_SYS_MX31_UART1 1 +#define CONFIG_MXC_UART 1 +#define CONFIG_SYS_MX31_UART1 1 #define CONFIG_MXC_SPI 1 @@ -99,9 +98,10 @@ "tftpboot ${loadaddr} ${tftp_server}:${kernel}; bootm\0" /* configure for smc91xx debug board ethernet */ -#define CONFIG_DRIVER_SMC911X 1 -#define CONFIG_DRIVER_SMC911X_16_BIT 1 -#define CONFIG_DRIVER_SMC911X_BASE CS5_BASE +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE CS5_BASE #define CONFIG_ARP_TIMEOUT 200UL diff --git a/include/configs/mx35_3stack.h b/include/configs/mx35_3stack.h index e0181d1..4140a86 100644 --- a/include/configs/mx35_3stack.h +++ b/include/configs/mx35_3stack.h @@ -90,6 +90,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_MII +#define CONFIG_CMD_NET #define CONFIG_BOOTDELAY 3 @@ -115,9 +116,9 @@ "setenv filesize; saveenv\0" /*Support LAN9217*/ -#define CONFIG_DRIVER_SMC911X 1 -#define CONFIG_DRIVER_SMC911X_16_BIT 1 -#define CONFIG_DRIVER_SMC911X_BASE CS5_BASE_ADDR +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE CS5_BASE_ADDR #define CONFIG_HAS_ETH1 #define CONFIG_NET_MULTI 1 diff --git a/include/configs/mx35_3stack_mmc.h b/include/configs/mx35_3stack_mmc.h index 1676004..e1d5d75 100644 --- a/include/configs/mx35_3stack_mmc.h +++ b/include/configs/mx35_3stack_mmc.h @@ -86,6 +86,8 @@ /*#define CONFIG_CMD_SPI*/ /*#define CONFIG_CMD_DATE*/ /*#define CONFIG_CMD_NAND*/ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MMC #define CONFIG_CMD_I2C #define CONFIG_CMD_MII @@ -114,9 +116,9 @@ "setenv filesize; saveenv\0" /*Support LAN9217*/ -#define CONFIG_DRIVER_SMC911X 1 -#define CONFIG_DRIVER_SMC911X_16_BIT 1 -#define CONFIG_DRIVER_SMC911X_BASE CS5_BASE_ADDR +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE CS5_BASE_ADDR #define CONFIG_HAS_ETH1 #define CONFIG_NET_MULTI 1 @@ -181,9 +183,14 @@ /* * MMC Configs * */ -#define CONFIG_FSL_MMC -#define CONFIG_MMC 1 -#define CONFIG_CMD_MMC +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_MMC_BASE 0x0 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 +#endif #define CONFIG_FLASH_HEADER 1 #define CONFIG_FLASH_HEADER_OFFSET 0x400 @@ -191,7 +198,6 @@ #define CONFIG_DOS_PARTITION 1 #define CONFIG_CMD_FAT 1 -#define CONFIG_MMC_BASE 0x0 /*----------------------------------------------------------------------- * FLASH and environment organization diff --git a/include/configs/mx51_3stack.h b/include/configs/mx51_3stack.h index 236de3c..e0fa523 100644 --- a/include/configs/mx51_3stack.h +++ b/include/configs/mx51_3stack.h @@ -83,23 +83,27 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP /* Enable below configure when supporting nand */ -/* #define CONFIG_CMD_NAND */ +#define CONFIG_CMD_NAND #define CONFIG_MXC_NAND #define CONFIG_CMD_ENV +#define CMD_SAVEENV #undef CONFIG_CMD_IMLS #define CONFIG_CMD_MII #define CONFIG_CMD_NET +#define CONFIG_NET_MULTI +#define CONFIG_CMD_MMC /* * MMC Configs */ -#define CONFIG_FSL_MMC 1 - -#define CONFIG_MMC 1 -#define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_CMD_FAT 1 -#define CONFIG_MMC_BASE 0x0 +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_MMC_BASE 0x0 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 +#endif /* * I2C Configs @@ -135,9 +139,9 @@ "setenv filesize; saveenv\0" /*Support LAN9217*/ -#define CONFIG_DRIVER_SMC911X 1 -#define CONFIG_DRIVER_SMC911X_16_BIT 1 -#define CONFIG_DRIVER_SMC911X_BASE_VARIABLE mx51_io_base_addr +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE mx51_io_base_addr /* * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under @@ -203,7 +207,9 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 /* Monitor at beginning of flash */ -#define CONFIG_FSL_ENV_IN_MMC +#define CONFIG_FSL_ENV_IN_NAND +/* #define CONFIG_FSL_ENV_IN_NAND */ + #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE #if defined(CONFIG_FSL_ENV_IN_NAND) diff --git a/include/configs/mx51_3stack_android.h b/include/configs/mx51_3stack_android.h index 153993b..a4c1004 100644 --- a/include/configs/mx51_3stack_android.h +++ b/include/configs/mx51_3stack_android.h @@ -84,30 +84,6 @@ #define MAX_SPI_BYTES (64 * 4) */ -/* - * MMC Configs - * */ -#define CONFIG_FSL_MMC 1 - -#define CONFIG_MMC 1 -#define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_CMD_FAT 1 -#define CONFIG_MMC_BASE 0x0 - -/* - * Eth Configs - */ -#define CONFIG_HAS_ETH1 -#define CONFIG_NET_MULTI 1 -#define CONFIG_MXC_FEC -#define CONFIG_MII -#define CONFIG_DISCOVER_PHY - -#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR -#define CONFIG_FEC0_PINMUX -1 -#define CONFIG_FEC0_PHY_ADDR 0x1F -#define CONFIG_FEC0_MIIBASE -1 #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP @@ -134,7 +110,9 @@ #define CONFIG_ANDROID_NORMAL_BOOTARGS "ip=dhcp mem=480M init=/init wvga calibration" #define CONFIG_ANDROID_RECOVERY_BOOTARGS "setenv bootargs ${bootargs} root=/dev/mmcblk0p4 ip=dhcp init=/init rootfstype=ext3 wvga" #define CONFIG_ANDROID_RECOVERY_BOOTCMD "run bootargs_base bootargs_android;mmcinit;cp.b 0x100000 ${loadaddr} 0x250000;bootm" +#define CONFIG_ANDROID_RECOVERY_CMD_FILE "/cache/recovery/command" #define CONFIG_ANDROID_BOOTMOD_DELAY 3 +#define CONFIG_ANDROID_CACHE_PARTITION 4 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -153,6 +131,7 @@ /* Enable below configure when supporting nand */ #define CONFIG_CMD_NAND #define CONFIG_MXC_NAND +#define CONFIG_CMD_MMC #define CONFIG_CMD_ENV #undef CONFIG_CMD_IMLS @@ -190,9 +169,35 @@ "setenv filesize; saveenv\0" /*Support LAN9217*/ -#define CONFIG_DRIVER_SMC911X 1 -#define CONFIG_DRIVER_SMC911X_16_BIT 1 -#define CONFIG_DRIVER_SMC911X_BASE_VARIABLE mx51_io_base_addr +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE mx51_io_base_addr + +/* + * MMC Configs + * */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_MMC_BASE 0x0 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 +#endif + +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR 0x1F +#define CONFIG_FEC0_MIIBASE -1 /* * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under @@ -258,13 +263,8 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 /* Monitor at beginning of flash */ -#if defined(CONFIG_FSL_SF) - #define CONFIG_FSL_ENV_IN_SF -#elif defined(CONFIG_FSL_MMC) - #define CONFIG_FSL_ENV_IN_MMC -#elif defined(CONFIG_CMD_NAND) - #define CONFIG_FSL_ENV_IN_NAND -#endif +/* #define CONFIG_FSL_ENV_IN_MMC */ +#define CONFIG_FSL_ENV_IN_NAND #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE diff --git a/include/configs/imx51.h b/include/configs/mx51_bbg.h index e5ae114..dd4727d 100644 --- a/include/configs/imx51.h +++ b/include/configs/mx51_bbg.h @@ -71,8 +71,6 @@ * SPI Configs * */ #define CONFIG_FSL_SF 1 -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_IMX_ATMEL 1 #define CONFIG_SPI_FLASH_CS 1 #define CONFIG_IMX_SPI @@ -115,6 +113,50 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII #define CONFIG_CMD_NET +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_MMC + +/* + * SPI Configs + * */ +#ifdef CONFIG_CMD_SF + #define CONFIG_FSL_SF 1 + #define CONFIG_SPI_FLASH_IMX_ATMEL 1 + #define CONFIG_SPI_FLASH_CS 1 + #define CONFIG_IMX_SPI + #define CONFIG_IMX_SPI_PMIC + #define CONFIG_IMX_SPI_PMIC_CS 0 + + #define MAX_SPI_BYTES (64 * 4) +#endif + +/* + * MMC Configs + * */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_MMC_BASE 0x0 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 +#endif +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR 0x1F +#define CONFIG_FEC0_MIIBASE -1 + + /* Enable below configure when supporting nand */ #define CONFIG_CMD_ENV @@ -205,13 +247,9 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 /* Monitor at beginning of flash */ -#if defined(CONFIG_FSL_SF) - #define CONFIG_FSL_ENV_IN_SF -#elif defined(CONFIG_FSL_MMC) - #define CONFIG_FSL_ENV_IN_MMC -#elif defined(CONFIG_CMD_NAND) - #define CONFIG_FSL_ENV_IN_NAND -#endif +/* #define CONFIG_FSL_ENV_IN_SF */ +#define CONFIG_FSL_ENV_IN_MMC +/* #define CONFIG_FSL_ENV_IN_NAND */ #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE diff --git a/include/configs/imx51_android.h b/include/configs/mx51_bbg_android.h index 55bcfbf..d49e039 100644 --- a/include/configs/imx51_android.h +++ b/include/configs/mx51_bbg_android.h @@ -68,44 +68,6 @@ #define CONFIG_MX51_UART 1 #define CONFIG_MX51_UART1 1 -/* - * SPI Configs - * */ -#define CONFIG_FSL_SF 1 -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_IMX_ATMEL 1 -#define CONFIG_SPI_FLASH_CS 1 -#define CONFIG_IMX_SPI -#define CONFIG_IMX_SPI_PMIC -#define CONFIG_IMX_SPI_PMIC_CS 0 - -#define MAX_SPI_BYTES (64 * 4) - -/* - * MMC Configs - * */ -#define CONFIG_FSL_MMC 1 - -#define CONFIG_MMC 1 -#define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_CMD_FAT 1 -#define CONFIG_MMC_BASE 0x0 - -/* - * Eth Configs - */ -#define CONFIG_HAS_ETH1 -#define CONFIG_NET_MULTI 1 -#define CONFIG_MXC_FEC -#define CONFIG_MII -#define CONFIG_DISCOVER_PHY - -#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR -#define CONFIG_FEC0_PINMUX -1 -#define CONFIG_FEC0_PHY_ADDR 0x1F -#define CONFIG_FEC0_MIIBASE -1 #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP @@ -138,8 +100,10 @@ #define CONFIG_MXC_KPD_ROWMAX 4 #define CONFIG_ANDROID_NORMAL_BOOTARGS "ip=dhcp mem=480M init=/init wvga calibration" #define CONFIG_ANDROID_RECOVERY_BOOTARGS "setenv bootargs ${bootargs} root=/dev/mmcblk0p4 ip=dhcp init=/init rootfstype=ext3 wvga" -#define CONFIG_ANDROID_RECOVERY_BOOTCMD "run bootargs_base bootargs_android;mmcinit;cp.b 0x100000 ${loadaddr} 0x250000;bootm" +#define CONFIG_ANDROID_RECOVERY_BOOTCMD "run bootargs_base bootargs_android;mmc read 0 ${loadaddr} 0x800 0x1280;bootm" +#define CONFIG_ANDROID_RECOVERY_CMD_FILE "/cache/recovery/command" #define CONFIG_ANDROID_BOOTMOD_DELAY 3 +#define CONFIG_ANDROID_CACHE_PARTITION 4 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -157,6 +121,7 @@ #define CONFIG_CMD_DHCP /* Enable below configure when supporting nand */ /* #define CONFIG_CMD_NAND */ +#define CONFIG_CMD_MMC #define CONFIG_CMD_ENV #undef CONFIG_CMD_IMLS @@ -195,9 +160,9 @@ /*Support LAN9217*/ /* -#define CONFIG_DRIVER_SMC911X 1 -#define CONFIG_DRIVER_SMC911X_16_BIT 1 -#define CONFIG_DRIVER_SMC911X_BASE_VARIABLE mx51_io_base_addr +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE mx51_io_base_addr */ /* @@ -235,6 +200,46 @@ #define CONFIG_CMDLINE_EDITING 1 +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_MXC_FEC +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_PHY_ADDR 0x1F +#define CONFIG_FEC0_MIIBASE -1 + +/* + * SPI Configs + * */ +#define CONFIG_FSL_SF 1 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_IMX_ATMEL 1 +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_SPI +#define CONFIG_IMX_SPI_PMIC +#define CONFIG_IMX_SPI_PMIC_CS 0 + +#define MAX_SPI_BYTES (64 * 4) + +/* + * MMC Configs + * */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_MMC_BASE 0x0 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 +#endif /*----------------------------------------------------------------------- * Stack sizes * @@ -264,13 +269,9 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 /* Monitor at beginning of flash */ -#if defined(CONFIG_FSL_SF) - #define CONFIG_FSL_ENV_IN_SF -#elif defined(CONFIG_FSL_MMC) - #define CONFIG_FSL_ENV_IN_MMC -#elif defined(CONFIG_CMD_NAND) - #define CONFIG_FSL_ENV_IN_NAND -#endif +/* #define CONFIG_FSL_ENV_IN_SF */ +#define CONFIG_FSL_ENV_IN_MMC +/* #define CONFIG_FSL_ENV_IN_NAND */ #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 89b8304..f3c38e6 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -30,9 +30,11 @@ /* FSL eSDHC-specific constants */ #define SYSCTL 0x0002e02c +#define SYSCTL_RSTA 0x01000000 #define SYSCTL_INITA 0x08000000 #define SYSCTL_TIMEOUT_MASK 0x000f0000 -#define SYSCTL_CLOCK_MASK 0x00000fff +#define SYSCTL_CLOCK_MASK 0x0000fff0 +#define SYSCTL_SDCLKEN 0x00000008 #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 @@ -86,6 +88,7 @@ #define PRSSTAT_CDPL (0x00040000) #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) +#define PRSSTAT_SDSTB (0x00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) #define PRSSTAT_CIDHB (0x00000001) @@ -94,6 +97,7 @@ #define PROCTL_INIT 0x00000020 #define PROCTL_DTW_4 0x00000002 #define PROCTL_DTW_8 0x00000004 +#define PROCTL_D3CD 0x00000008 #define CMDARG 0x0002e008 @@ -142,7 +146,7 @@ #define ESDHC_HOSTCAPBLT_DMAS 0x00400000 #define ESDHC_HOSTCAPBLT_HSS 0x00200000 -#ifdef CONFIG_FSL_ESDHC +#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_IMX_MMC) int fsl_esdhc_mmc_init(bd_t *bis); void fdt_fixup_esdhc(void *blob, bd_t *bd); #else diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h deleted file mode 100644 index 393d587..0000000 --- a/include/linux/mmc/card.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * linux/include/linux/mmc/card.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Card driver specific definitions. - */ -#ifndef LINUX_MMC_CARD_H -#define LINUX_MMC_CARD_H - -#include "core.h" - -struct mmc_cid { - unsigned int manfid; - char prod_name[8]; - unsigned int serial; - union { - unsigned short mmc_id; - char sd_id[2]; - } oemid; - unsigned short year; - unsigned char hwrev; - unsigned char fwrev; - unsigned char month; -}; - -struct mmc_csd { - unsigned char mmca_vsn; - unsigned short cmdclass; - unsigned short tacc_clks; - unsigned int tacc_ns; - unsigned int r2w_factor; - unsigned int max_dtr; - unsigned int read_blkbits; - unsigned int write_blkbits; - unsigned int capacity; - unsigned int read_partial:1, - read_misalign:1, - write_partial:1, - write_misalign:1; -}; - -struct mmc_ext_csd { - unsigned int hs_max_dtr; - unsigned int sectors; -}; - -struct sd_scr { - unsigned char sda_vsn; - unsigned char bus_widths; -#define SD_SCR_BUS_WIDTH_1 (1<<0) -#define SD_SCR_BUS_WIDTH_4 (1<<2) -}; - -struct sd_switch_caps { - unsigned int hs_max_dtr; -}; - -struct sdio_cccr { - unsigned int sdio_vsn; - unsigned int sd_vsn; - unsigned int multi_block:1, - low_speed:1, - wide_bus:1, - high_power:1, - high_speed:1; -}; - -struct sdio_cis { - unsigned short vendor; - unsigned short device; - unsigned short blksize; - unsigned int max_dtr; -}; - -struct mmc_host; -struct sdio_func; -struct sdio_func_tuple; - -#define SDIO_MAX_FUNCS 7 - -/* - * MMC device - */ -struct mmc_card { - unsigned int rca; /* relative card address of device */ - unsigned int type; /* card type */ -#define MMC_TYPE_MMC 0 /* MMC card */ -#define MMC_TYPE_SD 1 /* SD card */ -#define MMC_TYPE_SDIO 2 /* SDIO card */ - unsigned int state; /* (our) card state */ -#define MMC_STATE_PRESENT (1<<0) /* present in sysfs */ -#define MMC_STATE_READONLY (1<<1) /* card is read-only */ -#define MMC_STATE_HIGHSPEED (1<<2) /* card is in high speed mode */ -#define MMC_STATE_BLOCKADDR (1<<3) /* card uses block-addressing */ - - u32 raw_cid[4]; /* raw card CID */ - u32 raw_csd[4]; /* raw card CSD */ - u32 raw_scr[2]; /* raw card SCR */ - struct mmc_cid cid; /* card identification */ - struct mmc_csd csd; /* card specific */ - struct mmc_ext_csd ext_csd; /* mmc v4 extended card specific */ - struct sd_scr scr; /* extra SD information */ - struct sd_switch_caps sw_caps; /* switch (CMD6) caps */ - - unsigned int sdio_funcs; /* number of SDIO functions */ - struct sdio_cccr cccr; /* common card info */ - struct sdio_cis cis; /* common tuple info */ - /* SDIO functions (devices) */ - struct sdio_func *sdio_func[SDIO_MAX_FUNCS]; - unsigned num_info; /* number of info strings */ - const char **info; /* info strings */ - struct sdio_func_tuple *tuples; /* unknown common tuples */ -}; - -#define mmc_card_mmc(c) ((c)->type == MMC_TYPE_MMC) -#define mmc_card_sd(c) ((c)->type == MMC_TYPE_SD) -#define mmc_card_sdio(c) ((c)->type == MMC_TYPE_SDIO) - -#define mmc_card_present(c) ((c)->state & MMC_STATE_PRESENT) -#define mmc_card_readonly(c) ((c)->state & MMC_STATE_READONLY) -#define mmc_card_highspeed(c) ((c)->state & MMC_STATE_HIGHSPEED) -#define mmc_card_blockaddr(c) ((c)->state & MMC_STATE_BLOCKADDR) - -#define mmc_card_set_present(c) ((c)->state |= MMC_STATE_PRESENT) -#define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY) -#define mmc_card_set_highspeed(c) ((c)->state |= MMC_STATE_HIGHSPEED) -#define mmc_card_set_blockaddr(c) ((c)->state |= MMC_STATE_BLOCKADDR) - -#define mmc_card_name(c) ((c)->cid.prod_name) -#define mmc_card_id(c) ((c)->dev.bus_id) - -#define mmc_list_to_card(l) container_of(l, struct mmc_card, node) -#define mmc_get_drvdata(c) dev_get_drvdata(&(c)->dev) -#define mmc_set_drvdata(c, d) dev_set_drvdata(&(c)->dev, d) - -#endif diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h deleted file mode 100644 index 7f0e786..0000000 --- a/include/linux/mmc/core.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * linux/include/linux/mmc/core.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef MMC_CORE_H -#define MMC_CORE_H - -#include <asm/arch/sdhc.h> - -struct request; -struct mmc_data; -struct mmc_request; - -struct mmc_command { - esdhc_cmd_t cmd; - esdhc_resp_t resp; -#define MMC_RSP_PRESENT (1 << 0) -#define MMC_RSP_136 (1 << 1) /* 136 bit response */ -#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ -#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ -#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ - -#define MMC_CMD_MASK (3 << 5) /* non-SPI command type */ -#define MMC_CMD_AC (0 << 5) -#define MMC_CMD_ADTC (1 << 5) -#define MMC_CMD_BC (2 << 5) -#define MMC_CMD_BCR (3 << 5) - -#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */ -#define MMC_RSP_SPI_S2 (1 << 8) /* second byte */ -#define MMC_RSP_SPI_B4 (1 << 9) /* four data bytes */ -#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */ - -/* - * These are the native response types, and correspond to valid bit - * patterns of the above flags. One additional valid pattern - * is all zeros, which means we don't expect a response. - */ -#define MMC_RSP_NONE (0) -#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) -#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) -#define MMC_RSP_R3 (MMC_RSP_PRESENT) -#define MMC_RSP_R4 (MMC_RSP_PRESENT) -#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) - -#define mmc_resp_type(cmd) ((cmd)->flags & \ - (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC| \ - MMC_RSP_BUSY|MMC_RSP_OPCODE)) - -#define MMC_KEEP_CLK_RUN (1 << 31) /* Keep card clock on after request */ - -/* - * These are the SPI response types for MMC, SD, and SDIO cards. - * Commands return R1, with maybe more info. Zero is an error type; - * callers must always provide the appropriate MMC_RSP_SPI_Rx flags. - */ -#define MMC_RSP_SPI_R1 (MMC_RSP_SPI_S1) -#define MMC_RSP_SPI_R1B (MMC_RSP_SPI_S1|MMC_RSP_SPI_BUSY) -#define MMC_RSP_SPI_R2 (MMC_RSP_SPI_S1|MMC_RSP_SPI_S2) -#define MMC_RSP_SPI_R3 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4) -#define MMC_RSP_SPI_R4 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4) -#define MMC_RSP_SPI_R5 (MMC_RSP_SPI_S1|MMC_RSP_SPI_S2) -#define MMC_RSP_SPI_R7 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4) - -#define mmc_spi_resp_type(cmd) ((cmd)->flags & \ - (MMC_RSP_SPI_S1|MMC_RSP_SPI_BUSY|MMC_RSP_SPI_S2|MMC_RSP_SPI_B4)) - -/* - * These are the command types. - */ -#define mmc_cmd_type(cmd) ((cmd)->flags & MMC_CMD_MASK) - - unsigned int retries; /* max number of retries */ - unsigned int error; /* command error */ - -/* - * Standard errno values are used for errors, but some have specific - * meaning in the MMC layer: - * - * ETIMEDOUT Card took too long to respond - * EILSEQ Basic format problem with the received or sent data - * (e.g. CRC check failed, incorrect opcode in response - * or bad end bit) - * EINVAL Request cannot be performed because of restrictions - * in hardware and/or the driver - * ENOMEDIUM Host can determine that the slot is empty and is - * actively failing requests - */ - - struct mmc_data *data; /* data segment associated with cmd */ - struct mmc_request *mrq; /* associated request */ -}; - -struct mmc_data { - unsigned int timeout_ns; /* data timeout (in ns, max 80ms) */ - unsigned int timeout_clks; /* data timeout (in clocks) */ - unsigned int blksz; /* data block size */ - unsigned int blocks; /* number of blocks */ - unsigned int error; /* data error */ - unsigned int flags; - -#define MMC_DATA_WRITE (1 << 8) -#define MMC_DATA_READ (1 << 9) -#define MMC_DATA_STREAM (1 << 10) - - unsigned int bytes_xfered; - - struct mmc_command *stop; /* stop command */ - struct mmc_request *mrq; /* associated request */ - - unsigned int sg_len; /* size of scatter list */ - struct scatterlist *sg; /* I/O scatter list */ -}; - -struct mmc_request { - struct mmc_command *cmd; - struct mmc_data *data; - struct mmc_command *stop; - - void *done_data; /* completion data */ - void (*done)(struct mmc_request *); /* completion function */ -}; - -#endif diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h deleted file mode 100644 index 4b9bde9..0000000 --- a/include/linux/mmc/mmc.h +++ /dev/null @@ -1,291 +0,0 @@ -/* (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * Header for MultiMediaCard (MMC) - * - * Copyright 2002 Hewlett-Packard Company - * - * Use consistent with the GNU GPL is permitted, - * provided that this copyright notice is - * preserved in its entirety in all copies and derived works. - * - * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, - * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS - * FITNESS FOR ANY PARTICULAR PURPOSE. - * - * Many thanks to Alessandro Rubini and Jonathan Corbet! - * - * Based strongly on code by: - * - * Author: Yong-iL Joh <tolkien@mizi.com> - * Date : $Date: 2002/06/18 12:37:30 $ - * - * Author: Andrew Christian - * 15 May 2002 - */ - -#ifndef MMC_MMC_H -#define MMC_MMC_H - -/* Standard MMC commands (4.1) type argument response */ - /* class 1 */ -#define MMC_GO_IDLE_STATE 0 /* bc */ -#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ -#define MMC_ALL_SEND_CID 2 /* bcr R2 */ -#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ -#define MMC_SET_DSR 4 /* bc [31:16] RCA */ -#define MMC_SWITCH 6 /* ac [31:0] See below R1b */ -#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ -#define MMC_SEND_EXT_CSD 8 /* adtc R1 */ -#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */ -#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ -#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ -#define MMC_STOP_TRANSMISSION 12 /* ac R1b */ -#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ -#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ -#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */ -#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */ - - /* class 2 */ -#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ -#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ -#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ - - /* class 3 */ -#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ - - /* class 4 */ -#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ -#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ -#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ -#define MMC_PROGRAM_CID 26 /* adtc R1 */ -#define MMC_PROGRAM_CSD 27 /* adtc R1 */ - - /* class 6 */ -#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ -#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ -#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ - - /* class 5 */ -#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ -#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ -#define MMC_ERASE 38 /* ac R1b */ - - /* class 9 */ -#define MMC_FAST_IO 39 /* ac <Complex> R4 */ -#define MMC_GO_IRQ_STATE 40 /* bcr R5 */ - - /* class 7 */ -#define MMC_LOCK_UNLOCK 42 /* adtc R1b */ - - /* class 8 */ -#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ -#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ - -/* - * MMC_SWITCH argument format: - * - * [31:26] Always 0 - * [25:24] Access Mode - * [23:16] Location of target Byte in EXT_CSD - * [15:08] Value Byte - * [07:03] Always 0 - * [02:00] Command Set - */ - -#define MMC_BUS_WIDTH_1 0 -#define MMC_BUS_WIDTH_4 2 -#define MMC_BUS_WIDTH_8 3 - -/* - MMC status in R1, for native mode (SPI bits are different) - Type - e : error bit - s : status bit - r : detected and set for the actual command response - x : detected and set during command execution. the host must poll - the card by sending status command in order to read these bits. - Clear condition - a : according to the card state - b : always related to the previous command. Reception of - a valid command will clear it (with a delay of one command) - c : clear by read - */ - -#define R1_OUT_OF_RANGE (1 << 31) /* er, c */ -#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ -#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ -#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ -#define R1_ERASE_PARAM (1 << 27) /* ex, c */ -#define R1_WP_VIOLATION (1 << 26) /* erx, c */ -#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ -#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ -#define R1_COM_CRC_ERROR (1 << 23) /* er, b */ -#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ -#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ -#define R1_CC_ERROR (1 << 20) /* erx, c */ -#define R1_ERROR (1 << 19) /* erx, c */ -#define R1_UNDERRUN (1 << 18) /* ex, c */ -#define R1_OVERRUN (1 << 17) /* ex, c */ -#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ -#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ -#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ -#define R1_ERASE_RESET (1 << 13) /* sr, c */ -#define R1_STATUS(x) (x & 0xFFFFE000) -#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ -#define R1_READY_FOR_DATA (1 << 8) /* sx, a */ -#define R1_APP_CMD (1 << 5) /* sr, c */ - -/* - * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS - * R1 is the low order byte; R2 is the next highest byte, when present. - */ -#define R1_SPI_IDLE (1 << 0) -#define R1_SPI_ERASE_RESET (1 << 1) -#define R1_SPI_ILLEGAL_COMMAND (1 << 2) -#define R1_SPI_COM_CRC (1 << 3) -#define R1_SPI_ERASE_SEQ (1 << 4) -#define R1_SPI_ADDRESS (1 << 5) -#define R1_SPI_PARAMETER (1 << 6) -/* R1 bit 7 is always zero */ -#define R2_SPI_CARD_LOCKED (1 << 8) -#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */ -#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP -#define R2_SPI_ERROR (1 << 10) -#define R2_SPI_CC_ERROR (1 << 11) -#define R2_SPI_CARD_ECC_ERROR (1 << 12) -#define R2_SPI_WP_VIOLATION (1 << 13) -#define R2_SPI_ERASE_PARAM (1 << 14) -#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ -#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE - -/* These are unpacked versions of the actual responses */ - -struct _mmc_csd { - u8 csd_structure; - u8 spec_vers; - u8 taac; - u8 nsac; - u8 tran_speed; - u16 ccc; - u8 read_bl_len; - u8 read_bl_partial; - u8 write_blk_misalign; - u8 read_blk_misalign; - u8 dsr_imp; - u16 c_size; - u8 vdd_r_curr_min; - u8 vdd_r_curr_max; - u8 vdd_w_curr_min; - u8 vdd_w_curr_max; - u8 c_size_mult; - union { - struct { /* MMC system specification version 3.1 */ - u8 erase_grp_size; - u8 erase_grp_mult; - } v31; - struct { /* MMC system specification version 2.2 */ - u8 sector_size; - u8 erase_grp_size; - } v22; - } erase; - u8 wp_grp_size; - u8 wp_grp_enable; - u8 default_ecc; - u8 r2w_factor; - u8 write_bl_len; - u8 write_bl_partial; - u8 file_format_grp; - u8 copy; - u8 perm_write_protect; - u8 tmp_write_protect; - u8 file_format; - u8 ecc; -}; - -/* - * OCR bits are mostly in host.h - */ -#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */ - -/* - * Card Command Classes (CCC) - */ -#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */ - /* (CMD0,1,2,3,4,7,9,10,12,13,15) */ - /* (and for SPI, CMD58,59) */ -#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */ - /* (CMD11) */ -#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */ - /* (CMD16,17,18) */ -#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */ - /* (CMD20) */ -#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */ - /* (CMD16,24,25,26,27) */ -#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */ - /* (CMD32,33,34,35,36,37,38,39) */ -#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */ - /* (CMD28,29,30) */ -#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */ - /* (CMD16,CMD42) */ -#define CCC_APP_SPEC (1<<8) /* (8) Application specific */ - /* (CMD55,56,57,ACMD*) */ -#define CCC_IO_MODE (1<<9) /* (9) I/O mode */ - /* (CMD5,39,40,52,53) */ -#define CCC_SWITCH (1<<10) /* (10) High speed switch */ - /* (CMD6,34,35,36,37,50) */ - /* (11) Reserved */ - /* (CMD?) */ - -/* - * CSD field definitions - */ - -#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */ -#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */ -/* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */ -#define CSD_STRUCT_VER_1_2 2 -/* Version is coded in CSD_STRUCTURE in EXT_CSD */ -#define CSD_STRUCT_EXT_CSD 3 - -#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */ -#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */ -#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */ -#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */ -#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */ - -/* - * EXT_CSD fields - */ - -#define EXT_CSD_BUS_WIDTH 183 /* R/W */ -#define EXT_CSD_HS_TIMING 185 /* R/W */ -#define EXT_CSD_CARD_TYPE 196 /* RO */ -#define EXT_CSD_REV 192 /* RO */ -#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ - -/* - * EXT_CSD field definitions - */ - -#define EXT_CSD_CMD_SET_NORMAL (1<<0) -#define EXT_CSD_CMD_SET_SECURE (1<<1) -#define EXT_CSD_CMD_SET_CPSECURE (1<<2) - -#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */ -#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */ - -#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ -#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ -#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ - -/* - * MMC_SWITCH access modes - */ - -#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ -#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */ -#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */ -#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ - -#endif /* MMC_MMC_PROTOCOL_H */ - diff --git a/include/linux/mmc/sd.h b/include/linux/mmc/sd.h deleted file mode 100644 index f236909..0000000 --- a/include/linux/mmc/sd.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * include/linux/mmc/sd.h - * - * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved. - * - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or (at - * your option) any later version. - */ - -#ifndef MMC_SD_H -#define MMC_SD_H - -/* SD commands type argument response */ - /* class 0 */ -/* This is basically the same command as for MMC with some quirks. */ -#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */ -#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */ - - /* class 10 */ -#define SD_SWITCH 6 /* adtc [31:0] See below R1 */ - - /* Application commands */ -#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */ -#define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */ -#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */ -#define SD_APP_SEND_SCR 51 /* adtc R1 */ - -#define SD_OCR_VALUE_HV_LC (0x00ff8000) -#define SD_OCR_VALUE_HV_HC (0x40ff8000) -#define SD_OCR_VALUE_LV_HC (0x40000080) -#define SD_OCR_HC_RES (0x40000000) -#define SD_IF_HV_COND_ARG (0x000001AA) -#define SD_IF_LV_COND_ARG (0x000002AA) - -#define SD_OCR_VALUE_COUNT (3) -#define SD_IF_CMD_ARG_COUNT (2) - -/* - * SD_SWITCH argument format: - * - * [31] Check (0) or switch (1) - * [30:24] Reserved (0) - * [23:20] Function group 6 - * [19:16] Function group 5 - * [15:12] Function group 4 - * [11:8] Function group 3 - * [7:4] Function group 2 - * [3:0] Function group 1 - */ - -/* - * SD_SEND_IF_COND argument format: - * - * [31:12] Reserved (0) - * [11:8] Host Voltage Supply Flags - * [7:0] Check Pattern (0xAA) - */ - -/* - * SCR field definitions - */ - -#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */ -#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */ -#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00 */ - -/* - * SD bus widths - */ -#define SD_BUS_WIDTH_1 0 -#define SD_BUS_WIDTH_4 2 - -/* - * SD_SWITCH mode - */ -#define SD_SWITCH_CHECK 0 -#define SD_SWITCH_SET 1 - -/* - * SD_SWITCH function groups - */ -#define SD_SWITCH_GRP_ACCESS 0 - -/* - * SD_SWITCH access modes - */ -#define SD_SWITCH_ACCESS_DEF 0 -#define SD_SWITCH_ACCESS_HS 1 - -#endif - diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h deleted file mode 100644 index ee7fb26..0000000 --- a/include/linux/mmc/sdhci.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver - * - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or (at - * your option) any later version. - */ - -/* - * PCI registers - */ - -#define PCI_SDHCI_IFPIO 0x00 -#define PCI_SDHCI_IFDMA 0x01 -#define PCI_SDHCI_IFVENDOR 0x02 - -#define PCI_SLOT_INFO 0x40 /* 8 bits */ -#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) -#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 - -/* - * Controller registers - */ - -#define SDHCI_DMA_ADDRESS 0x00 - -#define SDHCI_BLOCK_SIZE 0x04 -#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) - -#define SDHCI_BLOCK_COUNT 0x06 - -#define SDHCI_ARGUMENT 0x08 - -#define SDHCI_TRANSFER_MODE 0x0C -#define SDHCI_TRNS_DMA 0x01 -#define SDHCI_TRNS_BLK_CNT_EN 0x02 -#define SDHCI_TRNS_ACMD12 0x04 -#define SDHCI_TRNS_READ 0x10 -#define SDHCI_TRNS_MULTI 0x20 - -#define SDHCI_COMMAND 0x0E -#define SDHCI_CMD_RESP_MASK 0x03 -#define SDHCI_CMD_CRC 0x08 -#define SDHCI_CMD_INDEX 0x10 -#define SDHCI_CMD_DATA 0x20 - -#define SDHCI_CMD_RESP_NONE 0x00 -#define SDHCI_CMD_RESP_LONG 0x01 -#define SDHCI_CMD_RESP_SHORT 0x02 -#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 - -#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) - -#define SDHCI_RESPONSE 0x10 - -#define SDHCI_BUFFER 0x20 - -#define SDHCI_PRESENT_STATE 0x24 -#define SDHCI_CMD_INHIBIT 0x00000001 -#define SDHCI_DATA_INHIBIT 0x00000002 -#define SDHCI_DOING_WRITE 0x00000100 -#define SDHCI_DOING_READ 0x00000200 -#define SDHCI_SPACE_AVAILABLE 0x00000400 -#define SDHCI_DATA_AVAILABLE 0x00000800 -#define SDHCI_CARD_PRESENT 0x00010000 -#define SDHCI_WRITE_PROTECT 0x00080000 - -#define SDHCI_HOST_CONTROL 0x28 -#define SDHCI_CTRL_LED 0x01 -#define SDHCI_CTRL_4BITBUS 0x00000002 -#define SDHCI_CTRL_8BITBUS 0x00000004 -#define SDHCI_CTRL_HISPD 0x04 - -#define SDHCI_POWER_CONTROL 0x29 -#define SDHCI_POWER_ON 0x01 -#define SDHCI_POWER_180 0x0A -#define SDHCI_POWER_300 0x0C -#define SDHCI_POWER_330 0x0E - -#define SDHCI_BLOCK_GAP_CONTROL 0x2A - -#define SDHCI_WAKE_UP_CONTROL 0x2B - -#define SDHCI_CLOCK_CONTROL 0x2C -#define SDHCI_SYSTEM_CONTROL 0x2C -#define SDHCI_DIVIDER_SHIFT 8 -#define SDHCI_CLOCK_CARD_EN 0x0004 -#define SDHCI_CLOCK_INT_STABLE 0x0002 -#define SDHCI_CLOCK_INT_EN 0x0001 - -#define SDHCI_TIMEOUT_CONTROL 0x2E - -#define SDHCI_SOFTWARE_RESET 0x2F -#define SDHCI_RESET_ALL 0x01 -#define SDHCI_RESET_CMD 0x02 -#define SDHCI_RESET_DATA 0x04 - -#define SDHCI_INT_STATUS 0x30 -#define SDHCI_INT_ENABLE 0x34 -#define SDHCI_SIGNAL_ENABLE 0x38 -#define SDHCI_INT_RESPONSE 0x00000001 -#define SDHCI_INT_DATA_END 0x00000002 -#define SDHCI_INT_DMA_END 0x00000008 -#define SDHCI_INT_SPACE_AVAIL 0x00000010 -#define SDHCI_INT_DATA_AVAIL 0x00000020 -#define SDHCI_INT_CARD_INSERT 0x00000040 -#define SDHCI_INT_CARD_REMOVE 0x00000080 -#define SDHCI_INT_CARD_INT 0x00000100 -#define SDHCI_INT_ERROR 0x00008000 -#define SDHCI_INT_TIMEOUT 0x00010000 -#define SDHCI_INT_CRC 0x00020000 -#define SDHCI_INT_END_BIT 0x00040000 -#define SDHCI_INT_INDEX 0x00080000 -#define SDHCI_INT_DATA_TIMEOUT 0x00100000 -#define SDHCI_INT_DATA_CRC 0x00200000 -#define SDHCI_INT_DATA_END_BIT 0x00400000 -#define SDHCI_INT_BUS_POWER 0x00800000 -#define SDHCI_INT_ACMD12ERR 0x01000000 - -#define SDHCI_INT_NORMAL_MASK 0x00007FFF -#define SDHCI_INT_ERROR_MASK 0xFFFF8000 - -#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ - SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) -#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ - SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ - SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ - SDHCI_INT_DATA_END_BIT) - -#define SDHCI_ACMD12_ERR 0x3C - -/* 3E-3F reserved */ - -#define SDHCI_CAPABILITIES 0x40 -#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F -#define SDHCI_TIMEOUT_CLK_SHIFT 0 -#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 -#define SDHCI_CLOCK_BASE_MASK 0x00003F00 -#define SDHCI_CLOCK_BASE_SHIFT 8 -#define SDHCI_MAX_BLOCK_MASK 0x00030000 -#define SDHCI_MAX_BLOCK_SHIFT 16 -#define SDHCI_CAN_DO_HISPD 0x00200000 -#define SDHCI_CAN_DO_DMA 0x00400000 -#define SDHCI_CAN_VDD_330 0x01000000 -#define SDHCI_CAN_VDD_300 0x02000000 -#define SDHCI_CAN_VDD_180 0x04000000 - -/* 44-47 reserved for more caps */ -#define SDHCI_WML_LEV 0x44 - -#define SDHCI_MAX_CURRENT 0x48 - -/* 4C-4F reserved for more max current */ - -/* 50-FB reserved */ - -#define SDHCI_SLOT_INT_STATUS 0xFC - -#define SDHCI_HOST_VERSION 0xFE -#define SDHCI_VENDOR_VER_MASK 0xFF00 -#define SDHCI_VENDOR_VER_SHIFT 8 -#define SDHCI_SPEC_VER_MASK 0x00FF -#define SDHCI_SPEC_VER_SHIFT 0 - -#if 0 - -struct sdhci_chip; - -struct sdhci_host { - struct sdhci_chip *chip; - struct mmc_host *mmc; /* MMC structure */ - -#ifdef CONFIG_LEDS_CLASS - struct led_classdev led; /* LED control */ -#endif - - spinlock_t lock; /* Mutex */ - - int flags; /* Host attributes */ -#define SDHCI_USE_DMA (1<<0) /* Host is DMA capable */ -#define SDHCI_REQ_USE_DMA (1<<1) /* Use DMA for this req. */ - - unsigned int max_clk; /* Max possible freq (MHz) */ - unsigned int timeout_clk; /* Timeout freq (KHz) */ - - unsigned int clock; /* Current clock (MHz) */ - unsigned short power; /* Current voltage */ - - struct mmc_request *mrq; /* Current request */ - struct mmc_command *cmd; /* Current command */ - struct mmc_data *data; /* Current data request */ - unsigned int data_early:1; /* Data finished before cmd */ - - struct scatterlist *cur_sg; /* We're working on this */ - int num_sg; /* Entries left */ - int offset; /* Offset into current sg */ - int remain; /* Bytes left in current */ - - int irq; /* Device IRQ */ - int bar; /* PCI BAR index */ - unsigned long addr; /* Bus address */ - void __iomem *ioaddr; /* Mapped address */ - - struct tasklet_struct card_tasklet; /* Tasklet structures */ - struct tasklet_struct finish_tasklet; - - struct timer_list timer; /* Timer for timeouts */ -}; - -struct sdhci_chip { - struct pci_dev *pdev; - - unsigned long quirks; - - int num_slots; /* Slots on controller */ - struct sdhci_host *hosts[0]; /* Pointers to hosts */ -}; - -#endif |