diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-blackfin/cplbtab.h | 38 | ||||
| -rw-r--r-- | include/asm-blackfin/cpu/bf533_irq.h | 2 | ||||
| -rw-r--r-- | include/asm-blackfin/cpu/defBF532.h | 4 | ||||
| -rw-r--r-- | include/asm-blackfin/cpu/def_LPBlackfin.h | 6 | ||||
| -rw-r--r-- | include/asm-blackfin/page_offset.h | 2 | ||||
| -rw-r--r-- | include/asm-blackfin/uaccess.h | 2 | ||||
| -rw-r--r-- | include/configs/ezkit533.h | 102 | ||||
| -rw-r--r-- | include/configs/stamp.h | 131 |
8 files changed, 140 insertions, 147 deletions
diff --git a/include/asm-blackfin/cplbtab.h b/include/asm-blackfin/cplbtab.h index dc6aee2..ab7d989 100644 --- a/include/asm-blackfin/cplbtab.h +++ b/include/asm-blackfin/cplbtab.h @@ -3,9 +3,9 @@ * * Blackfin BF533/2.6 support : LG Soft India * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd - * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's + * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's * shouldn't be victimized. cplbmgr.S search logic is corrected - * to findout the appropriate victim. + * to findout the appropriate victim. * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC * : LG Soft India */ @@ -15,12 +15,12 @@ #define __ARCH_BFINNOMMU_CPLBTAB_H /************************************************************************* - * ICPLB TABLE + * ICPLB TABLE *************************************************************************/ .data -/* This table is configurable */ +/* This table is configurable */ .align 4; @@ -33,7 +33,7 @@ /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ -#define ANOMALY_05000158 0x200 +#define ANOMALY_05000158 0x200 #ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) @@ -45,14 +45,14 @@ #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) - #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) + #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) #define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) -#endif +#endif .global icplb_table icplb_table: .byte4 0xFFA00000; -.byte4 (L1_IMEMORY); +.byte4 (L1_IMEMORY); .byte4 0x00000000; .byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ .byte4 0x00400000; @@ -174,20 +174,20 @@ ipdt_table: .byte4 0xffffffff; /* end of section - termination*/ /********************************************************************* - * DCPLB TABLE + * DCPLB TABLE ********************************************************************/ .global dcplb_table dcplb_table: .byte4 0x00000000; .byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ -.byte4 0x00400000; +.byte4 0x00400000; .byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ .byte4 0x07C00000; .byte4 (SDRAM_DKERNEL); /*SDRAM_Page15*/ -.byte4 0x00800000; +.byte4 0x00800000; .byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/ -.byte4 0x00C00000; +.byte4 0x00C00000; .byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/ .byte4 0x01000000; .byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/ @@ -197,7 +197,7 @@ dcplb_table: .byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/ .byte4 0x01C00000; .byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/ -#ifndef CONFIG_EZKIT +#ifndef CONFIG_EZKIT .byte4 0x02000000; .byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/ .byte4 0x02400000; @@ -217,7 +217,7 @@ dcplb_table: /********************************************************************** * PAGE DESCRIPTOR TABLE - * + * **********************************************************************/ /* Till here we are discussing about the static memory management model. @@ -225,15 +225,15 @@ dcplb_table: * descriptors to cover the entire addressable memory than will fit into * the available on-chip 16 CPLB MMRs. When this happens, the below table * will be used which will hold all the potentially required CPLB descriptors - * + * * This is how Page descriptor Table is implemented in uClinux/Blackfin. - */ + */ .global dpdt_table dpdt_table: #ifdef CONFIG_CPLB_INFO .byte4 0x00000000; .byte4 (SDRAM_DKERNEL); /*SDRAM_Page0*/ -.byte4 0x00400000; +.byte4 0x00400000; .byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ #endif .byte4 0x00800000; @@ -271,12 +271,12 @@ dpdt_table: .byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/ .byte4 0x20100000; .byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/ -.byte4 0x20000000; +.byte4 0x20000000; .byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/ .byte4 0x20300000; /*Fix for Network*/ .byte4 (SDRAM_EBIU); /*Async Memory bank 3*/ -#ifdef CONFIG_STAMP +#ifdef CONFIG_STAMP .byte4 0x04000000; .byte4 (SDRAM_DGENERIC); .byte4 0x04400000; diff --git a/include/asm-blackfin/cpu/bf533_irq.h b/include/asm-blackfin/cpu/bf533_irq.h index 902308a..9c5230d 100644 --- a/include/asm-blackfin/cpu/bf533_irq.h +++ b/include/asm-blackfin/cpu/bf533_irq.h @@ -81,7 +81,7 @@ /* The ABSTRACT IRQ definitions */ -/* The first seven of the following are fixed, +/* The first seven of the following are fixed, * the rest you change if you need to */ diff --git a/include/asm-blackfin/cpu/defBF532.h b/include/asm-blackfin/cpu/defBF532.h index c30d5cd..26a5fe6 100644 --- a/include/asm-blackfin/cpu/defBF532.h +++ b/include/asm-blackfin/cpu/defBF532.h @@ -30,7 +30,7 @@ /* include all Core registers and bit definitions */ #include <asm/cpu/def_LPBlackfin.h> -/* Helper macros +/* Helper macros * usage: * P0.H = HI(UART_THR); * P0.L = LO(UART_THR); @@ -789,7 +789,7 @@ #define ERR_TYP_P0 0x0E #define ERR_TYP_P1 0x0F -/* +/* * PROGRAMMABLE FLAG MASKS */ diff --git a/include/asm-blackfin/cpu/def_LPBlackfin.h b/include/asm-blackfin/cpu/def_LPBlackfin.h index 11a6504..9ac78c8 100644 --- a/include/asm-blackfin/cpu/def_LPBlackfin.h +++ b/include/asm-blackfin/cpu/def_LPBlackfin.h @@ -21,7 +21,7 @@ #ifndef _DEF_LPBLACKFIN_H #define _DEF_LPBLACKFIN_H -/* +/* * #if !defined(__ADSPLPBLACKFIN__) * #warning def_LPBlackfin.h should only be included for 532 compatible chips. * #endif @@ -344,9 +344,9 @@ /* ** Masks */ #define ENDM 0x00000001 /* (doesn't really exist) Enable Data Memory L1 */ #define ENDCPLB 0x00000002 /* Enable DCPLB */ -#define ASRAM_BSRAM 0x00000000 +#define ASRAM_BSRAM 0x00000000 #define ACACHE_BSRAM 0x00000008 -#define ACACHE_BCACHE 0x0000000C +#define ACACHE_BCACHE 0x0000000C #define DCBS 0x00000010 /* L1 Data Cache Bank Select */ #define PORT_PREF0 0x00001000 /* DAG0 Port Preference */ #define PORT_PREF1 0x00002000 /* DAG1 Port Preference */ diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h index 45e34b5..262473f 100644 --- a/include/asm-blackfin/page_offset.h +++ b/include/asm-blackfin/page_offset.h @@ -22,7 +22,7 @@ * MA 02111-1307 USA */ -/* +/* * Changes made by Akbar Hussain April 10, 2001 */ diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h index 84b4b4e..8578166 100644 --- a/include/asm-blackfin/uaccess.h +++ b/include/asm-blackfin/uaccess.h @@ -3,7 +3,7 @@ * * Copyright (c) 2005 blackfin.uclinux.org * - * This file is based on + * This file is based on * Based on: include/asm-m68knommu/uaccess.h * Changes made by Lineo Inc. May 2001 * diff --git a/include/configs/ezkit533.h b/include/configs/ezkit533.h index a52af4e..5eda673 100644 --- a/include/configs/ezkit533.h +++ b/include/configs/ezkit533.h @@ -9,111 +9,111 @@ #define CONFIG_DRIVER_SMC91111 1 #define CONFIG_SMC91111_BASE 0x20310300 #if 0 -#define CONFIG_MII +#define CONFIG_MII #define CFG_DISCOVER_PHY #endif #define CONFIG_RTC_BF533 1 #define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 27000000 -/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ -/* 1=CLKIN/2 */ -#define CONFIG_CLKIN_HALF 0 -/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ -/* 1=bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ -/* Values can range from 1-64 */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 27000000 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ #define CONFIG_VCO_MULT 22 -/* CONFIG_CCLK_DIV controls what the core clock divider is */ -/* Values can be 1, 2, 4, or 8 ONLY */ +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ #define CONFIG_CCLK_DIV 1 /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ -/* Values can range from 1-15 */ +/* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 5 #if ( CONFIG_CLKIN_HALF == 0 ) -#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) #else -#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) #endif #if (CONFIG_PLL_BYPASS == 0) -#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) -#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) #else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ #endif -#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ -#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ -#define CONFIG_MEM_MT48LC16M16A2TG_75 1 +#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC16M16A2TG_75 1 #define CONFIG_LOADS_ECHO 1 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_PING | \ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_JFFS2 | \ CFG_CMD_DATE) -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off" /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> -#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ +#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ #define CFG_MEMTEST_END 0x01F00000 /* 1 ... 31 MB in DRAM */ -#define CFG_LOAD_ADDR 0x01000000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ +#define CFG_LOAD_ADDR 0x01000000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 #define CFG_MAX_RAM_SIZE 0x02000000 #define CFG_FLASH_BASE 0x20000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) #define CFG_GBL_DATA_SIZE 0x4000 #define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) #define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CFG_FLASH0_BASE 0x20000000 #define CFG_FLASH1_BASE 0x20200000 #define CFG_FLASH2_BASE 0x20280000 #define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */ -#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR 0x20020000 -#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ /* JFFS Partition offset set */ #define CFG_JFFS2_FIRST_BANK 0 #define CFG_JFFS2_NUM_BANKS 1 /* 512k reserved for u-boot */ -#define CFG_JFFS2_FIRST_SECTOR 11 +#define CFG_JFFS2_FIRST_SECTOR 11 /* * Stack sizes */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ #define POLL_MODE 1 #define FLASH_TOT_SECT 40 @@ -123,7 +123,7 @@ /* * Initialize PSD4256 registers for using I2C */ -#define CONFIG_MISC_INIT_R +#define CONFIG_MISC_INIT_R /* * I2C settings @@ -144,7 +144,7 @@ *pFIO_FLAG_S = PF_SDA; \ asm("ssync;"); \ } \ - else { \ + else { \ *pFIO_FLAG_C = PF_SDA; \ asm("ssync;"); \ } @@ -152,7 +152,7 @@ *pFIO_FLAG_S = PF_SCL; \ asm("ssync;"); \ } \ - else { \ + else { \ *pFIO_FLAG_C = PF_SCL; \ asm("ssync;"); \ } @@ -166,15 +166,15 @@ #define __ADSPBF533__ 1 /* 0xFF, 0x7BB07BB0, 0x22547BB0 */ -/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) -#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ - ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) -#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ - B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) +/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ + ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) +#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ + B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) */ -#define AMGCTLVAL 0xFF -#define AMBCTL0VAL 0x7BB07BB0 -#define AMBCTL1VAL 0xFFC27BB0 +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0x7BB07BB0 +#define AMBCTL1VAL 0xFFC27BB0 #define CONFIG_VDSP 1 diff --git a/include/configs/stamp.h b/include/configs/stamp.h index 1402a41..248ca70 100644 --- a/include/configs/stamp.h +++ b/include/configs/stamp.h @@ -17,7 +17,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -40,7 +40,7 @@ #define CONFIG_RTC_BF533 1 /* FLASH/ETHERNET uses the same address range */ -#define SHARED_RESOURCES 1 +#define SHARED_RESOURCES 1 #define CONFIG_VDSP 1 @@ -49,37 +49,37 @@ * */ -/* CONFIG_CLKIN_HZ is any value in Hz */ +/* CONFIG_CLKIN_HZ is any value in Hz */ #define CONFIG_CLKIN_HZ 11059200 -/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ -/* 1=CLKIN/2 */ +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ #define CONFIG_CLKIN_HALF 0 -/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ -/* 1=bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ -/* Values can range from 1-64 */ +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ #define CONFIG_VCO_MULT 45 -/* CONFIG_CCLK_DIV controls what the core clock divider is */ -/* Values can be 1, 2, 4, or 8 ONLY */ +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ #define CONFIG_CCLK_DIV 1 /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ -/* Values can range from 1-15 */ +/* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 6 /* * Network Settings */ /* network support */ -#define CONFIG_IPADDR 192.168.0.15 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_HOSTNAME STAMP +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME STAMP #define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs /* To remove hardcoding and enable MAC storage in EEPROM */ -/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ /* * Command settings @@ -90,17 +90,17 @@ #define CONFIG_BOOTDELAY 5 #define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ -#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_BOOTCOMMAND "run ramboot" #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_PING | \ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_CACHE | \ - CFG_CMD_JFFS2 | \ + CFG_CMD_JFFS2 | \ CFG_CMD_DATE) -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" #define CONFIG_EXTRA_ENV_SETTINGS \ "ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \ @@ -127,14 +127,14 @@ #define CONFIG_BAUDRATE 57600 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_PROMPT "stamp>" /* Monitor Command Prompt */ +#define CFG_PROMPT "stamp>" /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_LOADS_ECHO 1 @@ -154,9 +154,9 @@ * */ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_CFI_AMD_RESET +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET #define CFG_ENV_IS_IN_FLASH 1 @@ -165,8 +165,8 @@ #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ #define CFG_ENV_ADDR 0x20020000 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ #define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ #define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */ @@ -176,10 +176,10 @@ #define CFG_JFFS2_FIRST_BANK 0 #define CFG_JFFS2_NUM_BANKS 1 /* 512k reserved for u-boot */ -#define CFG_JFFS2_FIRST_SECTOR 11 +#define CFG_JFFS2_FIRST_SECTOR 11 -/* - * following timeouts shall be used once the +/* + * following timeouts shall be used once the * Flash real protection is enabled */ #define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ @@ -204,7 +204,7 @@ *pFIO_FLAG_S = PF_SDA; \ asm("ssync;"); \ } \ - else { \ + else { \ *pFIO_FLAG_C = PF_SDA; \ asm("ssync;"); \ } @@ -212,7 +212,7 @@ *pFIO_FLAG_S = PF_SCL; \ asm("ssync;"); \ } \ - else { \ + else { \ *pFIO_FLAG_C = PF_SCL; \ asm("ssync;"); \ } @@ -236,9 +236,9 @@ /* * IDE/ATA stuff */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ #define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ @@ -246,9 +246,9 @@ #define CFG_ATA_BASE_ADDR 0x20200000 #define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ #define CFG_ATA_STRIDE 2 #endif @@ -258,23 +258,20 @@ * */ -#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ -#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ #define CONFIG_MEM_MT48LC64M4A2FB_7E 1 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ #define CFG_MEMTEST_END 0x07EFFFFF /* 1 ... 127 MB in DRAM */ -#define CFG_LOAD_ADDR 0x01000000 /* default load address */ +#define CFG_LOAD_ADDR 0x01000000 /* default load address */ -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 #define CFG_MAX_RAM_SIZE 0x08000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) - - - #if ( CONFIG_CLKIN_HALF == 0 ) #define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) #else @@ -289,14 +286,12 @@ #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ #endif - - /* * Miscellaneous configurable options */ -#define CFG_HZ 1000 /* 1ms time tick */ +#define CFG_HZ 1000 /* 1ms time tick */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) #define CFG_GBL_DATA_SIZE 0x4000 #define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) @@ -309,25 +304,24 @@ /* * Stack sizes */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ /* * FLASH organization and environment definitions */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* 0xFF, 0xBBC3BBc3, 0x99B39983 */ -/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) -#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ - B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) -#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ - B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) +/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ + B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) +#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ + B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) */ -#define AMGCTLVAL 0xFF -#define AMBCTL0VAL 0xBBC3BBC3 -#define AMBCTL1VAL 0x99B39983 -#define CF_AMBCTL1VAL 0x99B3ffc2 +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0xBBC3BBC3 +#define AMBCTL1VAL 0x99B39983 +#define CF_AMBCTL1VAL 0x99B3ffc2 #ifdef CONFIG_VDSP #define ET_EXEC_VDSP 0x8 @@ -336,5 +330,4 @@ #define VDSP_ENTRY_ADDR 0xFFA00000 #endif - #endif |