diff options
Diffstat (limited to 'include/usb')
| -rw-r--r-- | include/usb/mpc8xx_udc.h | 210 | ||||
| -rw-r--r-- | include/usb/omap1510_udc.h | 193 |
2 files changed, 403 insertions, 0 deletions
diff --git a/include/usb/mpc8xx_udc.h b/include/usb/mpc8xx_udc.h new file mode 100644 index 0000000..039d245 --- /dev/null +++ b/include/usb/mpc8xx_udc.h @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2006 Bryan O'Donoghue, CodeHermit + * bodonoghue@codehermit.ie + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the + * Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +#include <commproc.h> + +/* Mode Register */ +#define USMOD_EN 0x01 +#define USMOD_HOST 0x02 +#define USMOD_TEST 0x04 +#define USMOD_SFTE 0x08 +#define USMOD_RESUME 0x40 +#define USMOD_LSS 0x80 + +/* Endpoint Registers */ +#define USEP_RHS_NORM 0x00 +#define USEP_RHS_IGNORE 0x01 +#define USEP_RHS_NAK 0x02 +#define USEP_RHS_STALL 0x03 + +#define USEP_THS_NORM 0x00 +#define USEP_THS_IGNORE 0x04 +#define USEP_THS_NAK 0x08 +#define USEP_THS_STALL 0x0C + +#define USEP_RTE 0x10 +#define USEP_MF 0x20 + +#define USEP_TM_CONTROL 0x00 +#define USEP_TM_INT 0x100 +#define USEP_TM_BULK 0x200 +#define USEP_TM_ISO 0x300 + +/* Command Register */ +#define USCOM_EP0 0x00 +#define USCOM_EP1 0x01 +#define USCOM_EP2 0x02 +#define USCOM_EP3 0x03 + +#define USCOM_FLUSH 0x40 +#define USCOM_STR 0x80 + +/* Event Register */ +#define USB_E_RXB 0x0001 +#define USB_E_TXB 0x0002 +#define USB_E_BSY 0x0004 +#define USB_E_SOF 0x0008 +#define USB_E_TXE1 0x0010 +#define USB_E_TXE2 0x0020 +#define USB_E_TXE3 0x0040 +#define USB_E_TXE4 0x0080 +#define USB_TX_ERRMASK (USB_E_TXE1|USB_E_TXE2|USB_E_TXE3|USB_E_TXE4) +#define USB_E_IDLE 0x0100 +#define USB_E_RESET 0x0200 + +/* Mask Register */ +#define USBS_IDLE 0x01 + +/* RX Buffer Descriptor */ +#define RX_BD_OV 0x02 +#define RX_BD_CR 0x04 +#define RX_BD_AB 0x08 +#define RX_BD_NO 0x10 +#define RX_BD_PID_DATA0 0x00 +#define RX_BD_PID_DATA1 0x40 +#define RX_BD_PID_SETUP 0x80 +#define RX_BD_F 0x400 +#define RX_BD_L 0x800 +#define RX_BD_I 0x1000 +#define RX_BD_W 0x2000 +#define RX_BD_E 0x8000 + +/* Useful masks */ +#define RX_BD_PID_BITMASK (RX_BD_PID_DATA1 | RX_BD_PID_SETUP) +#define STALL_BITMASK (USEP_THS_STALL | USEP_RHS_STALL) +#define NAK_BITMASK (USEP_THS_NAK | USEP_RHS_NAK) +#define CBD_TX_BITMASK (TX_BD_R | TX_BD_L | TX_BD_TC | TX_BD_I | TX_BD_CNF) + +/* TX Buffer Descriptor */ +#define TX_BD_UN 0x02 +#define TX_BD_TO 0x04 +#define TX_BD_NO_PID 0x00 +#define TX_BD_PID_DATA0 0x80 +#define TX_BD_PID_DATA1 0xC0 +#define TX_BD_CNF 0x200 +#define TX_BD_TC 0x400 +#define TX_BD_L 0x800 +#define TX_BD_I 0x1000 +#define TX_BD_W 0x2000 +#define TX_BD_R 0x8000 + +/* Implementation specific defines */ + +#define EP_MIN_PACKET_SIZE 0x08 +#define MAX_ENDPOINTS 0x04 +#define FIFO_SIZE 0x10 +#define EP_MAX_PKT FIFO_SIZE +#define TX_RING_SIZE 0x04 +#define RX_RING_SIZE 0x06 +#define USB_MAX_PKT 0x40 +#define TOGGLE_TX_PID(x) x= ((~x)&0x40)|0x80 +#define TOGGLE_RX_PID(x) x^= 0x40 +#define EP_ATTACHED 0x01 /* Endpoint has a urb attached or not */ +#define EP_SEND_ZLP 0x02 /* Send ZLP y/n ? */ + +#define PROFF_USB 0x00000000 +#define CPM_USB_BASE 0x00000A00 + +/* UDC device defines */ +#define EP0_MAX_PACKET_SIZE EP_MAX_PKT +#define UDC_OUT_ENDPOINT 0x02 +#define UDC_OUT_PACKET_SIZE EP_MIN_PACKET_SIZE +#define UDC_IN_ENDPOINT 0x03 +#define UDC_IN_PACKET_SIZE EP_MIN_PACKET_SIZE +#define UDC_INT_ENDPOINT 0x01 +#define UDC_INT_PACKET_SIZE UDC_IN_PACKET_SIZE +#define UDC_BULK_PACKET_SIZE EP_MIN_PACKET_SIZE + +struct mpc8xx_ep { + struct urb * urb; + unsigned char pid; + unsigned char sc; + volatile cbd_t * prx; +}; + +typedef struct mpc8xx_usb{ + char usmod; /* Mode Register */ + char usaddr; /* Slave Address Register */ + char uscom; /* Command Register */ + char res1; /* Reserved */ + ushort usep[4]; + ulong res2; /* Reserved */ + ushort usber; /* Event Register */ + ushort res3; /* Reserved */ + ushort usbmr; /* Mask Register */ + char res4; /* Reserved */ + char usbs; /* Status Register */ + char res5[8]; /* Reserved */ +}usb_t; + +typedef struct mpc8xx_parameter_ram{ + ushort ep0ptr; /* Endpoint Pointer Register 0 */ + ushort ep1ptr; /* Endpoint Pointer Register 1 */ + ushort ep2ptr; /* Endpoint Pointer Register 2 */ + ushort ep3ptr; /* Endpoint Pointer Register 3 */ + uint rstate; /* Receive state */ + uint rptr; /* Receive internal data pointer */ + ushort frame_n; /* Frame number */ + ushort rbcnt; /* Receive byte count */ + uint rtemp; /* Receive temp cp use only */ + uint rxusb; /* Rx Data Temp */ + ushort rxuptr; /* Rx microcode return address temp */ +}usb_pram_t; + +typedef struct endpoint_parameter_block_pointer{ + ushort rbase; /* RxBD base address */ + ushort tbase; /* TxBD base address */ + char rfcr; /* Rx Function code */ + char tfcr; /* Tx Function code */ + ushort mrblr; /* Maximum Receive Buffer Length */ + ushort rbptr; /* RxBD pointer Next Buffer Descriptor */ + ushort tbptr; /* TxBD pointer Next Buffer Descriptor */ + ulong tstate; /* Transmit internal state */ + ulong tptr; /* Transmit internal data pointer */ + ushort tcrc; /* Transmit temp CRC */ + ushort tbcnt; /* Transmit internal bye count */ + ulong ttemp; /* Tx temp */ + ushort txuptr; /* Tx microcode return address */ + ushort res1; /* Reserved */ +}usb_epb_t; + +typedef enum mpc8xx_udc_state{ + STATE_NOT_READY, + STATE_ERROR, + STATE_READY, +}mpc8xx_udc_state_t; + +/* Declarations */ +int udc_init(void); +void udc_irq(void); +int udc_endpoint_write(struct usb_endpoint_instance *endpoint); +void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, + struct usb_endpoint_instance *endpoint); +void udc_connect(void); +void udc_disconnect(void); +void udc_enable(struct usb_device_instance *device); +void udc_disable(void); +void udc_startup_events(struct usb_device_instance *device); + +/* Flow control */ +void udc_set_nak(int epid); +void udc_unset_nak (int epid); diff --git a/include/usb/omap1510_udc.h b/include/usb/omap1510_udc.h new file mode 100644 index 0000000..ece0e95 --- /dev/null +++ b/include/usb/omap1510_udc.h @@ -0,0 +1,193 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * Based on + * linux/drivers/usb/device/bi/omap.h + * Register definitions for TI OMAP1510 USB bus interface driver + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * 2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef __USBDCORE_OMAP1510_H__ +#define __USBDCORE_OMAP1510_H__ + + +/* + * 13.2 MPU Register Map + */ + +/* Table 13-1. USB Function Module Registers (endpoint) */ +#define UDC_BASE 0xFFFB4000 +#define UDC_OFFSET(offset) (UDC_BASE + (offset)) +#define UDC_REV UDC_OFFSET(0x0) /* Revision */ +#define UDC_EP_NUM UDC_OFFSET(0x4) /* Endpoint selection */ +#define UDC_DATA UDC_OFFSET(0x08) /* Data */ +#define UDC_CTRL UDC_OFFSET(0x0C) /* Control */ +#define UDC_STAT_FLG UDC_OFFSET(0x10) /* Status flag */ +#define UDC_RXFSTAT UDC_OFFSET(0x14) /* Receive FIFO status */ +#define UDC_SYSCON1 UDC_OFFSET(0x18) /* System configuration 1 */ +#define UDC_SYSCON2 UDC_OFFSET(0x1C) /* System configuration 2 */ +#define UDC_DEVSTAT UDC_OFFSET(0x20) /* Device status */ +#define UDC_SOF UDC_OFFSET(0x24) /* Start of frame */ +#define UDC_IRQ_EN UDC_OFFSET(0x28) /* Interrupt enable */ +#define UDC_DMA_IRQ_EN UDC_OFFSET(0x2C) /* DMA interrupt enable */ +#define UDC_IRQ_SRC UDC_OFFSET(0x30) /* Interrupt source */ +#define UDC_EPN_STAT UDC_OFFSET(0x34) /* Endpoint interrupt status */ +#define UDC_DMAN_STAT UDC_OFFSET(0x3C) /* DMA endpoint interrupt status */ + +/* IRQ_EN register fields */ +#define UDC_Sof_IE (1 << 7) /* Start-of-frame interrupt enabled */ +#define UDC_EPn_RX_IE (1 << 5) /* Receive endpoint interrupt enabled */ +#define UDC_EPn_TX_IE (1 << 4) /* Transmit endpoint interrupt enabled */ +#define UDC_DS_Chg_IE (1 << 3) /* Device state changed interrupt enabled */ +#define UDC_EP0_IE (1 << 0) /* EP0 transaction interrupt enabled */ + +/* IRQ_SRC register fields */ +#define UDC_TXn_Done (1 << 10) /* Transmit DMA channel n done */ +#define UDC_RXn_Cnt (1 << 9) /* Receive DMA channel n transactions count */ +#define UDC_RXn_EOT (1 << 8) /* Receive DMA channel n end of transfer */ +#define UDC_SOF_Flg (1 << 7) /* Start-of-frame interrupt flag */ +#define UDC_EPn_RX (1 << 5) /* Endpoint n OUT transaction */ +#define UDC_EPn_TX (1 << 4) /* Endpoint n IN transaction */ +#define UDC_DS_Chg (1 << 3) /* Device state changed */ +#define UDC_Setup (1 << 2) /* Setup transaction */ +#define UDC_EP0_RX (1 << 1) /* EP0 OUT transaction */ +#define UDC_EP0_TX (1 << 0) /* EP0 IN transaction */ + +/* DEVSTAT register fields, 14.2.9 */ +#define UDC_R_WK_OK (1 << 6) /* Remote wakeup granted */ +#define UDC_USB_Reset (1 << 5) /* USB reset signalling is active */ +#define UDC_SUS (1 << 4) /* Suspended state */ +#define UDC_CFG (1 << 3) /* Configured state */ +#define UDC_ADD (1 << 2) /* Addressed state */ +#define UDC_DEF (1 << 1) /* Default state */ +#define UDC_ATT (1 << 0) /* Attached state */ + +/* SYSCON1 register fields */ +#define UDC_Cfg_Lock (1 << 8) /* Device configuration locked */ +#define UDC_Nak_En (1 << 4) /* NAK enable */ +#define UDC_Self_Pwr (1 << 2) /* Device is self-powered */ +#define UDC_Soff_Dis (1 << 1) /* Shutoff disabled */ +#define UDC_Pullup_En (1 << 0) /* External pullup enabled */ + +/* SYSCON2 register fields */ +#define UDC_Rmt_Wkp (1 << 6) /* Remote wakeup */ +#define UDC_Stall_Cmd (1 << 5) /* Stall endpoint */ +#define UDC_Dev_Cfg (1 << 3) /* Device configured */ +#define UDC_Clr_Cfg (1 << 2) /* Clear configured */ + +/* + * Select and enable endpoints + */ + +/* Table 13-1. USB Function Module Registers (endpoint configuration) */ +#define UDC_EPBASE UDC_OFFSET(0x80) /* Endpoints base address */ +#define UDC_EP0 UDC_EPBASE /* Control endpoint configuration */ +#define UDC_EP_RX_BASE UDC_OFFSET(0x84) /* Receive endpoints base address */ +#define UDC_EP_RX(endpoint) (UDC_EP_RX_BASE + ((endpoint) - 1) * 4) +#define UDC_EP_TX_BASE UDC_OFFSET(0xC4) /* Transmit endpoints base address */ +#define UDC_EP_TX(endpoint) (UDC_EP_TX_BASE + ((endpoint) - 1) * 4) + +/* EP_NUM register fields */ +#define UDC_Setup_Sel (1 << 6) /* Setup FIFO select */ +#define UDC_EP_Sel (1 << 5) /* TX/RX FIFO select */ +#define UDC_EP_Dir (1 << 4) /* Endpoint direction */ + +/* CTRL register fields */ +#define UDC_Clr_Halt (1 << 7) /* Clear halt endpoint */ +#define UDC_Set_Halt (1 << 6) /* Set halt endpoint */ +#define UDC_Set_FIFO_En (1 << 2) /* Set FIFO enable */ +#define UDC_Clr_EP (1 << 1) /* Clear endpoint */ +#define UDC_Reset_EP (1 << 0) /* Reset endpoint */ + +/* STAT_FLG register fields */ +#define UDC_Miss_In (1 << 14) +#define UDC_Data_Flush (1 << 13) +#define UDC_ISO_Err (1 << 12) +#define UDC_ISO_FIFO_Empty (1 << 9) +#define UDC_ISO_FIFO_Full (1 << 8) +#define UDC_EP_Halted (1 << 6) +#define UDC_STALL (1 << 5) +#define UDC_NAK (1 << 4) +#define UDC_ACK (1 << 3) +#define UDC_FIFO_En (1 << 2) +#define UDC_Non_ISO_FIFO_Empty (1 << 1) +#define UDC_Non_ISO_FIFO_Full (1 << 0) + +/* EPn_RX register fields */ +#define UDC_EPn_RX_Valid (1 << 15) /* valid */ +#define UDC_EPn_RX_Db (1 << 14) /* double-buffer */ +#define UDC_EPn_RX_Iso (1 << 11) /* isochronous */ + +/* EPn_TX register fields */ +#define UDC_EPn_TX_Valid (1 << 15) /* valid */ +#define UDC_EPn_TX_Db (1 << 14) /* double-buffer */ +#define UDC_EPn_TX_Iso (1 << 11) /* isochronous */ + +#define EP0_PACKETSIZE 0x40 + +/* physical to logical endpoint mapping + * Physical endpoints are an index into device->bus->endpoint_array. + * Logical endpoints are endpoints 0 to 15 IN and OUT as defined in + * the USB specification. + * + * physical ep logical ep direction endpoint_address + * 0 0 IN and OUT 0x00 + * 1 to 15 1 to 15 OUT 0x01 to 0x0f + * 16 to 30 1 to 15 IN 0x81 to 0x8f + */ +#define PHYS_EP_TO_EP_ADDR(ep) (((ep) < 16) ? (ep) : (((ep) - 15) | 0x80)) +#define EP_ADDR_TO_PHYS_EP(a) (((a) & 0x80) ? (((a) & ~0x80) + 15) : (a)) + +/* MOD_CONF_CTRL_0 bits (FIXME: move to board hardware.h ?) */ +#define CONF_MOD_USB_W2FC_VBUS_MODE_R (1 << 17) + +/* Other registers (may be) related to USB */ + +#define CLOCK_CTRL (0xFFFE0830) +#define APLL_CTRL (0xFFFE084C) +#define DPLL_CTRL (0xFFFE083C) +#define SOFT_REQ (0xFFFE0834) +#define STATUS_REQ (0xFFFE0840) + +/* FUNC_MUX_CTRL_0 bits related to USB */ +#define UDC_VBUS_CTRL (1 << 19) +#define UDC_VBUS_MODE (1 << 18) + +/* OMAP Endpoint parameters */ +#define EP0_MAX_PACKET_SIZE 64 +#define UDC_OUT_ENDPOINT 2 +#define UDC_OUT_PACKET_SIZE 64 +#define UDC_IN_ENDPOINT 1 +#define UDC_IN_PACKET_SIZE 64 +#define UDC_INT_ENDPOINT 5 +#define UDC_INT_PACKET_SIZE 16 +#define UDC_BULK_PACKET_SIZE 16 + +void udc_irq (void); +/* Flow control */ +void udc_set_nak(int epid); +void udc_unset_nak (int epid); + +/* Higher level functions for abstracting away from specific device */ +int udc_endpoint_write(struct usb_endpoint_instance *endpoint); + +int udc_init (void); + +void udc_enable(struct usb_device_instance *device); +void udc_disable(void); + +void udc_connect(void); +void udc_disconnect(void); + +void udc_startup_events(struct usb_device_instance *device); +void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, struct usb_endpoint_instance *endpoint); + +#endif |