summaryrefslogtreecommitdiff
path: root/include/mpc83xx.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/mpc83xx.h')
-rw-r--r--include/mpc83xx.h56
1 files changed, 32 insertions, 24 deletions
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index dba1aea..7299ca0 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -145,10 +145,10 @@
/* SPCR bits - MPC831x and MPC837x specific */
#define SPCR_TSECDP 0x00003000 /* TSEC data priority */
#define SPCR_TSECDP_SHIFT (31-19)
-#define SPCR_TSECEP 0x00000C00 /* TSEC emergency priority */
-#define SPCR_TSECEP_SHIFT (31-21)
-#define SPCR_TSECBDP 0x00000300 /* TSEC buffer descriptor priority */
-#define SPCR_TSECBDP_SHIFT (31-23)
+#define SPCR_TSECBDP 0x00000C00 /* TSEC buffer descriptor priority */
+#define SPCR_TSECBDP_SHIFT (31-21)
+#define SPCR_TSECEP 0x00000300 /* TSEC emergency priority */
+#define SPCR_TSECEP_SHIFT (31-23)
#endif
/* SICRL/H - System I/O Configuration Register Low/High
@@ -486,7 +486,15 @@
#define HRCWL_CE_TO_PLL_1X30 0x0000001E
#define HRCWL_CE_TO_PLL_1X31 0x0000001F
-#elif defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
+#elif defined(CONFIG_MPC8315)
+#define HRCWL_SVCOD 0x30000000
+#define HRCWL_SVCOD_SHIFT 28
+#define HRCWL_SVCOD_DIV_2 0x00000000
+#define HRCWL_SVCOD_DIV_4 0x10000000
+#define HRCWL_SVCOD_DIV_8 0x20000000
+#define HRCWL_SVCOD_DIV_1 0x30000000
+
+#elif defined(CONFIG_MPC837X)
#define HRCWL_SVCOD 0x30000000
#define HRCWL_SVCOD_SHIFT 28
#define HRCWL_SVCOD_DIV_4 0x00000000
@@ -752,31 +760,31 @@
#define SCCR_TSEC2CM_2 0x20000000
#define SCCR_TSEC2CM_3 0x30000000
-#define SCCR_USBDRCM 0x00300000
-#define SCCR_USBDRCM_SHIFT 20
+#define SCCR_USBDRCM 0x00c00000
+#define SCCR_USBDRCM_SHIFT 22
#define SCCR_USBDRCM_0 0x00000000
-#define SCCR_USBDRCM_1 0x00100000
-#define SCCR_USBDRCM_2 0x00200000
-#define SCCR_USBDRCM_3 0x00300000
+#define SCCR_USBDRCM_1 0x00400000
+#define SCCR_USBDRCM_2 0x00800000
+#define SCCR_USBDRCM_3 0x00c00000
-#define SCCR_PCIEXP1CM 0x00080000
-#define SCCR_PCIEXP2CM 0x00040000
+#define SCCR_PCIEXP1CM 0x00300000
+#define SCCR_PCIEXP2CM 0x000c0000
-#define SCCR_SATA1CM 0x0000c000
-#define SCCR_SATA1CM_SHIFT 14
-#define SCCR_SATACM 0x0000f000
-#define SCCR_SATACM_SHIFT 8
+#define SCCR_SATA1CM 0x00003000
+#define SCCR_SATA1CM_SHIFT 12
+#define SCCR_SATACM 0x00003c00
+#define SCCR_SATACM_SHIFT 10
#define SCCR_SATACM_0 0x00000000
-#define SCCR_SATACM_1 0x00005000
-#define SCCR_SATACM_2 0x0000a000
-#define SCCR_SATACM_3 0x0000f000
+#define SCCR_SATACM_1 0x00001400
+#define SCCR_SATACM_2 0x00002800
+#define SCCR_SATACM_3 0x00003c00
-#define SCCR_TDMCM 0x000000c0
-#define SCCR_TDMCM_SHIFT 6
+#define SCCR_TDMCM 0x00000030
+#define SCCR_TDMCM_SHIFT 4
#define SCCR_TDMCM_0 0x00000000
-#define SCCR_TDMCM_1 0x00000040
-#define SCCR_TDMCM_2 0x00000080
-#define SCCR_TDMCM_3 0x000000c0
+#define SCCR_TDMCM_1 0x00000010
+#define SCCR_TDMCM_2 0x00000020
+#define SCCR_TDMCM_3 0x00000030
#elif defined(CONFIG_MPC837X)
/* SCCR bits - MPC837x specific */