diff options
Diffstat (limited to 'include/dt-bindings/clock')
-rw-r--r-- | include/dt-bindings/clock/imx6qdl-clock.h | 121 |
1 files changed, 61 insertions, 60 deletions
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index 2905033..6915b25 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -62,8 +62,8 @@ #define IMX6QDL_CLK_USDHC3_SEL 50 #define IMX6QDL_CLK_USDHC4_SEL 51 #define IMX6QDL_CLK_ENFC_SEL 52 -#define IMX6QDL_CLK_EIM_SEL 53 -#define IMX6QDL_CLK_EIM_SLOW_SEL 54 +#define IMX6QDL_CLK_EMI_SEL 53 +#define IMX6QDL_CLK_EMI_SLOW_SEL 54 #define IMX6QDL_CLK_VDO_AXI_SEL 55 #define IMX6QDL_CLK_VPU_AXI_SEL 56 #define IMX6QDL_CLK_CKO1_SEL 57 @@ -86,8 +86,6 @@ #define IMX6QDL_CLK_GPU3D_SHADER 74 #define IMX6QDL_CLK_IPU1_PODF 75 #define IMX6QDL_CLK_IPU2_PODF 76 -#define IMX6QDL_CLK_LDB_DI0_PODF 77 -#define IMX6QDL_CLK_LDB_DI1_PODF 78 #define IMX6QDL_CLK_IPU1_DI0_PRE 79 #define IMX6QDL_CLK_IPU1_DI1_PRE 80 #define IMX6QDL_CLK_IPU2_DI0_PRE 81 @@ -106,13 +104,11 @@ #define IMX6QDL_CLK_USDHC4_PODF 94 #define IMX6QDL_CLK_ENFC_PRED 95 #define IMX6QDL_CLK_ENFC_PODF 96 -#define IMX6QDL_CLK_EIM_PODF 97 -#define IMX6QDL_CLK_EIM_SLOW_PODF 98 +#define IMX6QDL_CLK_EMI_PODF 97 +#define IMX6QDL_CLK_EMI_SLOW_PODF 98 #define IMX6QDL_CLK_VPU_AXI_PODF 99 #define IMX6QDL_CLK_CKO1_PODF 100 #define IMX6QDL_CLK_AXI 101 -#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102 -#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103 #define IMX6QDL_CLK_ARM 104 #define IMX6QDL_CLK_AHB 105 #define IMX6QDL_CLK_APBH_DMA 106 @@ -218,57 +214,62 @@ #define IMX6QDL_CLK_LVDS2_SEL 205 #define IMX6QDL_CLK_LVDS1_GATE 206 #define IMX6QDL_CLK_LVDS2_GATE 207 -#define IMX6QDL_CLK_ESAI_IPG 208 -#define IMX6QDL_CLK_ESAI_MEM 209 -#define IMX6QDL_CLK_ASRC_IPG 210 -#define IMX6QDL_CLK_ASRC_MEM 211 -#define IMX6QDL_CLK_LVDS1_IN 212 -#define IMX6QDL_CLK_LVDS2_IN 213 -#define IMX6QDL_CLK_ANACLK1 214 -#define IMX6QDL_CLK_ANACLK2 215 -#define IMX6QDL_PLL1_BYPASS_SRC 216 -#define IMX6QDL_PLL2_BYPASS_SRC 217 -#define IMX6QDL_PLL3_BYPASS_SRC 218 -#define IMX6QDL_PLL4_BYPASS_SRC 219 -#define IMX6QDL_PLL5_BYPASS_SRC 220 -#define IMX6QDL_PLL6_BYPASS_SRC 221 -#define IMX6QDL_PLL7_BYPASS_SRC 222 -#define IMX6QDL_CLK_PLL1 223 -#define IMX6QDL_CLK_PLL2 224 -#define IMX6QDL_CLK_PLL3 225 -#define IMX6QDL_CLK_PLL4 226 -#define IMX6QDL_CLK_PLL5 227 -#define IMX6QDL_CLK_PLL6 228 -#define IMX6QDL_CLK_PLL7 229 -#define IMX6QDL_PLL1_BYPASS 230 -#define IMX6QDL_PLL2_BYPASS 231 -#define IMX6QDL_PLL3_BYPASS 232 -#define IMX6QDL_PLL4_BYPASS 233 -#define IMX6QDL_PLL5_BYPASS 234 -#define IMX6QDL_PLL6_BYPASS 235 -#define IMX6QDL_PLL7_BYPASS 236 -#define IMX6QDL_CLK_GPT_3M 237 -#define IMX6QDL_CLK_VIDEO_27M 238 -#define IMX6QDL_CLK_MIPI_CORE_CFG 239 -#define IMX6QDL_CLK_MIPI_IPG 240 -#define IMX6QDL_CLK_CAAM_MEM 241 -#define IMX6QDL_CLK_CAAM_ACLK 242 -#define IMX6QDL_CLK_CAAM_IPG 243 -#define IMX6QDL_CLK_SPDIF_GCLK 244 -#define IMX6QDL_CLK_UART_SEL 245 -#define IMX6QDL_CLK_IPG_PER_SEL 246 -#define IMX6QDL_CLK_ECSPI_SEL 247 -#define IMX6QDL_CLK_CAN_SEL 248 -#define IMX6QDL_CLK_MMDC_CH1_AXI_CG 249 -#define IMX6QDL_CLK_PRE0 250 -#define IMX6QDL_CLK_PRE1 251 -#define IMX6QDL_CLK_PRE2 252 -#define IMX6QDL_CLK_PRE3 253 -#define IMX6QDL_CLK_PRG0_AXI 254 -#define IMX6QDL_CLK_PRG1_AXI 255 -#define IMX6QDL_CLK_PRG0_APB 256 -#define IMX6QDL_CLK_PRG1_APB 257 -#define IMX6QDL_CLK_PRE_AXI 258 -#define IMX6QDL_CLK_END 259 +#define IMX6QDL_CLK_ESAI_MEM 208 +#define IMX6QDL_CLK_LDB_DI0_DIV_7 209 +#define IMX6QDL_CLK_LDB_DI1_DIV_7 210 +#define IMX6QDL_CLK_LDB_DI0_DIV_SEL 211 +#define IMX6QDL_CLK_LDB_DI1_DIV_SEL 212 +#define IMX6QDL_CLK_VIDEO_27M 213 +#define IMX6QDL_CLK_DCIC1 214 +#define IMX6QDL_CLK_DCIC2 215 +#define IMX6QDL_CLK_GPT_3M 216 +#define IMX6QDL_CLK_ESAI_IPG 217 +#define IMX6QDL_CLK_ASRC_IPG 218 +#define IMX6QDL_CLK_ASRC_MEM 219 +#define IMX6QDL_CLK_LVDS1_IN 220 +#define IMX6QDL_CLK_LVDS2_IN 221 +#define IMX6QDL_CLK_ANACLK1 222 +#define IMX6QDL_CLK_ANACLK2 223 +#define IMX6QDL_PLL1_BYPASS_SRC 224 +#define IMX6QDL_PLL2_BYPASS_SRC 225 +#define IMX6QDL_PLL3_BYPASS_SRC 226 +#define IMX6QDL_PLL4_BYPASS_SRC 227 +#define IMX6QDL_PLL5_BYPASS_SRC 228 +#define IMX6QDL_PLL6_BYPASS_SRC 229 +#define IMX6QDL_PLL7_BYPASS_SRC 230 +#define IMX6QDL_CLK_PLL1 231 +#define IMX6QDL_CLK_PLL2 232 +#define IMX6QDL_CLK_PLL3 233 +#define IMX6QDL_CLK_PLL4 234 +#define IMX6QDL_CLK_PLL5 235 +#define IMX6QDL_CLK_PLL6 236 +#define IMX6QDL_CLK_PLL7 237 +#define IMX6QDL_PLL1_BYPASS 238 +#define IMX6QDL_PLL2_BYPASS 239 +#define IMX6QDL_PLL3_BYPASS 240 +#define IMX6QDL_PLL4_BYPASS 241 +#define IMX6QDL_PLL5_BYPASS 242 +#define IMX6QDL_PLL6_BYPASS 243 +#define IMX6QDL_PLL7_BYPASS 244 +#define IMX6QDL_CLK_AXI_ALT_SEL 245 +#define IMX6QDL_CAAM_MEM 246 +#define IMX6QDL_CAAM_ACLK 247 +#define IMX6QDL_CAAM_IPG 248 +#define IMX6QDL_CLK_SPDIF_GCLK 249 +#define IMX6QDL_CLK_UART_SEL 250 +#define IMX6QDL_CLK_IPG_PER_SEL 251 +#define IMX6QDL_CLK_ECSPI_SEL 252 +#define IMX6QDL_CLK_CAN_SEL 253 +#define IMX6QDL_CLK_MMDC_CH1_AXI_CG 254 +#define IMX6QDL_CLK_PRE0 255 +#define IMX6QDL_CLK_PRE1 256 +#define IMX6QDL_CLK_PRE2 257 +#define IMX6QDL_CLK_PRE3 258 +#define IMX6QDL_CLK_PRG0_AXI 259 +#define IMX6QDL_CLK_PRG1_AXI 260 +#define IMX6QDL_CLK_PRG0_APB 261 +#define IMX6QDL_CLK_PRG1_APB 262 +#define IMX6QDL_CLK_PRE_AXI 263 +#define IMX6QDL_CLK_END 264 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ |