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-rw-r--r--include/configs/canyonlands.h2
-rw-r--r--include/configs/lpd7a400-10.h1
-rw-r--r--include/configs/lpd7a404-10.h1
-rw-r--r--include/configs/lpd7a404.h2
-rw-r--r--include/configs/sbc8349.h2
5 files changed, 3 insertions, 5 deletions
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index 3dddccf..ac9b3c5 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -593,7 +593,7 @@
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
#endif /* !defined(CONFIG_ARCHES) */
-#define CONFIG_SYS_EBC_CFG 0xB8400000 /* EBC0_CFG */
+#define CONFIG_SYS_EBC_CFG 0xbfc00000
/*
* Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
diff --git a/include/configs/lpd7a400-10.h b/include/configs/lpd7a400-10.h
index 5f57c3a..91bf1fa 100644
--- a/include/configs/lpd7a400-10.h
+++ b/include/configs/lpd7a400-10.h
@@ -76,6 +76,5 @@
#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0x70000000)
#undef CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC_USE_IOFUNCS
#endif /* __LPD7A400_10_H */
diff --git a/include/configs/lpd7a404-10.h b/include/configs/lpd7a404-10.h
index 9074e28..b10e69d 100644
--- a/include/configs/lpd7a404-10.h
+++ b/include/configs/lpd7a404-10.h
@@ -76,6 +76,5 @@
#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0x70000000)
#undef CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC_USE_IOFUNCS
#endif /* __LPD7A404_10_H */
diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h
index 102c0af..557f389 100644
--- a/include/configs/lpd7a404.h
+++ b/include/configs/lpd7a404.h
@@ -72,7 +72,7 @@
#include <config_cmd_default.h>
#ifndef USE_920T_MMU
- #define CONFIG_CMD_PING)
+ #define CONFIG_CMD_PING
#undef CONFIG_CMD_CACHE
#else
#define CONFIG_CMD_DATE
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 4dea27d..7bef119 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -158,7 +158,7 @@
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \
- (2 << BR_PS_SHIFT) | /* 32 bit port size */ \
+ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
BR_V) /* valid */
#define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */