diff options
Diffstat (limited to 'include/configs')
35 files changed, 2649 insertions, 52 deletions
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 1fea6c3..50b3a03 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -88,6 +88,7 @@ # define _IO_BASE 0 #endif +#define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 #ifdef CONFIG_DRIVER_DM9000 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 2aba689..6f1b1a4 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -404,7 +404,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* controller 3, direct to uli, tgtid 3, Base address 8000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull #else #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 @@ -423,7 +423,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* controller 2, Slot 2, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 @@ -442,7 +442,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull #else #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index d8042fb..035874b 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -335,7 +335,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL #else #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index a39ff26..fddcce5 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -46,6 +46,7 @@ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -437,7 +438,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* controller 3, Slot 1, tgtid 3, Base address b000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull #else #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 @@ -456,7 +457,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* controller 2, direct to uli, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 @@ -475,7 +476,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* controller 1, Slot 2, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull #else #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 3f943aa..4b9bcca 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -96,6 +96,7 @@ #undef CONFIG_DDR_SPD #define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_FSL_DMA /* use DMA to init DDR ECC */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 43c2873..1db20bc 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -98,6 +98,7 @@ #undef CONFIG_DDR_SPD #define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_FSL_DMA /* use DMA to init DDR ECC */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h new file mode 100644 index 0000000..2553293 --- /dev/null +++ b/include/configs/XPEDITE5170.h @@ -0,0 +1,756 @@ +/* + * Copyright 2009 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * xpedite5170 board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_MPC86xx 1 /* MPC86xx */ +#define CONFIG_MPC8641 1 /* MPC8641 specific */ +#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */ +#define CONFIG_SYS_BOARD_NAME "XPedite5170" +#define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ +#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ +#define CONFIG_ALTIVEC 1 + +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +/* + * DDR config + */ +#define CONFIG_FSL_DDR2 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ +#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ +#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ + +/* + * virtual address to be used for temporary mappings. There + * should be 128k free at this VA. + */ +#define CONFIG_SYS_SCRATCH_VA 0xe0000000 + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(unsigned long dummy); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */ + +/* + * L2CR setup + */ +#define CONFIG_SYS_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) + +/* + * Diagnostics + */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x20000000 + +/* + * Memory map + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable + * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable + * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable + * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable + * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable + * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable + * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable + * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable + * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable + */ + +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_2 | LCRR_EADC_3) + +/* + * NAND flash configuration + */ +#define CONFIG_SYS_NAND_BASE 0xef800000 +#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2} +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define CONFIG_NAND_ACTL +#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */ +#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */ +#define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */ +#define CONFIG_SYS_NAND_ACTL_DELAY 25 +#define CONFIG_SYS_NAND_QUIET_TEST +#define CONFIG_JFFS2_NAND + +/* + * NOR flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xf8000000 +#define CONFIG_SYS_FLASH_BASE2 0xf0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \ + {0xf7f00000, 0xc0000} } +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ + +/* + * Chip select configuration + */ +/* NOR Flash 0 on CS0 */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ + BR_PS_16 |\ + BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\ + OR_GPCM_CSNT |\ + OR_GPCM_XACS |\ + OR_GPCM_ACS_DIV2 |\ + OR_GPCM_SCY_8 |\ + OR_GPCM_TRLX |\ + OR_GPCM_EHTR |\ + OR_GPCM_EAD) + +/* NOR Flash 1 on CS1 */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\ + BR_PS_16 |\ + BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM + +/* NAND flash on CS2 */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\ + BR_PS_8 |\ + BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\ + OR_GPCM_BCTLD |\ + OR_GPCM_CSNT |\ + OR_GPCM_ACS_DIV4 |\ + OR_GPCM_SCY_4 |\ + OR_GPCM_TRLX |\ + OR_GPCM_EHTR) + +/* Optional NAND flash on CS3 */ +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\ + BR_PS_8 |\ + BR_V) +#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM + +/* + * Use L1 as initial stack + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 +#define CONFIG_SYS_INIT_RAM_END 0x00004000 + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} +#define CONFIG_BAUDRATE 115200 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SYS_I2C_SPEED 100000 /* M41T00 only supports 100 KHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE + +/* PEX8518 slave I2C interface */ +#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 + +/* I2C DS1631 temperature sensor */ +#define CONFIG_SYS_I2C_DS1621_ADDR 0x48 +#define CONFIG_DTT_DS1621 +#define CONFIG_DTT_SENSORS { 0 } + +/* I2C EEPROM - AT24C128B */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 + +/* GPIO/EEPROM/SRAM */ +#define CONFIG_DS4510 +#define CONFIG_SYS_I2C_DS4510_ADDR 0x51 + +/* GPIO */ +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 +#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c +#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e +#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f +#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 + +/* + * PU = pulled high, PD = pulled low + * I = input, O = output, IO = input/output + */ +/* PCA9557 @ 0x18*/ +#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ +#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ + +/* PCA9557 @ 0x1c*/ +#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ +#define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */ +#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ +#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ +#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ +#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ +#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ +#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ + +/* PCA9557 @ 0x1e*/ +#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */ +#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */ + +/* PCA9557 @ 0x1f */ +#define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */ +#define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */ +#define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */ +#define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* PCIE1 - PEX8518 */ +#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ + +/* PCIE2 - VPX P1 */ +#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ + +/* + * Networking options + */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define CONFIG_HAS_ETH0 + +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_PHY_ADDR 2 +#define TSEC2_PHYIDX 0 +#define CONFIG_HAS_ETH1 + +/* + * BAT mappings + */ +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) +#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\ + BATU_BL_1M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU +#endif + +/* + * BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U + +/* + * BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 1G PCI-Express 1 Memory + */ +#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\ + BATU_BL_1G |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U + +/* + * BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M PCI-Express 2 Memory + */ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\ + BATU_BL_512M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U + +/* + * BAT3 1M Cache-inhibited, guarded + * 0xe000_0000 1M CCSR + */ +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\ + BATU_BL_1M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U + +/* + * BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 + */ +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\ + BATU_BL_32M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U + +/* + * BAT5 128K Cacheable, non-guarded + * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\ + BATL_PP_RW |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\ + BATU_BL_128K |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L +#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U + +/* + * BAT6 256M Cache-inhibited, guarded + * 0xf000_0000 256M FLASH + */ +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\ + BATU_BL_256M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\ + BATL_PP_RW |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U + +/* Map the last 1M of flash where we're running from reset */ +#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE |\ + BATU_BL_1M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ + BATL_PP_RW |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY + +/* + * BAT7 64M Cache-inhibited, guarded + * 0xe800_0000 64K NAND FLASH + * 0xe804_0000 128K DUART Registers + */ +#define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\ + BATU_BL_512K |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U + +/* + * Command configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DS4510 +#define CONFIG_CMD_DS4510_INFO +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ +#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ +#define CONFIG_PANIC_HANG /* do not reset board on panic */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ + +/* + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + +/* + * Flash memory map: + * fffc0000 - ffffffff Pri FDT (256KB) + * fff80000 - fffbffff Pri U-Boot Environment (256 KB) + * fff00000 - fff7ffff Pri U-Boot (512 KB) + * fef00000 - ffefffff Pri OS image (16MB) + * f8000000 - feefffff Pri OS Use/Filesystem (111MB) + * + * f7fc0000 - f7ffffff Sec FDT (256KB) + * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB) + * f7f00000 - f7f7ffff Sec U-Boot (512 KB) + * f6f00000 - f7efffff Sec OS image (16MB) + * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) + */ +#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff00000) +#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f00000) +#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfffc0000) +#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7fc0000) +#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) +#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000) + +#define CONFIG_PROG_UBOOT1 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_UBOOT2 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_BOOT_OS_NET \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "if test -n $fdtaddr; then " \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "bootm $osaddr - $fdtaddr; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi; " \ + "else; " \ + "bootm $osaddr; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS1 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS2 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT1 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT2 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=yes\0" \ + "download_cmd=tftp\0" \ + "console_args=console=ttyS0,115200\0" \ + "root_args=root=/dev/nfs rw\0" \ + "misc_args=ip=on\0" \ + "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ + "bootfile=/home/user/file\0" \ + "osfile=/home/user/uImage-XPedite5170\0" \ + "fdtfile=/home/user/xpedite5170.dtb\0" \ + "ubootfile=/home/user/u-boot.bin\0" \ + "fdtaddr=c00000\0" \ + "osaddr=0x1000000\0" \ + "loadaddr=0x1000000\0" \ + "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ + "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ + "prog_os1="CONFIG_PROG_OS1"\0" \ + "prog_os2="CONFIG_PROG_OS2"\0" \ + "prog_fdt1="CONFIG_PROG_FDT1"\0" \ + "prog_fdt2="CONFIG_PROG_FDT2"\0" \ + "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ + "bootcmd_flash1=run set_bootargs; " \ + "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ + "bootcmd_flash2=run set_bootargs; " \ + "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ + "bootcmd=run bootcmd_flash1\0" +#endif /* __CONFIG_H */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 4f6b640..83e05b3 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -131,6 +131,7 @@ #define CONFIG_SYS_NO_FLASH 1 /* Ethernet */ +#define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x30000000 #define DM9000_IO CONFIG_DM9000_BASE diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index 06f2765..3db8171 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF518F_EZBRD_H__ #define __CONFIG_BF518F_EZBRD_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -88,8 +88,9 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST #define CONFIG_SPI_FLASH_STMICRO @@ -143,6 +144,4 @@ */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index afd9bb2..97853af 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF526_EZBRD_H__ #define __CONFIG_BF526_EZBRD_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -106,7 +106,7 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_SST @@ -185,6 +185,4 @@ void __led_toggle(led_id_t mask); */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index 0fe5fa5..0d02354 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF527_EZKIT_H__ #define __CONFIG_BF527_EZKIT_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -105,7 +105,7 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO @@ -167,6 +167,4 @@ */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index eb08890..f896cb0 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF533_EZKIT_H__ #define __CONFIG_BF533_EZKIT_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -152,6 +152,4 @@ */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index d8e1ffc..c03561c 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF533_STAMP_H__ #define __CONFIG_BF533_STAMP_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -89,7 +89,7 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SPI_FLASH_SPANSION @@ -102,9 +102,9 @@ */ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_OFFSET 0x10000 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_OFFSET 0x4000 @@ -117,6 +117,21 @@ #else #define ENV_IS_EMBEDDED_CUSTOM #endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif /* @@ -241,6 +256,4 @@ void __led_toggle(led_id_t mask); */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h new file mode 100644 index 0000000..23c2d33 --- /dev/null +++ b/include/configs/bf537-minotaur.h @@ -0,0 +1,201 @@ +/* + * U-boot - Configuration file for CSP Minotaur board + * + * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch> + * Minotaur config, brushed up for official uClinux dist. + * Parallel flash support disabled, SPI flash boot command + * added ('run flashboot'). + * + * Flash image map: + * + * 0x00000000 u-boot bootstrap + * 0x00010000 environment + * 0x00020000 u-boot code + * 0x00030000 uImage.initramfs + * + */ + +#ifndef __CONFIG_BF537_MINOTAUR_H__ +#define __CONFIG_BF537_MINOTAUR_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf537-0.2 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 20 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_SIZE 32 +#define CONFIG_MEM_ADD_WDTH 9 + +#define CONFIG_EBIU_SDRRC_VAL 0x306 +#define CONFIG_EBIU_SDGCTL_VAL 0x91114d + +#define CONFIG_EBIU_AMGCTL_VAL 0xFF +#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_SYS_MALLOC_LEN (128 << 10) + + +/* + * Network Settings + */ +#ifndef __ADSPBF534__ +#define CONFIG_BFIN_MAC +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 +#endif +#ifdef CONFIG_BFIN_MAC +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME bf537-minotaur +#endif + +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_ROOTPATH /romfs +/* Use a fixed MAC address for booting up. Firstboot linux + * must fetch a valid MAC from the production server. */ +#define CONFIG_ETHADDR 02:80:ad:20:31:42 + + +/* + * Flash Settings + */ +/* We don't have a parallel flash chip there */ +#define CONFIG_SYS_NO_FLASH + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define ENV_IS_EMBEDDED_CUSTOM + + +/* + * I2C settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_MISC_INIT_R + +#define CONFIG_BAUDRATE 57600 +#define CONFIG_UART_CONSOLE 0 + +#define CONFIG_PANIC_HANG 1 +#define CONFIG_RTC_BFIN 1 +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_LOADS_ECHO 1 + +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) +# define CONFIG_BOOTDELAY -1 +#else +# define CONFIG_BOOTDELAY 5 +#endif + +#include <config_cmd_default.h> + +#ifdef CONFIG_BFIN_MAC +# define CONFIG_CMD_DHCP +# define CONFIG_CMD_PING +#else +# undef CONFIG_CMD_NET +#endif + +#define CONFIG_CMD_BOOTLDR +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#undef CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_SF + +#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" +#define CONFIG_SYS_PROMPT "minotaur> " + +#define BOOT_ENV_SETTINGS \ + "update=tftpboot $(loadaddr) u-boot.ldr;" \ + "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \ + "sf erase 0 0x30000;" \ + "sf write $(loadaddr) 0 $(filesize)" \ + "flashboot=sf read 0x1000000 0x30000 0x320000;" \ + "bootm 0x1000000\0" +#ifdef CONFIG_BFIN_MAC +# define NETWORK_ENV_SETTINGS \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux;" \ + "run ramargs;run addip;bootelf\0" \ + "nfsboot=tftpboot $(loadaddr) linux;" \ + "run nfsargs;run addip;bootelf\0" +#else +# define NETWORK_ENV_SETTINGS +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \ + NETWORK_ENV_SETTINGS \ + "ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \ + BOOT_ENV_SETTINGS + +#endif diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h new file mode 100644 index 0000000..0f908ef --- /dev/null +++ b/include/configs/bf537-pnav.h @@ -0,0 +1,185 @@ +/* + * U-boot - Configuration file for BF537 PNAV board + */ + +#ifndef __CONFIG_BF537_PNAV_H__ +#define __CONFIG_BF537_PNAV_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf537-0.2 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 24576000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 20 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 4 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 10 +#define CONFIG_MEM_SIZE 64 + +#define CONFIG_EBIU_SDRRC_VAL 0x3b7 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL 0xFF +#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +#ifndef __ADSPBF534__ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_BFIN_MAC +#define CONFIG_RMII +#define CONFIG_NET_MULTI 1 +#endif +#define CONFIG_HOSTNAME bf537-pnav +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:24:21:18 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 71 + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + + +/* + * Env Storage Settings + */ +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) +#define ENV_IS_EMBEDDED_CUSTOM +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x4000 +#else +#define ENV_IS_EMBEDDED +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR 0x20004000 +#define CONFIG_ENV_OFFSET 0x4000 +#endif +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_SECT_SIZE 0x2000 +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif + + +/* + * NAND Settings + */ +#define CONFIG_NAND_PLAT + +#define CONFIG_SYS_NAND_BASE 0x20100000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) +#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) +#define BFIN_NAND_READY PF12 +#define BFIN_NAND_WRITE(addr, cmd) \ + do { \ + bfin_write8(addr, cmd); \ + SSYNC(); \ + } while (0) + +#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) +#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) +#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTHIO() & BFIN_NAND_READY) +#define NAND_PLAT_INIT() \ + do { \ + bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \ + bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \ + bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \ + } while (0) + + +/* + * I2C settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_BFIN +#define CONFIG_UART_CONSOLE 0 + +/* JFFS Partition offset set */ +#define CONFIG_SYS_JFFS2_FIRST_BANK 0 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15 + +#define CONFIG_BOOTCOMMAND "run nandboot" +#define CONFIG_BOOTARGS_ROOT "/dev/mtdblock1 rw rootfstype=yaffs" + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h new file mode 100644 index 0000000..727b7e7 --- /dev/null +++ b/include/configs/bf537-srv1.h @@ -0,0 +1,201 @@ +/* + * U-boot - Configuration file for CSP Minotaur board + * + * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch> + * Minotaur config, brushed up for official uClinux dist. + * Parallel flash support disabled, SPI flash boot command + * added ('run flashboot'). + * + * Flash image map: + * + * 0x00000000 u-boot bootstrap + * 0x00010000 environment + * 0x00020000 u-boot code + * 0x00030000 uImage.initramfs + * + */ + +#ifndef __CONFIG_BF537_SRV1_H__ +#define __CONFIG_BF537_SRV1_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf537-0.2 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 22118400 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 20 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_SIZE 32 +#define CONFIG_MEM_ADD_WDTH 9 + +#define CONFIG_EBIU_SDRRC_VAL 0x2ac +#define CONFIG_EBIU_SDGCTL_VAL 0x91110d + +#define CONFIG_EBIU_AMGCTL_VAL 0xFF +#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_SYS_MALLOC_LEN (384 << 10) + + +/* + * Network Settings + */ +#ifndef __ADSPBF534__ +#define CONFIG_BFIN_MAC +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 +#endif +#ifdef CONFIG_BFIN_MAC +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME bf537-srv1 +#endif + +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_ROOTPATH /romfs +/* Use a fixed MAC address for booting up. Firstboot linux + * must fetch a valid MAC from the production server. */ +#define CONFIG_ETHADDR 02:80:ad:20:31:42 + + +/* + * Flash Settings + */ +/* We don't have a parallel flash chip there */ +#define CONFIG_SYS_NO_FLASH + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define ENV_IS_EMBEDDED_CUSTOM + + +/* + * I2C settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_MISC_INIT_R + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_UART_CONSOLE 0 + +#define CONFIG_PANIC_HANG 1 +#define CONFIG_RTC_BFIN 1 +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_LOADS_ECHO 1 + +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) +# define CONFIG_BOOTDELAY -1 +#else +# define CONFIG_BOOTDELAY 5 +#endif + +#include <config_cmd_default.h> + +#ifdef CONFIG_BFIN_MAC +# define CONFIG_CMD_DHCP +# define CONFIG_CMD_PING +#else +# undef CONFIG_CMD_NET +#endif + +#define CONFIG_CMD_BOOTLDR +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#undef CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_SF + +#define CONFIG_BOOTCOMMAND "run flashboot" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" +#define CONFIG_SYS_PROMPT "srv1> " + +#define BOOT_ENV_SETTINGS \ + "update=tftpboot $(loadaddr) u-boot.ldr;" \ + "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \ + "sf erase 0 0x30000;" \ + "sf write $(loadaddr) 0 $(filesize)" \ + "flashboot=sf read 0x1000000 0x30000 0x320000;" \ + "bootm 0x1000000\0" +#ifdef CONFIG_BFIN_MAC +# define NETWORK_ENV_SETTINGS \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux;" \ + "run ramargs;run addip;bootelf\0" \ + "nfsboot=tftpboot $(loadaddr) linux;" \ + "run nfsargs;run addip;bootelf\0" +#else +# define NETWORK_ENV_SETTINGS +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \ + NETWORK_ENV_SETTINGS \ + "ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \ + BOOT_ENV_SETTINGS + +#endif diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 3e5862d..0a86e83 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF537_STAMP_H__ #define __CONFIG_BF537_STAMP_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -87,7 +87,7 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SPI_FLASH_SPANSION @@ -100,9 +100,9 @@ */ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_OFFSET 0x10000 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_OFFSET 0x4000 @@ -115,6 +115,21 @@ #else #define ENV_IS_EMBEDDED_CUSTOM #endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif /* @@ -257,6 +272,4 @@ */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index a7fb92e..535687f 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF538F_EZKIT_H__ #define __CONFIG_BF538F_EZKIT_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -83,7 +83,7 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SPI_FLASH_SPANSION @@ -111,6 +111,21 @@ #else #define ENV_IS_EMBEDDED_CUSTOM #endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif /* @@ -134,6 +149,4 @@ */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index ae9fb36..dbcd2af 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF548_EZKIT_H__ #define __CONFIG_BF548_EZKIT_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -61,7 +61,7 @@ #define CONFIG_EBIU_FCTL_VAL (BCLK_4) #define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH) -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) #define CONFIG_SYS_MALLOC_LEN (768 * 1024) @@ -93,7 +93,7 @@ */ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO @@ -206,6 +206,4 @@ */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - #endif diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index ef2019f..4779a97 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_BF561_EZKIT_H__ #define __CONFIG_BF561_EZKIT_H__ -#include <asm/blackfin-config-pre.h> +#include <asm/config-pre.h> /* @@ -88,6 +88,23 @@ #else #define ENV_IS_EMBEDDED_CUSTOM #endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + lib_generic/zlib.o (.text .text.*); \ + board/bf561-ezkit/bf561-ezkit.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif /* @@ -149,6 +166,4 @@ */ #include <configs/bfin_adi_common.h> -#include <asm/blackfin-config-post.h> - -#endif /* __CONFIG_EZKIT561_H__ */ +#endif diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index e0be07b..4149a29 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -71,6 +71,7 @@ # define CONFIG_CMD_STRINGS # if defined(__ADSPBF51x__) || defined(__ADSPBF52x__) || defined(__ADSPBF54x__) # define CONFIG_CMD_OTP +# define CONFIG_CMD_SPIBOOTLDR # endif #endif @@ -102,14 +103,19 @@ #else # define CONFIG_BOOTDELAY 5 #endif -#define CONFIG_BOOTCOMMAND "run ramboot" +#ifndef CONFIG_BOOTCOMMAND +# define CONFIG_BOOTCOMMAND "run ramboot" +#endif #ifdef CONFIG_VIDEO # define CONFIG_BOOTARGS_VIDEO "console=tty0 " #else # define CONFIG_BOOTARGS_VIDEO "" #endif +#ifndef CONFIG_BOOTARGS_ROOT +# define CONFIG_BOOTARGS_ROOT "/dev/mtdblock0 rw" +#endif #define CONFIG_BOOTARGS \ - "root=/dev/mtdblock0 rw " \ + "root=" CONFIG_BOOTARGS_ROOT " " \ "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \ "earlyprintk=" \ "serial," \ @@ -117,7 +123,17 @@ MK_STR(CONFIG_BAUDRATE) " " \ CONFIG_BOOTARGS_VIDEO \ "console=ttyBF0," MK_STR(CONFIG_BAUDRATE) - +#if defined(CONFIG_CMD_NAND) +# define NAND_ENV_SETTINGS \ + "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \ + "nandboot=" \ + "nand read $(loadaddr) 0x20000 0x100000;" \ + "run nandargs;" \ + "bootm" \ + "\0" +#else +# define NAND_ENV_SETTINGS +#endif #if defined(CONFIG_CMD_NET) # if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) # define UBOOT_ENV_FILE "u-boot.bin" @@ -155,19 +171,23 @@ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \ "$(hostname):eth0:off" \ "\0" \ + \ + "ramfile=uImage\0" \ "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \ "ramboot=" \ - "tftp $(loadaddr) uImage;" \ + "tftp $(loadaddr) $(ramfile);" \ "run ramargs;" \ "run addip;" \ "bootm" \ "\0" \ + \ + "nfsfile=vmImage\0" \ "nfsargs=set bootargs " \ "root=/dev/nfs rw " \ "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \ "\0" \ "nfsboot=" \ - "tftp $(loadaddr) vmImage;" \ + "tftp $(loadaddr) $(nfsfile);" \ "run nfsargs;" \ "run addip;" \ "bootm" \ @@ -176,6 +196,7 @@ # define NETWORK_ENV_SETTINGS #endif #define CONFIG_EXTRA_ENV_SETTINGS \ + NAND_ENV_SETTINGS \ NETWORK_ENV_SETTINGS \ "flashboot=bootm 0x20100000\0" @@ -196,4 +217,9 @@ # define CONFIG_NET_RETRY_COUNT 20 #endif +/* + * Misc Settings + */ +#define CONFIG_LZMA + #endif diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h new file mode 100644 index 0000000..1e4c716 --- /dev/null +++ b/include/configs/blackstamp.h @@ -0,0 +1,273 @@ +/* + * U-boot - Configuration file for BlackStamp board + * Configuration by Ben Matthews for UR LLE using bf533-stamp.h + * as a template + * See http://blackfin.uclinux.org/gf/project/blackstamp/ + */ + +#ifndef __CONFIG_BLACKSTAMP_H__ +#define __CONFIG_BLACKSTAMP_H__ + +#include <asm/config-pre.h> + +/* + * Debugging: Set these options if you're having problems + */ +/* + * #define CONFIG_DEBUG_EARLY_SERIAL + * #define DEBUG + * #define CONFIG_DEBUG_DUMP + * #define CONFIG_DEBUG_DUMP_SYMS +*/ +#define CONFIG_PANIC_HANG 0 + +/* CPU Options + * Be sure to set the Silicon Revision Correctly + */ +#define CONFIG_BFIN_CPU bf532-0.5 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER + +/* + * Board settings + */ +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20300300 + +/* FLASH/ETHERNET uses the same address range + * Depending on what you have the CPLD doing + * this probably isn't needed + */ +#define SHARED_RESOURCES 1 + +/* Is I2C bit-banged? */ +#undef CONFIG_SOFT_I2 + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 16 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 3 + +/* + * Network settings + */ + +#ifdef CONFIG_DRIVER_SMC91111 +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME blackstamp +#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs +#define CONFIG_SYS_AUTOLOAD "no" + +/* To remove hardcoding and enable MAC storage in EEPROM */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ +#endif + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x40000 +#define ENV_IS_EMBEDDED_CUSTOM + +/* + * SDRAM settings & memory map + */ + +#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */ + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_SYS_MALLOC_LEN (384 << 10) + +/* + * Command settings + */ + +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE 1 +#define CONFIG_ENV_OVERWRITE 1 + +#include <config_cmd_default.h> + +#ifdef CONFIG_DRIVER_SMC91111 +# define CONFIG_CMD_DHCP +# define CONFIG_CMD_PING +#else +# undef CONFIG_CMD_NET +#endif + +#ifdef CONFIG_SOFT_I2C +# define CONFIG_CMD_I2C +#endif + +#define CONFIG_CMD_BOOTLDR +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_CPLBINFO +#define CONFIG_CMD_DATE +#define CONFIG_CMD_SF +#define CONFIG_CMD_ELF + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_BOOTARGS \ + "root=/dev/mtdblock0 rw " \ + "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \ + "earlyprintk=" \ + "serial," \ + "uart" MK_STR(CONFIG_UART_CONSOLE) "," \ + MK_STR(CONFIG_BAUDRATE) " " \ + "console=ttyBF0," MK_STR(CONFIG_BAUDRATE) + +#if defined(CONFIG_CMD_NET) +# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) +# define UBOOT_ENV_FILE "u-boot.bin" +# else +# define UBOOT_ENV_FILE "u-boot.ldr" +# endif +# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) +# ifdef CONFIG_SPI +# define UBOOT_ENV_UPDATE \ + "eeprom write $(loadaddr) 0x0 $(filesize)" +# else +# define UBOOT_ENV_UPDATE \ + "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \ + "sf erase 0 0x40000;" \ + "sf write $(loadaddr) 0 $(filesize)" +# endif +# else +# define UBOOT_ENV_UPDATE \ + "protect off 0x20000000 0x2003FFFF;" \ + "erase 0x20000000 0x2003FFFF;" \ + "cp.b $(loadaddr) 0x20000000 $(filesize)" +# endif +# define NETWORK_ENV_SETTINGS \ + "ubootfile=" UBOOT_ENV_FILE "\0" \ + "update=" \ + "tftp $(loadaddr) $(ubootfile);" \ + UBOOT_ENV_UPDATE \ + "\0" \ + "addip=set bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \ + "$(hostname):eth0:off" \ + "\0" \ + "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \ + "ramboot=" \ + "tftp $(loadaddr) uImage;" \ + "run ramargs;" \ + "run addip;" \ + "bootm" \ + "\0" \ + "nfsargs=set bootargs " \ + "root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \ + "\0" \ + "nfsboot=" \ + "tftp $(loadaddr) vmImage;" \ + "run nfsargs;" \ + "run addip;" \ + "bootm" \ + "\0" +#else +# define NETWORK_ENV_SETTINGS +#endif + +/* + * Console settings + */ +#define CONFIG_BAUDRATE 57600 +#define CONFIG_LOADS_ECHO 1 +#define CONFIG_UART_CONSOLE 0 + +/* + * I2C settings + * By default PF2 is used as SDA and PF3 as SCL on the Stamp board + * Located on the expansion connector on pins 86/85 + * Note these pins are arbitrarily chosen because we aren't using + * them yet. You can (and probably should) change these values! + */ +#ifdef CONFIG_SOFT_I2C + +#define PF_SCL PF9 +#define PF_SDA PF8 + +#define I2C_INIT do { *pFIO_DIR |= PF_SCL; SSYNC(); } while (0) +#define I2C_ACTIVE do { *pFIO_DIR |= PF_SDA; *pFIO_INEN &= ~PF_SDA; SSYNC(); } while (0) +#define I2C_TRISTATE do { *pFIO_DIR &= ~PF_SDA; *pFIO_INEN |= PF_SDA; SSYNC(); } while (0) +#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0) +#define I2C_SDA(bit) \ + do { \ + if (bit) \ + *pFIO_FLAG_S = PF_SDA; \ + else \ + *pFIO_FLAG_C = PF_SDA; \ + SSYNC(); \ + } while (0) +#define I2C_SCL(bit) \ + do { \ + if (bit) \ + *pFIO_FLAG_S = PF_SCL; \ + else \ + *pFIO_FLAG_C = PF_SCL; \ + SSYNC(); \ + } while (0) +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0xFE +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_RTC_BFIN 1 + +/* + * Serial Flash Infomation + */ +#define CONFIG_BFIN_SPI +/* For the M25P64 SCK Should be Kept < 20Mhz */ +#define CONFIG_ENV_SPI_MAX_HZ 20000000 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + +/* + * FLASH organization and environment definitions + */ + +#define CONFIG_EBIU_AMGCTL_VAL 0xFF +#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3 +#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983 +#define CONFIG_EBIU_SDRRC_VAL 0x268 +#define CONFIG_EBIU_SDGCTL_VAL 0x911109 + +/* Even though Rev C boards have Parallel Flash + * We aren't supporting it. Newer versions of the + * hardware don't support Parallel Flash at all. + */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_FLASH + +#endif diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h new file mode 100644 index 0000000..79d06fb --- /dev/null +++ b/include/configs/cm-bf527.h @@ -0,0 +1,135 @@ +/* + * U-boot - Configuration file for CM-BF527 board + */ + +#ifndef __CONFIG_CM_BF527_H__ +#define __CONFIG_CM_BF527_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf527-0.0 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 21 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 4 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL 0x3f8 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * NAND Settings + * (can't be used sametime as ethernet) + */ +/* #define CONFIG_BFIN_NFC */ +#ifdef CONFIG_BFIN_NFC +#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 +#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_CMD_NAND +#endif + + +/* + * Network Settings + */ +#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \ + !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC) +#define ADI_CMDS_NETWORK 1 +#define CONFIG_BFIN_MAC +#define CONFIG_RMII +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 +#endif +#define CONFIG_HOSTNAME cm-bf527 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 64 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR 0x20008000 +#define CONFIG_ENV_OFFSET 0x8000 +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define ENV_IS_EMBEDDED_CUSTOM + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_BFIN +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h new file mode 100644 index 0000000..ea548e9 --- /dev/null +++ b/include/configs/cm-bf533.h @@ -0,0 +1,102 @@ +/* + * U-boot - Configuration file for CM-BF533 board + */ + +#ifndef __CONFIG_CM_BF533_H__ +#define __CONFIG_CM_BF533_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf533-0.3 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 22 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 8192) - (7 + 2)) +#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3) + +#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20200300 +#define CONFIG_HOSTNAME cm-bf533 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 16 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x10000 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h new file mode 100644 index 0000000..021b631 --- /dev/null +++ b/include/configs/cm-bf537e.h @@ -0,0 +1,137 @@ +/* + * U-boot - Configuration file for CM-BF537E board + */ + +#ifndef __CONFIG_CM_BF537E_H__ +#define __CONFIG_CM_BF537E_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf537-0.2 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 21 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 4 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL 0x3f8 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +#ifndef __ADSPBF534__ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_BFIN_MAC +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 +#endif +#define CONFIG_HOSTNAME cm-bf537e +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 32 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) +#define ENV_IS_EMBEDDED +#else +#define ENV_IS_EMBEDDED_CUSTOM +#endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_BFIN +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h new file mode 100644 index 0000000..93c2239 --- /dev/null +++ b/include/configs/cm-bf548.h @@ -0,0 +1,139 @@ +/* + * U-boot - Configuration file for cm-bf548 board + */ + +#ifndef __CONFIG_CM_BF548_H__ +#define __CONFIG_CM_BF548_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf548-0.0 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 21 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 4 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 10 +#define CONFIG_MEM_SIZE 64 + +#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE +#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222 +#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021 + +/* Default bank mapping: + * Async Bank 0 - 32MB Burst Flash + * Async Bank 1 - Ethernet + * Async Bank 2 - Nothing + * Async Bank 3 - Nothing + */ +#define CONFIG_EBIU_AMGCTL_VAL 0xFF +#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 +#define CONFIG_EBIU_FCTL_VAL (BCLK_4) +#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH) + +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) +#define CONFIG_SYS_MALLOC_LEN (640 * 1024) + + +/* + * Network Settings + */ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_DRIVER_SMC911X 1 +#define CONFIG_DRIVER_SMC911X_BASE 0x24000000 +#define CONFIG_DRIVER_SMC911X_16_BIT +#define CONFIG_HOSTNAME cm-bf548 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:24:31:91 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 259 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR 0x20008000 +#define CONFIG_ENV_OFFSET 0x8000 +#define CONFIG_ENV_SIZE 0x8000 +#define ENV_IS_EMBEDDED_CUSTOM + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_RTC_BFIN +#define CONFIG_UART_CONSOLE 1 + +#ifndef __ADSPBF542__ +/* Don't waste time transferring a logo over the UART */ +# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) +# define CONFIG_VIDEO +# endif +# define CONFIG_DEB_DMA_URGENT +#endif + +/* Define if want to do post memory test */ +#undef CONFIG_POST +#ifdef CONFIG_POST +#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */ +#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ +#endif + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h new file mode 100644 index 0000000..53a2580 --- /dev/null +++ b/include/configs/cm-bf561.h @@ -0,0 +1,102 @@ +/* + * U-boot - Configuration file for CM-BF561 board + */ + +#ifndef __CONFIG_CM_BF561_H__ +#define __CONFIG_CM_BF561_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf561-0.3 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 22 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 64 + +#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 4096) - (7 + 2)) +#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3) + +#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | B3_PEN | B2_PEN | B1_PEN | B0_PEN | AMBEN_ALL | AMCKEN) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x28000300 +#define CONFIG_HOSTNAME cm-bf561 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:cf */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 67 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x10000 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 6c5d065..96b6afc 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -109,6 +109,7 @@ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI /*=====================*/ /* Flash & Environment */ /*=====================*/ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 6612cb3..9cb9838 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -77,6 +77,7 @@ #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_NET_MULTI /*=====================*/ /* Flash & Environment */ /*=====================*/ diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 6c1dc11..a47620f 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -74,6 +74,7 @@ #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_NET_MULTI /* Flash & Environment */ #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 893729c..82901b3 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -109,6 +109,7 @@ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI /*=====================*/ /* Flash & Environment */ /*=====================*/ diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h new file mode 100644 index 0000000..066859f --- /dev/null +++ b/include/configs/ibf-dsp561.h @@ -0,0 +1,145 @@ +/* + * U-boot - Configuration file for IBF-DSP561 board + */ + +#ifndef __CONFIG_IBF_DSP561__H__ +#define __CONFIG_IBF_DSP561__H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf561-0.5 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 24 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 64 + +#define CONFIG_EBIU_SDRRC_VAL 0x377 +#define CONFIG_EBIU_SDGCTL_VAL 0x91998d +#define CONFIG_EBIU_SDBCTL_VAL 0x15 + +#define CONFIG_EBIU_AMGCTL_VAL 0x3F +#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Flash Settings + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ +/* The BF561-EZKIT uses a top boot flash */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR 0x20004000 +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) +#define ENV_IS_EMBEDDED +#else +#define ENV_IS_EMBEDDED_CUSTOM +#endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + lib_generic/zlib.o (.text .text.*); \ + board/ibf-dsp561/ibf-dsp561.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif + + +/* + * I2C Settings + */ +#define CONFIG_SOFT_I2C 1 +#define PF_SCL 0x1/*PF0*/ +#define PF_SDA 0x2/*PF1*/ + +#ifdef CONFIG_SOFT_I2C +#define I2C_INIT do { *pFIO0_DIR |= PF_SCL; SSYNC(); } while (0) +#define I2C_ACTIVE do { *pFIO0_DIR |= PF_SDA; *pFIO0_INEN &= ~PF_SDA; SSYNC(); } while (0) +#define I2C_TRISTATE do { *pFIO0_DIR &= ~PF_SDA; *pFIO0_INEN |= PF_SDA; SSYNC(); } while (0) +#define I2C_READ ((*pFIO0_FLAG_D & PF_SDA) != 0) +#define I2C_SDA(bit) \ + do { \ + if (bit) \ + *pFIO0_FLAG_S = PF_SDA; \ + else \ + *pFIO0_FLAG_C = PF_SDA; \ + SSYNC(); \ + } while (0) +#define I2C_SCL(bit) \ + do { \ + if (bit) \ + *pFIO0_FLAG_S = PF_SCL; \ + else \ + *pFIO0_FLAG_C = PF_SCL; \ + SSYNC(); \ + } while (0) +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 +#endif + + +/* + * Misc Settings + */ +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index 893c3d3..5556714 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -255,6 +255,7 @@ #define CONFIG_SYS_CS5U_VAL 0x00008400 #define CONFIG_SYS_CS5L_VAL 0x00000D03 +#define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x16000000 #define DM9000_IO CONFIG_DM9000_BASE diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h new file mode 100644 index 0000000..9794e1b --- /dev/null +++ b/include/configs/tcm-bf537.h @@ -0,0 +1,139 @@ +/* + * U-boot - Configuration file for TCM-BF537 board + */ + +#ifndef __CONFIG_TCM_BF537_H__ +#define __CONFIG_TCM_BF537_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf537-0.2 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 21 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 4 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL 0x3f8 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +/* TCM-BF537E has no PHY on it, but EXT-BF5xx-USB/Ethernet board has */ +#ifndef __ADSPBF534__ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_BFIN_MAC +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 +#endif +#define CONFIG_HOSTNAME tcm-bf537 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 67 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) +#define ENV_IS_EMBEDDED +#else +#define ENV_IS_EMBEDDED_CUSTOM +#endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_BFIN +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + + +#endif diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index 49045fd..bfa7157 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -278,6 +278,7 @@ #define CONFIG_SYS_MCIO0_VAL 0x00008407 #define CONFIG_SYS_MCIO1_VAL 0x0000c108 +#define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x08000000 #define DM9000_IO CONFIG_DM9000_BASE |