diff options
Diffstat (limited to 'include/configs')
38 files changed, 919 insertions, 3488 deletions
diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h deleted file mode 100644 index 2d4fc77..0000000 --- a/include/configs/ADNPESC1.h +++ /dev/null @@ -1,689 +0,0 @@ -/* - * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net> - * Stephan Linz <linz@li-pro.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*********************************************************************** - * Include the whole NIOS CPU configuration. - * - * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! - * - ***********************************************************************/ - -#if defined(CONFIG_NIOS_BASE_32) -#include <configs/ADNPESC1_base_32.h> -#else -#error *** CONFIG_SYS_ERROR: you have to setup right NIOS CPU configuration -#endif - -/*------------------------------------------------------------------------ - * BOARD/CPU -- TOP-LEVEL - *----------------------------------------------------------------------*/ -#define CONFIG_NIOS 1 /* NIOS-32 core */ -#define CONFIG_ADNPESC1 1 /* SSV ADNP/ESC1 board */ -#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock */ -#define CONFIG_SYS_HZ 1000 /* 1 msec time tick */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM) - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_SDRAM_SIZE != 0) - -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_NIOS_CPU_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_NIOS_CPU_SDRAM_SIZE - -#else -#error *** CONFIG_SYS_ERROR: you have to setup any SDRAM in NIOS CPU config -#endif - -#if defined(CONFIG_SYS_NIOS_CPU_SRAM_BASE) && defined(CONFIG_SYS_NIOS_CPU_SRAM_SIZE) - -#define CONFIG_SYS_SRAM_BASE CONFIG_SYS_NIOS_CPU_SRAM_BASE -#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_NIOS_CPU_SRAM_SIZE - -#else - -#undef CONFIG_SYS_SRAM_BASE -#undef CONFIG_SYS_SRAM_SIZE - -#endif - -#define CONFIG_SYS_VECT_BASE CONFIG_SYS_NIOS_CPU_VEC_BASE - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - For the most part, you can put things pretty - * much anywhere. This is pretty flexible for Nios. So here we make some - * arbitrary choices & assume that the monitor is placed at the end of - * a memory resource (so you must make sure TEXT_BASE is chosen - * appropriately -- this is very important if you plan to move your - * memory to another place as configured at this time !!!). - * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_NIOS_CPU_FLASH_BASE -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_NIOS_CPU_FLASH_SIZE -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size */ - -#else -#error *** CONFIG_SYS_ERROR: you have to setup any Flash memory in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * ENVIRONMENT - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) - -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ - -/* Mem addr of environment */ -#if defined(CONFIG_NIOS_BASE_32) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -#else -#error *** CONFIG_SYS_ERROR: you have to setup the environment base address CONFIG_ENV_ADDR -#endif - -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ - -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* NO Environment */ -#endif - -/*------------------------------------------------------------------------ - * NIOS APPLICATION CODE BASE AREA - *----------------------------------------------------------------------*/ -#if ((CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) == 0x1050000) -#define CONFIG_SYS_ADNPESC1_UPDATE_LOAD_ADDR "0x2000100" -#define CONFIG_SYS_ADNPESC1_NIOS_APPL_ENTRY "0x1050000" -#define CONFIG_SYS_ADNPESC1_NIOS_APPL_IDENT "0x105000c" -#define CONFIG_SYS_ADNPESC1_NIOS_APPL_END "0x11fffff" -#define CONFIG_SYS_ADNPESC1_FILESYSTEM_BASE "0x1200000" -#define CONFIG_SYS_ADNPESC1_FILESYSTEM_END "0x17fffff" -#else -#error *** CONFIG_SYS_ERROR: missing right appl.code base configuration, expand your config.h -#endif -#define CONFIG_SYS_ADNPESC1_NIOS_IDENTIFIER "Nios" - -/*------------------------------------------------------------------------ - * BOOT ENVIRONMENT - *----------------------------------------------------------------------*/ -#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */ -#define CONFIG_SYS_ADNPESC1_SLED_BOOT_OFF "sled boot off; " -#define CONFIG_SYS_ADNPESC1_SLED_RED_BLINK "sled red blink; " -#else -#define CONFIG_SYS_ADNPESC1_SLED_BOOT_OFF -#define CONFIG_SYS_ADNPESC1_SLED_RED_BLINK -#endif - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTCOMMAND \ - "if itest.s *$appl_ident_addr == \"$appl_ident_str\"; " \ - "then " \ - "wd off; " \ - CONFIG_SYS_ADNPESC1_SLED_BOOT_OFF \ - "go $appl_entry_addr; " \ - "else " \ - CONFIG_SYS_ADNPESC1_SLED_RED_BLINK \ - "echo *** missing \"$appl_ident_str\" at $appl_ident_addr; "\ - "echo *** invalid application at $appl_entry_addr; " \ - "echo *** stop bootup...; " \ - "fi" - -/*------------------------------------------------------------------------ - * EXTRA ENVIRONMENT - *----------------------------------------------------------------------*/ -#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */ -#define CONFIG_SYS_ADNPESC1_SLED_YELLO_ON "sled yellow on; " -#define CONFIG_SYS_ADNPESC1_SLED_YELLO_OFF "sled yellow off; " -#else -#define CONFIG_SYS_ADNPESC1_SLED_YELLO_ON -#define CONFIG_SYS_ADNPESC1_SLED_YELLO_OFF -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_allowed=0\0" \ - "update_load_addr=" CONFIG_SYS_ADNPESC1_UPDATE_LOAD_ADDR "\0" \ - "appl_entry_addr=" CONFIG_SYS_ADNPESC1_NIOS_APPL_ENTRY "\0" \ - "appl_end_addr=" CONFIG_SYS_ADNPESC1_NIOS_APPL_END "\0" \ - "appl_ident_addr=" CONFIG_SYS_ADNPESC1_NIOS_APPL_IDENT "\0" \ - "appl_ident_str=" CONFIG_SYS_ADNPESC1_NIOS_IDENTIFIER "\0" \ - "appl_name=ADNPESC1/base32/linux.bin\0" \ - "appl_update=" \ - "if itest.b $update_allowed != 0; " \ - "then " \ - CONFIG_SYS_ADNPESC1_SLED_YELLO_ON \ - "tftp $update_load_addr $appl_name; " \ - "protect off $appl_entry_addr $appl_end_addr; " \ - "era $appl_entry_addr $appl_end_addr; " \ - "cp.b $update_load_addr $appl_entry_addr $filesize; "\ - CONFIG_SYS_ADNPESC1_SLED_YELLO_OFF \ - "else " \ - "echo *** update not allowed (update_allowed=$update_allowed); "\ - "fi\0" \ - "fs_base_addr=" CONFIG_SYS_ADNPESC1_FILESYSTEM_BASE "\0" \ - "fs_end_addr=" CONFIG_SYS_ADNPESC1_FILESYSTEM_END "\0" \ - "fs_name=ADNPESC1/base32/romfs.img\0" \ - "fs_update=" \ - "if itest.b $update_allowed != 0; " \ - "then " \ - CONFIG_SYS_ADNPESC1_SLED_YELLO_ON \ - "tftp $update_load_addr $fs_name; " \ - "protect off $fs_base_addr $fs_end_addr; " \ - "era $fs_base_addr $fs_end_addr; " \ - "cp.b $update_load_addr $fs_base_addr $filesize; "\ - CONFIG_SYS_ADNPESC1_SLED_YELLO_OFF \ - "else " \ - "echo *** update not allowed (update_allowed=$update_allowed); "\ - "fi\0" \ - "uboot_name=ADNPESC1/base32/u-boot.bin\0" \ - "uboot_loadnrun=" \ - "if ping $serverip; " \ - "then " \ - CONFIG_SYS_ADNPESC1_SLED_YELLO_ON \ - "tftp $update_load_addr $uboot_name; " \ - "wd off; " \ - "go $update_load_addr; " \ - "else " \ - "echo *** missing connection to $serverip; " \ - "echo *** check your network and try again...; "\ - "fi\0" - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_UART_NUMS != 0) - -#define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_NIOS_CPU_UART0 /* 1st UART is Cons. */ - -#if (CONFIG_SYS_NIOS_CPU_UART0_BR != 0) -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE CONFIG_SYS_NIOS_CPU_UART0_BR -#else -#undef CONFIG_SYS_NIOS_FIXEDBAUD -#define CONFIG_BAUDRATE 115200 -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one UART in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, - * so an avalon bus timer is required. - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_TIMER_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_TICK_TIMER) - -#if (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 0) - -#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER0 /* TIMER0 as tick */ -#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER0_IRQ - -#if (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 1) /* fixed period */ - -#if (CONFIG_SYS_NIOS_CPU_TIMER0_PER >= CONFIG_SYS_HZ) -#define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER0_PER / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ -#endif - -#undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 0) /* variable period */ - -#if (CONFIG_SYS_HZ <= 1000) -#define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 -#endif - -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - -#else -#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER0_FP correct -#endif - -#elif (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 1) - -#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER1 /* TIMER1 as tick */ -#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER1_IRQ - -#if (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 1) /* fixed period */ - -#if (CONFIG_SYS_NIOS_CPU_TIMER1_PER >= CONFIG_SYS_HZ) -#define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER1_PER / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ -#endif - -#undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 0) /* variable period */ - -#if (CONFIG_SYS_HZ <= 1000) -#define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 -#endif - -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - -#else -#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER1_FP correct -#endif - -#endif /* CONFIG_SYS_NIOS_CPU_TICK_TIMER */ - -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one TIMER in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * WATCHDOG (or better MAX823 supervisory circuite access) - *----------------------------------------------------------------------*/ -#define CONFIG_HW_WATCHDOG 1 /* board specific WD */ - -#ifdef CONFIG_HW_WATCHDOG - -/* MAX823 supervisor -- watchdog enable port at: */ -#if (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 0) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO0 /* PIO0 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 1) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO1 /* PIO1 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 2) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO2 /* PIO2 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 3) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO3 /* PIO3 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 4) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO4 /* PIO4 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 5) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO5 /* PIO5 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 6) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO6 /* PIO6 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 7) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO7 /* PIO7 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 8) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO8 /* PIO8 */ -#elif (CONFIG_SYS_NIOS_CPU_WDENA_PIO == 9) -#define CONFIG_HW_WDENA_BASE CONFIG_SYS_NIOS_CPU_PIO9 /* PIO9 */ -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one WDENA_PIO in NIOS CPU config -#endif - -/* MAX823 supervisor -- watchdog trigger port at: */ -#if (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 0) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO0 /* PIO0 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 1) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO1 /* PIO1 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 2) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO2 /* PIO2 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 3) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO3 /* PIO3 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 4) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO4 /* PIO4 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 5) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO5 /* PIO5 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 6) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO6 /* PIO6 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 7) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO7 /* PIO7 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 8) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO8 /* PIO8 */ -#elif (CONFIG_SYS_NIOS_CPU_WDTOG_PIO == 9) -#define CONFIG_HW_WDTOG_BASE CONFIG_SYS_NIOS_CPU_PIO9 /* PIO9 */ -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one WDTOG_PIO in NIOS CPU config -#endif - -#if defined(CONFIG_NIOS_BASE_32) /* NIOS CPU specifics */ -#define CONFIG_HW_WDENA_BIT 0 /* WD enable @ Bit 0 */ -#define CONFIG_HW_WDTOG_BIT 0 /* WD trigger @ Bit 0 */ -#define CONFIG_HW_WDPORT_WRONLY 1 /* each WD port wr/only*/ -#else -#error *** CONFIG_SYS_ERROR: missing watchdog bit configuration, expand your config.h -#endif - -#endif /* CONFIG_HW_WATCHDOG */ - -/*------------------------------------------------------------------------ - * SERIAL PERIPHAREL INTERFACE - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_SPI_NUMS == 1) - -#define CONFIG_NIOS_SPI 1 /* SPI support active */ -#define CONFIG_SYS_NIOS_SPIBASE CONFIG_SYS_NIOS_CPU_SPI0 -#define CONFIG_SYS_NIOS_SPIBITS CONFIG_SYS_NIOS_CPU_SPI0_BITS - -#define CONFIG_RTC_DS1306 1 /* Dallas 1306 real time clock */ -#define CONFIG_SYS_SPI_RTC_DEVID 0 /* as 1st SPI device */ - -#else -#undef CONFIG_NIOS_SPI /* NO SPI support */ -#endif - -/*------------------------------------------------------------------------ - * Ethernet -- needs work! - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_LAN_NUMS == 1) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ - -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC91111_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) -#define CONFIG_SMC_USE_32_BIT 1 -#else /* no */ -#undef CONFIG_SMC_USE_32_BIT -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */ - - /********************************************/ - /* !!! CS8900 is __not__ tested on NIOS !!! */ - /********************************************/ -#define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* Using CS8900 */ -#define CONFIG_CS8900_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + \ - CONFIG_SYS_NIOS_CPU_LAN0_OFFS) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) -#undef CONFIG_CS8900_BUS16 -#define CONFIG_CS8900_BUS32 -#else /* no */ -#define CONFIG_CS8900_BUS16 -#undef CONFIG_CS8900_BUS32 -#endif - -#else -#error *** CONFIG_SYS_ERROR: invalid LAN0 chip type, check your NIOS CPU config -#endif - -#define CONFIG_ETHADDR 02:80:ae:20:60:6f -#define CONFIG_NETMASK 255.255.255.248 -#define CONFIG_IPADDR 192.168.161.84 -#define CONFIG_SERVERIP 192.168.161.85 - -#else -#error *** CONFIG_SYS_ERROR: you have to setup just one LAN only or expand your config.h -#endif - -/*------------------------------------------------------------------------ - * STATUS LEDs - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_LED_PIO) - -#if (CONFIG_SYS_NIOS_CPU_LED_PIO == 0) - -#define STATUS_LED_BASE CONFIG_SYS_NIOS_CPU_PIO0 -#define STATUS_LED_BITS CONFIG_SYS_NIOS_CPU_PIO0_BITS -#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -#if (CONFIG_SYS_NIOS_CPU_PIO0_TYPE == 1) -#define STATUS_LED_WRONLY 1 -#else -#undef STATUS_LED_WRONLY -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 1) - -#define STATUS_LED_BASE CONFIG_SYS_NIOS_CPU_PIO1 -#define STATUS_LED_BITS CONFIG_SYS_NIOS_CPU_PIO1_BITS -#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -#if (CONFIG_SYS_NIOS_CPU_PIO1_TYPE == 1) -#define STATUS_LED_WRONLY 1 -#else -#undef STATUS_LED_WRONLY -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 2) - -#define STATUS_LED_BASE CONFIG_SYS_NIOS_CPU_PIO2 -#define STATUS_LED_BITS CONFIG_SYS_NIOS_CPU_PIO2_BITS -#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -#if (CONFIG_SYS_NIOS_CPU_PIO2_TYPE == 1) -#define STATUS_LED_WRONLY 1 -#else -#undef STATUS_LED_WRONLY -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 3) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO3 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 4) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO4 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 5) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO5 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 6) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO6 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 7) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO7 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 8) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO8 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 9) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO9 not supported, expand your config.h - -#else -#error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_LED_PIO in right case -#endif - -#define CONFIG_STATUS_LED 1 /* enable status led driver */ - -#define STATUS_LED_BIT (1 << 0) /* LED[0] */ -#define STATUS_LED_STATE STATUS_LED_BLINKING -#define STATUS_LED_BOOT_STATE STATUS_LED_OFF -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) /* ca. 1 Hz */ -#define STATUS_LED_BOOT 0 /* boot LED */ - -#if (STATUS_LED_BITS > 1) -#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */ -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 10) /* ca. 5 Hz */ -#define STATUS_LED_RED 1 /* fail LED */ -#endif - -#if (STATUS_LED_BITS > 2) -#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */ -#define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) /* ca. 1 Hz */ -#define STATUS_LED_YELLOW 2 /* info LED */ -#endif - -#if (STATUS_LED_BITS > 3) -#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */ -#define STATUS_LED_STATE3 STATUS_LED_OFF -#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2) /* ca. 1 Hz */ -#define STATUS_LED_GREEN 3 /* info LED */ -#endif - -#define STATUS_LED_PAR 1 /* makes status_led.h happy */ - -#endif /* CONFIG_SYS_NIOS_CPU_PIO_NUMS */ - -/*------------------------------------------------------------------------ - * Diagnostics / Power On Self Tests - *----------------------------------------------------------------------*/ -#define CONFIG_POST CONFIG_SYS_POST_RTC -#define CONFIG_SYS_NIOS_POST_WORD_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_REISER -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG - -#if (CONFIG_SYS_NIOS_CPU_SPI_NUMS == 1) -#define CONFIG_CMD_DATE -#define CONFIG_CMD_SPI -#endif - -/*------------------------------------------------------------------------ - * KGDB - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 9600 -#endif - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser - undef to save memory */ -#define CONFIG_SYS_PROMPT "ADNPESC1 > " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max number of command args*/ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "[]> " -#endif - -/* Default load address */ -#if (CONFIG_SYS_SRAM_SIZE != 0) - -/* default in SRAM */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SRAM_BASE - -#elif (CONFIG_SYS_SDRAM_SIZE != 0) - -/* default in SDRAM */ -#if (CONFIG_SYS_SDRAM_BASE == CONFIG_SYS_NIOS_CPU_VEC_BASE) -#if 1 -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_NIOS_CPU_VEC_SIZE) -#else -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x400000) -#endif -#else -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE -#endif - -#else -#undef CONFIG_SYS_LOAD_ADDR /* force error break */ -#endif - -/* MEM test area */ -#if (CONFIG_SYS_SDRAM_SIZE != 0) - -/* SDRAM begin to stack area (1MB stack) */ -#if (CONFIG_SYS_SDRAM_BASE == CONFIG_SYS_NIOS_CPU_VEC_BASE) -#if 0 -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_NIOS_CPU_VEC_SIZE) -#else -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400000) -#endif -#else -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#endif - -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - (1024 * 1024)) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - (1024 * 1024)) - -#else -#undef CONFIG_SYS_MEMTEST_START /* force error break */ -#undef CONFIG_SYS_MEMTEST_END -#endif - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ADNPESC1_base_32.h b/include/configs/ADNPESC1_base_32.h deleted file mode 100644 index 1fe8d09..0000000 --- a/include/configs/ADNPESC1_base_32.h +++ /dev/null @@ -1,431 +0,0 @@ -/* - * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net> - * Stephan Linz <linz@li-pro.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_ADNPESC1_BASE_32_H -#define __CONFIG_ADNPESC1_BASE_32_H - -/* - * NIOS CPU configuration. (PART OF configs/ADNPESC1.h) - * - * Here we must define CPU dependencies. Any unsupported option have to - * be undefined or defined with zero, example CPU without data cache / OCI: - * - * #define CONFIG_SYS_NIOS_CPU_ICACHE 4096 - * #define CONFIG_SYS_NIOS_CPU_DCACHE 0 - * #undef CONFIG_SYS_NIOS_CPU_OCI_BASE - * #undef CONFIG_SYS_NIOS_CPU_OCI_SIZE - */ - -/* CPU core */ -#define CONFIG_SYS_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ -#define CONFIG_SYS_NIOS_CPU_ICACHE (0) /* instruction cache */ -#define CONFIG_SYS_NIOS_CPU_DCACHE (0) /* data cache */ -#define CONFIG_SYS_NIOS_CPU_REG_NUMS 512 /* number of register */ -#define CONFIG_SYS_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_STACK 0x03000000 /* stack top addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_BASE 0x02000000 /* IRQ vectors addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CONFIG_SYS_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CONFIG_SYS_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */ -#define CONFIG_SYS_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* The offset address in flash to check for the Nios signature "Ni". - * (see GM_FlashExec in germs_monitor.s) */ -#define CONFIG_SYS_NIOS_CPU_EXES_OFFS 0x0C - -/* on-chip extensions */ -#undef CONFIG_SYS_NIOS_CPU_RAM_BASE /* on chip RAM addr */ -#undef CONFIG_SYS_NIOS_CPU_RAM_SIZE /* 64 KB size */ - -#define CONFIG_SYS_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */ -#define CONFIG_SYS_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#undef CONFIG_SYS_NIOS_CPU_OCI_BASE /* OCI core addr */ -#undef CONFIG_SYS_NIOS_CPU_OCI_SIZE /* size */ - -/* timer */ -#define CONFIG_SYS_NIOS_CPU_TIMER_NUMS 1 /* number of timer */ - -#define CONFIG_SYS_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CONFIG_SYS_NIOS_CPU_UART_NUMS 2 /* number of uarts */ - -#define CONFIG_SYS_NIOS_CPU_UART0 0x00000800 /* UART0 addr */ -#define CONFIG_SYS_NIOS_CPU_UART0_IRQ 17 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CONFIG_SYS_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_SB 1 /* stop bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CONFIG_SYS_NIOS_CPU_UART0_HS 1 /* handshake: no(0) */ - /* crts(1) */ -#define CONFIG_SYS_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -#define CONFIG_SYS_NIOS_CPU_UART1 0x00000820 /* UART1 addr */ -#define CONFIG_SYS_NIOS_CPU_UART1_IRQ 18 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */ -#define CONFIG_SYS_NIOS_CPU_UART1_DB 8 /* data bit */ -#define CONFIG_SYS_NIOS_CPU_UART1_SB 1 /* stop bit */ -#define CONFIG_SYS_NIOS_CPU_UART1_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CONFIG_SYS_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CONFIG_SYS_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* serial peripheral i/o */ -#define CONFIG_SYS_NIOS_CPU_SPI_NUMS 1 /* number of spis */ - -#define CONFIG_SYS_NIOS_CPU_SPI0 0x000008c0 /* SPI0 addr */ -#define CONFIG_SYS_NIOS_CPU_SPI0_IRQ 25 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_SPI0_BITS 16 /* data bit */ -#define CONFIG_SYS_NIOS_CPU_SPI0_MA 1 /* is master: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_SPI0_SLN 1 /* num slaves */ -#define CONFIG_SYS_NIOS_CPU_SPI0_TCLK 250000 /* clock (Hz) */ -#define CONFIG_SYS_NIOS_CPU_SPI0_TDELAY 2 /* delay (usec) */ -#define CONFIG_SYS_NIOS_CPU_SPI0_FB 0 /* first bit msb(0) */ - /* lsb(1) */ - -/* parallel i/o */ -#define CONFIG_SYS_NIOS_CPU_PIO_NUMS 14 /* number of parports */ - -#define CONFIG_SYS_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO0_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO0_BITS 8 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO0_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO1_BITS 8 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO2 0x00000880 /* PIO2 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO2_BITS 4 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO2_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO3 0x00000890 /* PIO3 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO3_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO3_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO3 0x00000890 /* PIO3 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO3_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO3_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO4 0x000008a0 /* PIO4 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO4_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO4_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO5 0x000008b0 /* PIO5 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO5_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO5_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO5_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO6 0x00000900 /* PIO6 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO6_IRQ 20 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO6_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO6_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO7 0x00000910 /* PIO7 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO7_IRQ 31 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO7_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO7_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO8 0x00000920 /* PIO8 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO8_IRQ 32 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO8_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO8_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO8_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO8_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO8_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO9 0x00000930 /* PIO9 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO9_IRQ 33 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO9_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO9_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO9_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO9_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO9_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO10 0x00000940 /* PIO10 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO10_IRQ 34 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO10_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO10_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO10_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO10_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO10_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO11 0x00000950 /* PIO11 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO11_IRQ 35 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO11_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO11_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO11_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO11_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO11_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO12 0x00000960 /* PIO12 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO12_IRQ 36 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO12_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO12_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO12_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO12_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO12_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO13 0x00000970 /* PIO113 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO13_IRQ 37 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO13_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO13_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO13_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO13_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO13_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CONFIG_SYS_NIOS_CPU_IDE_NUMS 2 /* number of IDE contr. */ - -#define CONFIG_SYS_NIOS_CPU_IDE0 0x00001000 /* IDE0 addr */ -#define CONFIG_SYS_NIOS_CPU_IDE0_IRQ 36 /* IRQ */ - -#define CONFIG_SYS_NIOS_CPU_IDE1 0x00001020 /* IDE1 addr */ -#define CONFIG_SYS_NIOS_CPU_IDE1_IRQ 37 /* IRQ */ - -/* memory accessibility */ -#undef CONFIG_SYS_NIOS_CPU_SRAM_BASE /* board SRAM addr */ -#undef CONFIG_SYS_NIOS_CPU_SRAM_SIZE /* 1 MB size */ - -#define CONFIG_SYS_NIOS_CPU_SDRAM_BASE 0x02000000 /* board SDRAM addr */ -#define CONFIG_SYS_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CONFIG_SYS_NIOS_CPU_FLASH_BASE 0x01000000 /* board Flash addr */ -#define CONFIG_SYS_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CONFIG_SYS_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CONFIG_SYS_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */ -#define CONFIG_SYS_NIOS_CPU_LAN0_OFFS (0) /* offset */ -#define CONFIG_SYS_NIOS_CPU_LAN0_IRQ 20 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_LAN0_BUSW 16 /* buswidth*/ -#define CONFIG_SYS_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: openmac(2) */ - /* ex: alteramac(3) */ - -/* external extension */ -#define CONFIG_SYS_NIOS_CPU_CS0_BASE 0x40000000 /* board EXT0 addr */ -#define CONFIG_SYS_NIOS_CPU_CS0_SIZE (16*1024*1024) /* max. 16 MB size */ - -#define CONFIG_SYS_NIOS_CPU_CS1_BASE 0x41000000 /* board EXT1 addr */ -#define CONFIG_SYS_NIOS_CPU_CS1_SIZE (16*1024*1024) /* max. 16 MB size */ - -#define CONFIG_SYS_NIOS_CPU_CS2_BASE 0x42000000 /* board EXT2 addr */ -#define CONFIG_SYS_NIOS_CPU_CS2_SIZE (16*1024*1024) /* max. 16 MB size */ - -#define CONFIG_SYS_NIOS_CPU_CS3_BASE 0x43000000 /* board EXT3 addr */ -#define CONFIG_SYS_NIOS_CPU_CS3_SIZE (16*1024*1024) /* max. 16 MB size */ - -/* symbolic redefinition (undef, if not present) */ -#define CONFIG_SYS_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/ -#undef CONFIG_SYS_NIOS_CPU_USER_TIMER /* TIMERx: users choice */ - -#define CONFIG_SYS_NIOS_CPU_PORTA_PIO 0 /* PIO0: Port A */ -#define CONFIG_SYS_NIOS_CPU_PORTB_PIO 1 /* PIO1: Port D */ -#define CONFIG_SYS_NIOS_CPU_PORTC_PIO 2 /* PIO2: Port C */ -#define CONFIG_SYS_NIOS_CPU_RCM_PIO 3 /* PIO3: RCM jumper */ -#define CONFIG_SYS_NIOS_CPU_WDENA_PIO 4 /* PIO4: watchdog enable*/ -#define CONFIG_SYS_NIOS_CPU_WDTOG_PIO 5 /* PIO5: watchdog trigg.*/ - -/* PIOx: LED bar */ -#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */ -#define CONFIG_SYS_NIOS_CPU_LED_PIO CONFIG_SYS_NIOS_CPU_PORTA_PIO -#else -#undef CONFIG_SYS_NIOS_CPU_LED_PIO /* no LED bar */ -#endif - -#endif /* __CONFIG_ADNPESC1_BASE_32_H */ diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h deleted file mode 100644 index 0dfb23b..0000000 --- a/include/configs/AmigaOneG3SE.h +++ /dev/null @@ -1,404 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the AmigaOneG3SE board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_AMIGAONEG3SE 1 - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_VERY_BIG_RAM 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passed to Linux in Hz */ - -#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk_size=4096" - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_AMIGA_PARTITION - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NET -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FDC -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_USB -#define CONFIG_CMD_BSP -#define CONFIG_CMD_PCI - - -#define CONFIG_PCI 1 -/* #define CONFIG_PCI_SCAN_SHOW 1 */ -#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ - -#define atoi(x) simple_strtoul(x,NULL,10) - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "] " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ -/* #undef CONFIG_SYS_HUSH_PARSER */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00500000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#define CONFIG_SYS_FLASH_MAX_SIZE 0x00080000 -/* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x80000000 /* 2G */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* Reserve 512 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve 128 kB for malloc() */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \ - CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* Size in bytes reserved for initial data - */ -/* HJF: used to be 0x400000 */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_END 0x8000 -#define CONFIG_SYS_GBL_DATA_SIZE 128 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_INIT_RAM_LOCK - -/* - * Temporary buffer for serial data until the real serial driver - * is initialised (memtest will destroy this buffer) - */ -#define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_SCONSOLE_SIZE 0x0002000 - -/* SDRAM 0 - 256MB - */ - -/*HJF: #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U*/ - -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -/* PCI Range - */ -#define CONFIG_SYS_DBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) -/* HJF: -#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR) | BATL_PP_RW) -#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW ) -#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP) -*/ - -/* Init RAM in the CPU DCache (no backing memory) - */ -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -/* This used to be commented out */ -#define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L -/* This here too */ -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U - - -/* I/O and PCI memory at 0xf0000000 - */ -#define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_BUS_HZ 133000000 /* bus speed - 100 mhz */ -#define CONFIG_SYS_CPU_CLK 133000000 -#define CONFIG_SYS_BUS_CLK 133000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* Max number of sectors in one bank */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -/* - * Environment is stored in NVRAM. - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_ADDR 0xFD0E0000 /* This should be 0xFD0E0000, but we skip bytes to - * protect softex's settings for now. - * Original 768 bytes where not enough. - */ -#define CONFIG_ENV_SIZE 0x8000 /* Size of the Environment. See comment above */ - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 /* stdin/stdout/stderr are in environment */ -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 -#define CONFIG_ENV_OVERWRITE 1 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * L2 cache - */ -#define CONFIG_SYS_L2 -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*----------------------------------------------------------------------- - * IDE ATAPI Configuration - */ - -#define CONFIG_ATAPI 1 -#define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_IDE_MAXDEVICE 4 -#define CONFIG_ISO_PARTITION 1 - -#define CONFIG_SYS_ATA_BASE_ADDR 0xFE000000 /* was: via_get_base_addr() */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1F0 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 - -#define CONFIG_SYS_ATA_REG_OFFSET 0 -#define CONFIG_SYS_ATA_DATA_OFFSET 0 -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 - -/*----------------------------------------------------------------------- - * Disk-On-Chip configuration - */ - -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CONFIG_SYS_DOC_SUPPORT_2000 -#undef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM - -/*----------------------------------------------------------------------- - RTC -*/ -#define CONFIG_RTC_MC146818 - -/*----------------------------------------------------------------------- - * NS16550 Configuration - */ - -#define CONFIG_SYS_NS16550 - -#define CONFIG_SYS_NS16550_COM1 0xFE0003F8 -#define CONFIG_SYS_NS16550_COM2 0xFE0002F8 - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -/* base address for ISA I/O - */ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xFE000000 - -/* ISA Interrupt stuff (taken from JWL) */ - -#define ISA_INT1_OCW1 0x21 -#define ISA_INT2_OCW1 0xA1 -#define ISA_INT1_OCW2 0x20 -#define ISA_INT2_OCW2 0xA0 -#define ISA_INT1_OCW3 0x20 -#define ISA_INT2_OCW3 0xA0 - -#define ISA_INT1_ICW1 0x20 -#define ISA_INT2_ICW1 0xA0 -#define ISA_INT1_ICW2 0x21 -#define ISA_INT2_ICW2 0xA1 -#define ISA_INT1_ICW3 0x21 -#define ISA_INT2_ICW3 0xA1 -#define ISA_INT1_ICW4 0x21 -#define ISA_INT2_ICW4 0xA1 - - -/* - * misc - */ - -#define CONFIG_NET_MULTI -#define CONFIG_SYS_BOARD_ASM_INIT -#define CONFIG_LAST_STAGE_INIT - -/* #define CONFIG_ETHADDR 00:09:D2:10:00:76 */ -/* #define CONFIG_IPADDR 192.168.0.2 */ -/* #define CONFIG_NETMASK 255.255.255.240 */ -/* #define CONFIG_GATEWAYIP 192.168.0.3 */ - -#define CONFIG_3COM -/* #define CONFIG_BOOTP_RANDOM_DELAY */ - -/* - * USB configuration - */ -#define CONFIG_USB_UHCI 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_USB_KEYBOARD 1 -#define CONFIG_SYS_STDIO_DEREGISTER 1 /* needed by CONFIG_USB_KEYBOARD */ - -/* - * Autoboot stuff - */ -#define CONFIG_BOOTDELAY 5 /* Boot automatically after five seconds */ -#define CONFIG_PREBOOT "" -#define CONFIG_BOOTCOMMAND "fdcboot; diskboot" -#define CONFIG_MENUPROMPT \ - "Press any key to interrupt autoboot: %2d ", bootdelay -#define CONFIG_MENUKEY ' ' -#define CONFIG_MENUCOMMAND "menu" -/* #define CONFIG_AUTOBOOT_KEYED */ - -/* - * Extra ENV stuff - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "stdout=vga\0" \ - "stdin=ps2kbd\0" \ - "ide_doreset=on\0" \ - "ide_maxbus=2\0" \ - "ide_cd_timeout=30\0" \ - "menucmd=menu\0" \ - "pci_irqa=9\0" \ - "pci_irqa_select=edge\0" \ - "pci_irqb=10\0" \ - "pci_irqb_select=edge\0" \ - "pci_irqc=11\0" \ - "pci_irqc_select=edge\0" \ - "pci_irqd=7\0" \ - "pci_irqd_select=edge\0" - - -/* #define CONFIG_MII 1 */ -/* #define CONFIG_BITBANGMII 1 */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h index 40a1c40..4d83786 100644 --- a/include/configs/BAB7xx.h +++ b/include/configs/BAB7xx.h @@ -436,9 +436,8 @@ extern unsigned char scsi_sym53c8xx_ccf; extern unsigned long bab7xx_get_bus_freq (void); extern unsigned long bab7xx_get_gclk_freq (void); #endif -#define CONFIG_SYS_BUS_HZ bab7xx_get_bus_freq() -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ -#define CONFIG_SYS_CPU_CLK bab7xx_get_gclk_freq() +#define CONFIG_SYS_BUS_CLK bab7xx_get_bus_freq() +#define CONFIG_SYS_CPU_CLK bab7xx_get_gclk_freq() /* * For booting Linux, the board info and command line data diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 1c8c68b..f2d51f7 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -234,8 +234,7 @@ #define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ -#define CONFIG_SYS_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h index 160871b..910933a 100644 --- a/include/configs/DB64360.h +++ b/include/configs/DB64360.h @@ -318,8 +318,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ /*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ -#define CONFIG_SYS_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ #define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ #define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */ diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h index 06fd157..765eaaf 100644 --- a/include/configs/DB64460.h +++ b/include/configs/DB64460.h @@ -256,8 +256,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ /*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ -#define CONFIG_SYS_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ #define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ #define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */ diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h deleted file mode 100644 index cdc488b..0000000 --- a/include/configs/DK1C20.h +++ /dev/null @@ -1,555 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * Stephan Linz <linz@li-pro.net> - * - * CompactFlash/IDE: - * (C) Copyright 2004, Shlomo Kut <skut@vyyo.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*********************************************************************** - * Include the whole NIOS CPU configuration. - * - * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! - * - ***********************************************************************/ - -#if defined(CONFIG_NIOS_SAFE_32) -#include <configs/DK1C20_safe_32.h> -#elif defined(CONFIG_NIOS_STANDARD_32) -#include <configs/DK1C20_standard_32.h> -#else -#error *** CONFIG_SYS_ERROR: you have to setup right NIOS CPU configuration -#endif - -/*------------------------------------------------------------------------ - * BOARD/CPU -- TOP-LEVEL - *----------------------------------------------------------------------*/ -#define CONFIG_NIOS 1 /* NIOS-32 core */ -#define CONFIG_DK1C20 1 /* Cyclone DK-1C20 board*/ -#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock */ -#define CONFIG_SYS_HZ 1000 /* 1 msec time tick */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM) - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_SDRAM_SIZE != 0) - -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_NIOS_CPU_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_NIOS_CPU_SDRAM_SIZE - -#else -#error *** CONFIG_SYS_ERROR: you have to setup any SDRAM in NIOS CPU config -#endif - -#define CONFIG_SYS_SRAM_BASE CONFIG_SYS_NIOS_CPU_SRAM_BASE -#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_NIOS_CPU_SRAM_SIZE -#define CONFIG_SYS_VECT_BASE CONFIG_SYS_NIOS_CPU_VEC_BASE - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - For the most part, you can put things pretty - * much anywhere. This is pretty flexible for Nios. So here we make some - * arbitrary choices & assume that the monitor is placed at the end of - * a memory resource (so you must make sure TEXT_BASE is chosen - * appropriately). - * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_NIOS_CPU_FLASH_BASE -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_NIOS_CPU_FLASH_SIZE -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ - -#else -#error *** CONFIG_SYS_ERROR: you have to setup any Flash memory in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * ENVIRONMENT - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) - -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Mem addr of env */ -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ - -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* NO Environment */ -#endif - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_UART_NUMS != 0) - -#define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_NIOS_CPU_UART0 /* 1st UART is Cons. */ - -#if (CONFIG_SYS_NIOS_CPU_UART0_BR != 0) -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE CONFIG_SYS_NIOS_CPU_UART0_BR -#else -#undef CONFIG_SYS_NIOS_FIXEDBAUD -#define CONFIG_BAUDRATE 115200 -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one UART in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, - * so an avalon bus timer is required. - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_TIMER_NUMS != 0) - -#if (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 0) - -#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER0 /* TIMER0 as tick */ -#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER0_IRQ - -#if (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 1) /* fixed period */ - -#if (CONFIG_SYS_NIOS_CPU_TIMER0_PER >= CONFIG_SYS_HZ) -#define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER0_PER / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ -#endif - -#undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 0) /* variable period */ - -#if (CONFIG_SYS_HZ <= 1000) -#define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 -#endif - -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - -#else -#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER0_FP correct -#endif - -#elif (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 1) - -#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER1 /* TIMER1 as tick */ -#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER1_IRQ - -#if (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 1) /* fixed period */ - -#if (CONFIG_SYS_NIOS_CPU_TIMER1_PER >= CONFIG_SYS_HZ) -#define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER1_PER / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ -#endif - -#undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 0) /* variable period */ - -#if (CONFIG_SYS_HZ <= 1000) -#define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 -#endif - -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - -#else -#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER1_FP correct -#endif - -#endif /* CONFIG_SYS_NIOS_CPU_TICK_TIMER */ - -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one TIMER in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * Ethernet - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_LAN_NUMS == 1) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ - -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC91111_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) -#define CONFIG_SMC_USE_32_BIT 1 -#else /* no */ -#undef CONFIG_SMC_USE_32_BIT -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */ - - /********************************************/ - /* !!! CS8900 is __not__ tested on NIOS !!! */ - /********************************************/ -#define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* Using CS8900 */ -#define CONFIG_CS8900_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + \ - CONFIG_SYS_NIOS_CPU_LAN0_OFFS) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) -#undef CONFIG_CS8900_BUS16 -#define CONFIG_CS8900_BUS32 -#else /* no */ -#define CONFIG_CS8900_BUS16 -#undef CONFIG_CS8900_BUS32 -#endif - -#else -#error *** CONFIG_SYS_ERROR: invalid LAN0 chip type, check your NIOS CPU config -#endif - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - -#else -#error *** CONFIG_SYS_ERROR: you have to setup just one LAN only or expand your config.h -#endif - -/*------------------------------------------------------------------------ - * STATUS LEDs - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) - -#if (CONFIG_SYS_NIOS_CPU_LED_PIO == 0) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO0 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 1) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO1 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 2) - -#define STATUS_LED_BASE CONFIG_SYS_NIOS_CPU_PIO2 -#define STATUS_LED_BITS CONFIG_SYS_NIOS_CPU_PIO2_BITS -#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -#if (CONFIG_SYS_NIOS_CPU_PIO2_TYPE == 1) -#define STATUS_LED_WRONLY 1 -#else -#undef STATUS_LED_WRONLY -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 3) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO3 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 4) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO4 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 5) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO5 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 6) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO6 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 7) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO7 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 8) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO8 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 9) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO9 not supported, expand your config.h - -#else -#error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_LED_PIO in right case -#endif - -#define CONFIG_STATUS_LED 1 /* enable status led driver */ - -#define STATUS_LED_BIT (1 << 0) /* LED[0] */ -#define STATUS_LED_STATE STATUS_LED_BLINKING -#define STATUS_LED_BOOT_STATE STATUS_LED_OFF -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_BOOT 0 /* boot LED */ - -#if (STATUS_LED_BITS > 1) -#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */ -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 50) /* ca. 5 Hz */ -#define STATUS_LED_RED 1 /* fail LED */ -#endif - -#if (STATUS_LED_BITS > 2) -#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */ -#define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_YELLOW 2 /* info LED */ -#endif - -#if (STATUS_LED_BITS > 3) -#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */ -#define STATUS_LED_STATE3 STATUS_LED_OFF -#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_GREEN 3 /* info LED */ -#endif - -#define STATUS_LED_PAR 1 /* makes status_led.h happy */ - -#endif /* CONFIG_SYS_NIOS_CPU_PIO_NUMS */ - -/*------------------------------------------------------------------------ - * SEVEN SEGMENT LED DISPLAY - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) - -#if (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 0) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO0 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 1) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO1 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 2) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO2 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 3) - -#define SEVENSEG_BASE CONFIG_SYS_NIOS_CPU_PIO3 -#define SEVENSEG_BITS CONFIG_SYS_NIOS_CPU_PIO3_BITS -#define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */ - -#if (CONFIG_SYS_NIOS_CPU_PIO3_TYPE == 1) -#define SEVENSEG_WRONLY 1 -#else -#undef SEVENSEG_WRONLY -#endif - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 4) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO4 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 5) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO5 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 6) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO6 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 7) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO7 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 8) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO8 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 9) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO9 not supported, expand your config.h - -#else -#error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO in right case -#endif - -#define CONFIG_SEVENSEG 1 /* enable seven segment led driver */ - -/* - * Dual 7-Segment Display pin assignment -- read more in your - * "Nios Development Board Reference Manual" - * - * - * (U8) HI:D[15..8] (U9) LO:D[7..0] - * ______ ______ - * | D14 | | D6 | - * | | | | - * D9| |D13 D1| |D5 - * |______| |______| ___ - * | D8 | | D0 | | A | - * | | | | F|___|B - * D10| |D12 D2| |D4 | G | - * |______| |______| E|___|C - * D11 * D3 * D * - * D15 D7 DP - * - */ -#define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */ -#define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */ -#define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */ -#define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */ -#define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */ -#define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */ -#define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */ -#define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */ -#define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */ - -#endif /* CONFIG_SYS_NIOS_CPU_PIO_NUMS */ - -/*------------------------------------------------------------------------ - * ASMI - Active Serial Memory Interface. - * - * ASMI is for Cyclone devices only and only works when the configuration - * is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details. - *----------------------------------------------------------------------*/ -#define CONFIG_NIOS_ASMI /* Enable ASMI */ -#define CONFIG_SYS_NIOS_ASMIBASE CONFIG_SYS_NIOS_CPU_ASMI0 /* ASMI base address */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG - -/*------------------------------------------------------------------------ - * COMPACT FLASH - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_IDE) -#define CONFIG_IDE_PREINIT /* Implement id_preinit */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0x00920a00 /* IDE/ATA base addr */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0040 /* Data IO offset */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0040 /* Register offset */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */ -#define CONFIG_SYS_ATA_STRIDE 4 /* Width betwix addrs */ -#define CONFIG_DOS_PARTITION - -/* Board-specific cf regs */ -#define CONFIG_SYS_CF_PRESENT 0x009209b0 /* CF Present PIO base */ -#define CONFIG_SYS_CF_POWER 0x009209c0 /* CF Power FET PIO base*/ -#define CONFIG_SYS_CF_ATASEL 0x009209d0 /* CF ATASEL PIO base */ - -#endif - -/*------------------------------------------------------------------------ - * KGDB - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 9600 -#endif - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "DK1C20 > " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#if (CONFIG_SYS_SRAM_SIZE != 0) -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SRAM_BASE /* Default load address */ -#else -#undef CONFIG_SYS_LOAD_ADDR -#endif - -#if (CONFIG_SYS_SDRAM_SIZE != 0) -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* SDRAM til stack area */ -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - (1024 * 1024)) /* 1MB stack */ -#else -#undef CONFIG_SYS_MEMTEST_START -#undef CONFIG_SYS_MEMTEST_END -#endif - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/DK1C20_safe_32.h b/include/configs/DK1C20_safe_32.h deleted file mode 100644 index 86e4869..0000000 --- a/include/configs/DK1C20_safe_32.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> - * Stephan Linz <linz@li-pro.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_DK1C20_SAFE_32_H -#define __CONFIG_DK1C20_SAFE_32_H - -/* - * NIOS CPU configuration. (PART OF configs/DK1C20.h) - * - * !!! TODO !!! TODO !!! - */ -#error *** CONFIG_SYS_ERROR: DK1C20_safe_32 have to be defined (use DK1C20_standard_32 as template) - -#endif /* __CONFIG_DK1C20_SAFE_32_H */ diff --git a/include/configs/DK1C20_standard_32.h b/include/configs/DK1C20_standard_32.h deleted file mode 100644 index c08aaae..0000000 --- a/include/configs/DK1C20_standard_32.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> - * Stephan Linz <linz@li-pro.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_DK1C20_STANDARD_32_H -#define __CONFIG_DK1C20_STANDARD_32_H - -/* - * NIOS CPU configuration. (PART OF configs/DK1C20.h) - * - * Here we must define CPU dependencies. Any unsupported option have to - * be defined with zero, example CPU without data cache / OCI: - * - * #define CONFIG_SYS_NIOS_CPU_ICACHE 4096 - * #define CONFIG_SYS_NIOS_CPU_DCACHE 0 - * #define CONFIG_SYS_NIOS_CPU_OCI_BASE 0 - * #define CONFIG_SYS_NIOS_CPU_OCI_SIZE 0 - */ - -/* CPU core */ -#define CONFIG_SYS_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ -#define CONFIG_SYS_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ -#define CONFIG_SYS_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ -#define CONFIG_SYS_NIOS_CPU_REG_NUMS 256 /* number of register */ -#define CONFIG_SYS_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CONFIG_SYS_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CONFIG_SYS_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ -#define CONFIG_SYS_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* on-chip extensions */ -#define CONFIG_SYS_NIOS_CPU_RAM_BASE 0 /* on chip RAM addr */ -#define CONFIG_SYS_NIOS_CPU_RAM_SIZE 0 /* size */ - -#define CONFIG_SYS_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ -#define CONFIG_SYS_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#define CONFIG_SYS_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ -#define CONFIG_SYS_NIOS_CPU_OCI_SIZE 256 /* size */ - -/* timer */ -#define CONFIG_SYS_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ - -#define CONFIG_SYS_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -#define CONFIG_SYS_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CONFIG_SYS_NIOS_CPU_UART_NUMS 1 /* number of uarts */ - -#define CONFIG_SYS_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ -#define CONFIG_SYS_NIOS_CPU_UART0_IRQ 25 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CONFIG_SYS_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_SB 1 /* stop bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CONFIG_SYS_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CONFIG_SYS_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* parallel i/o */ -#define CONFIG_SYS_NIOS_CPU_PIO_NUMS 8 /* number of parports */ - -#define CONFIG_SYS_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO0_BITS 4 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO1_BITS 11 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO2_BITS 8 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO3_BITS 16 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO4_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO5_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO6_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO7_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CONFIG_SYS_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ -#define CONFIG_SYS_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ - -/* active serial memory i/f */ -#define CONFIG_SYS_NIOS_CPU_ASMI_NUMS 1 /* number of ASMI */ -#define CONFIG_SYS_NIOS_CPU_ASMI0 0x00920b00 /* ASMI0 addr */ -#define CONFIG_SYS_NIOS_CPU_ASMI0_IRQ 45 /* IRQ */ - -/* memory accessibility */ -#define CONFIG_SYS_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ -#define CONFIG_SYS_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ - -#define CONFIG_SYS_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ -#define CONFIG_SYS_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CONFIG_SYS_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ -#define CONFIG_SYS_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CONFIG_SYS_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CONFIG_SYS_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ -#define CONFIG_SYS_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ -#define CONFIG_SYS_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ -#define CONFIG_SYS_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: alteramac(2) */ - -/* symbolic redefinition (undef, if not present) */ -#define CONFIG_SYS_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ -#define CONFIG_SYS_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ - -#define CONFIG_SYS_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ -#define CONFIG_SYS_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ -#define CONFIG_SYS_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ -#define CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ -#define CONFIG_SYS_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ -#define CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ -#define CONFIG_SYS_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ -#define CONFIG_SYS_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ - -#endif /* __CONFIG_DK1C20_STANDARD_32_H */ diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h deleted file mode 100644 index 6e78861..0000000 --- a/include/configs/DK1S10.h +++ /dev/null @@ -1,561 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> - * Stephan Linz <linz@li-pro.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*********************************************************************** - * Include the whole NIOS CPU configuration. - * - * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! - * - ***********************************************************************/ - -#if defined(CONFIG_NIOS_SAFE_32) -#include <configs/DK1S10_safe_32.h> -#elif defined(CONFIG_NIOS_STANDARD_32) -#include <configs/DK1S10_standard_32.h> -#elif defined(CONFIG_NIOS_MTX_LDK_20) -#include <configs/DK1S10_mtx_ldk_20.h> -#else -#error *** CONFIG_SYS_ERROR: you have to setup right NIOS CPU configuration -#endif - -/*------------------------------------------------------------------------ - * BOARD/CPU -- TOP-LEVEL - *----------------------------------------------------------------------*/ -#define CONFIG_NIOS 1 /* NIOS-32 core */ -#define CONFIG_DK1S10 1 /* Stratix DK-1S10 board*/ -#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock */ -#define CONFIG_SYS_HZ 1000 /* 1 msec time tick */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM) - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_SDRAM_SIZE != 0) - -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_NIOS_CPU_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_NIOS_CPU_SDRAM_SIZE - -#else -#error *** CONFIG_SYS_ERROR: you have to setup any SDRAM in NIOS CPU config -#endif - -#if defined(CONFIG_SYS_NIOS_CPU_SRAM_BASE) && defined(CONFIG_SYS_NIOS_CPU_SRAM_SIZE) - -#define CONFIG_SYS_SRAM_BASE CONFIG_SYS_NIOS_CPU_SRAM_BASE -#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_NIOS_CPU_SRAM_SIZE - -#else - -#undef CONFIG_SYS_SRAM_BASE -#undef CONFIG_SYS_SRAM_SIZE - -#endif - -#define CONFIG_SYS_VECT_BASE CONFIG_SYS_NIOS_CPU_VEC_BASE - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - For the most part, you can put things pretty - * much anywhere. This is pretty flexible for Nios. So here we make some - * arbitrary choices & assume that the monitor is placed at the end of - * a memory resource (so you must make sure TEXT_BASE is chosen - * appropriately). - * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_NIOS_CPU_FLASH_BASE -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_NIOS_CPU_FLASH_SIZE -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ - -#else -#error *** CONFIG_SYS_ERROR: you have to setup any Flash memory in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * ENVIRONMENT - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_FLASH_SIZE != 0) - -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ - -#if defined(CONFIG_NIOS_STANDARD_32) -#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Mem addr of env */ -#elif defined(CONFIG_NIOS_MTX_LDK_20) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -#else -#error *** CONFIG_SYS_ERROR: you have to setup the environment base address CONFIG_ENV_ADDR -#endif - -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ - -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* NO Environment */ -#endif - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_UART_NUMS != 0) - -#define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_NIOS_CPU_UART0 /* 1st UART is Cons. */ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#if (CONFIG_SYS_NIOS_CPU_UART0_BR != 0) -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE CONFIG_SYS_NIOS_CPU_UART0_BR -#else -#undef CONFIG_SYS_NIOS_FIXEDBAUD -#define CONFIG_BAUDRATE 115200 -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one UART in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, - * so an avalon bus timer is required. - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_TIMER_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_TICK_TIMER) - -#if (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 0) - -#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER0 /* TIMER0 as tick */ -#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER0_IRQ - -#if (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 1) /* fixed period */ - -#if (CONFIG_SYS_NIOS_CPU_TIMER0_PER >= CONFIG_SYS_HZ) -#define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER0_PER / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ -#endif - -#undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CONFIG_SYS_NIOS_CPU_TIMER0_FP == 0) /* variable period */ - -#if (CONFIG_SYS_HZ <= 1000) -#define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 -#endif - -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - -#else -#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER0_FP correct -#endif - -#elif (CONFIG_SYS_NIOS_CPU_TICK_TIMER == 1) - -#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_NIOS_CPU_TIMER1 /* TIMER1 as tick */ -#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_NIOS_CPU_TIMER1_IRQ - -#if (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 1) /* fixed period */ - -#if (CONFIG_SYS_NIOS_CPU_TIMER1_PER >= CONFIG_SYS_HZ) -#define CONFIG_SYS_NIOS_TMRMS (CONFIG_SYS_NIOS_CPU_TIMER1_PER / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: you have to use a timer periode greater than CONFIG_SYS_HZ -#endif - -#undef CONFIG_SYS_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CONFIG_SYS_NIOS_CPU_TIMER1_FP == 0) /* variable period */ - -#if (CONFIG_SYS_HZ <= 1000) -#define CONFIG_SYS_NIOS_TMRMS (1000 / CONFIG_SYS_HZ) -#else -#error *** CONFIG_SYS_ERROR: sorry, CONFIG_SYS_HZ have to be less than 1000 -#endif - -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - -#else -#error *** CONFIG_SYS_ERROR: you have to define CONFIG_SYS_NIOS_CPU_TIMER1_FP correct -#endif - -#endif /* CONFIG_SYS_NIOS_CPU_TICK_TIMER */ - -#else -#error *** CONFIG_SYS_ERROR: you have to setup at least one TIMER in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * Ethernet -- needs work! - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_LAN_NUMS == 1) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ - -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC91111_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + CONFIG_SYS_NIOS_CPU_LAN0_OFFS) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) -#define CONFIG_SMC_USE_32_BIT 1 -#else /* no */ -#undef CONFIG_SMC_USE_32_BIT -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */ - - /********************************************/ - /* !!! CS8900 is __not__ tested on NIOS !!! */ - /********************************************/ -#define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* Using CS8900 */ -#define CONFIG_CS8900_BASE (CONFIG_SYS_NIOS_CPU_LAN0_BASE + \ - CONFIG_SYS_NIOS_CPU_LAN0_OFFS) - -#if (CONFIG_SYS_NIOS_CPU_LAN0_BUSW == 32) -#undef CONFIG_CS8900_BUS16 -#define CONFIG_CS8900_BUS32 -#else /* no */ -#define CONFIG_CS8900_BUS16 -#undef CONFIG_CS8900_BUS32 -#endif - -#else -#error *** CONFIG_SYS_ERROR: invalid LAN0 chip type, check your NIOS CPU config -#endif - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - -#else -#error *** CONFIG_SYS_ERROR: you have to setup just one LAN only or expand your config.h -#endif - -/*------------------------------------------------------------------------ - * STATUS LEDs - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_LED_PIO) - -#if (CONFIG_SYS_NIOS_CPU_LED_PIO == 0) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO0 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 1) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO1 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 2) - -#define STATUS_LED_BASE CONFIG_SYS_NIOS_CPU_PIO2 -#define STATUS_LED_BITS CONFIG_SYS_NIOS_CPU_PIO2_BITS -#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -#if (CONFIG_SYS_NIOS_CPU_PIO2_TYPE == 1) -#define STATUS_LED_WRONLY 1 -#else -#undef STATUS_LED_WRONLY -#endif - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 3) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO3 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 4) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO4 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 5) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO5 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 6) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO6 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 7) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO7 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 8) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO8 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_LED_PIO == 9) - -#error *** CONFIG_SYS_ERROR: status LEDs at PIO9 not supported, expand your config.h - -#else -#error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_LED_PIO in right case -#endif - -#define CONFIG_STATUS_LED 1 /* enable status led driver */ - -#define STATUS_LED_BIT (1 << 0) /* LED[0] */ -#define STATUS_LED_STATE STATUS_LED_BLINKING -#define STATUS_LED_BOOT_STATE STATUS_LED_OFF -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_BOOT 0 /* boot LED */ - -#if (STATUS_LED_BITS > 1) -#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */ -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 50) /* ca. 5 Hz */ -#define STATUS_LED_RED 1 /* fail LED */ -#endif - -#if (STATUS_LED_BITS > 2) -#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */ -#define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_YELLOW 2 /* info LED */ -#endif - -#if (STATUS_LED_BITS > 3) -#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */ -#define STATUS_LED_STATE3 STATUS_LED_OFF -#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_GREEN 3 /* info LED */ -#endif - -#define STATUS_LED_PAR 1 /* makes status_led.h happy */ - -#endif /* CONFIG_SYS_NIOS_CPU_PIO_NUMS */ - -/*------------------------------------------------------------------------ - * SEVEN SEGMENT LED DISPLAY - *----------------------------------------------------------------------*/ -#if (CONFIG_SYS_NIOS_CPU_PIO_NUMS != 0) && defined(CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO) - -#if (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 0) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO0 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 1) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO1 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 2) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO2 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 3) - -#define SEVENSEG_BASE CONFIG_SYS_NIOS_CPU_PIO3 -#define SEVENSEG_BITS CONFIG_SYS_NIOS_CPU_PIO3_BITS -#define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */ - -#if (CONFIG_SYS_NIOS_CPU_PIO3_TYPE == 1) -#define SEVENSEG_WRONLY 1 -#else -#undef SEVENSEG_WRONLY -#endif - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 4) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO4 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 5) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO5 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 6) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO6 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 7) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO7 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 8) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO8 not supported, expand your config.h - -#elif (CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO == 9) - -#error *** CONFIG_SYS_ERROR: seven segment display at PIO9 not supported, expand your config.h - -#else -#error *** CONFIG_SYS_ERROR: you have to set CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO in right case -#endif - -#define CONFIG_SEVENSEG 1 /* enable seven segment led driver */ - -/* - * Dual 7-Segment Display pin assignment -- read more in your - * "Nios Development Board Reference Manual" - * - * - * (U8) HI:D[15..8] (U9) LO:D[7..0] - * ______ ______ - * | D14 | | D6 | - * | | | | - * D9| |D13 D1| |D5 - * |______| |______| ___ - * | D8 | | D0 | | A | - * | | | | F|___|B - * D10| |D12 D2| |D4 | G | - * |______| |______| E|___|C - * D11 * D3 * D * - * D15 D7 DP - * - */ -#define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */ -#define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */ -#define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */ -#define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */ -#define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */ -#define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */ -#define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */ -#define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */ -#define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */ - -#endif /* CONFIG_SYS_NIOS_CPU_PIO_NUMS */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_REISER -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG - -/*------------------------------------------------------------------------ - * KGDB - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 9600 -#endif - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "DK1S10 > " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* Default load address */ -#if (CONFIG_SYS_SRAM_SIZE != 0) - -/* default in SRAM */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SRAM_BASE - -#elif (CONFIG_SYS_SDRAM_SIZE != 0) - -/* default in SDRAM */ -#if (CONFIG_SYS_SDRAM_BASE == CONFIG_SYS_NIOS_CPU_VEC_BASE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_NIOS_CPU_VEC_SIZE) -#else -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE -#endif - -#else -#undef CONFIG_SYS_LOAD_ADDR /* force error break */ -#endif - - -/* MEM test area */ -#if (CONFIG_SYS_SDRAM_SIZE != 0) - -/* SDRAM begin to stack area (1MB stack) */ -#if (CONFIG_SYS_SDRAM_BASE == CONFIG_SYS_NIOS_CPU_VEC_BASE) -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_NIOS_CPU_VEC_SIZE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - (1024 * 1024)) -#else -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - (1024 * 1024)) -#endif - -#else -#undef CONFIG_SYS_MEMTEST_START /* force error break */ -#undef CONFIG_SYS_MEMTEST_END -#endif - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/DK1S10_mtx_ldk_20.h b/include/configs/DK1S10_mtx_ldk_20.h deleted file mode 100644 index 87a8a54..0000000 --- a/include/configs/DK1S10_mtx_ldk_20.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> - * Stephan Linz <linz@li-pro.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_DK1S10_MTX_LDK_20_H -#define __CONFIG_DK1S10_MTX_LDK_20_H - -/* - * NIOS CPU configuration. (PART OF configs/DK1S10.h) - * - * Here we must define CPU dependencies. Any unsupported option have to - * be defined with zero, example CPU without data cache / OCI: - * - * #define CONFIG_SYS_NIOS_CPU_ICACHE 4096 - * #define CONFIG_SYS_NIOS_CPU_DCACHE 0 - * #define CONFIG_SYS_NIOS_CPU_OCI_BASE 0 - * #define CONFIG_SYS_NIOS_CPU_OCI_SIZE 0 - */ - -/* CPU core */ -#define CONFIG_SYS_NIOS_CPU_CLK 75000000 /* NIOS CPU clock */ -#define CONFIG_SYS_NIOS_CPU_ICACHE (0) /* instruction cache */ -#define CONFIG_SYS_NIOS_CPU_DCACHE (0) /* data cache */ -#define CONFIG_SYS_NIOS_CPU_REG_NUMS 512 /* number of register */ -#define CONFIG_SYS_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_STACK 0x02000000 /* stack top addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_BASE 0x01000000 /* IRQ vectors addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CONFIG_SYS_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CONFIG_SYS_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */ -#define CONFIG_SYS_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* The offset address in flash to check for the Nios signature "Ni". - * (see GM_FlashExec in germs_monitor.s) */ -#define CONFIG_SYS_NIOS_CPU_EXES_OFFS 0x0C - -/* on-chip extensions */ -#undef CONFIG_SYS_NIOS_CPU_RAM_BASE /* on chip RAM addr */ -#undef CONFIG_SYS_NIOS_CPU_RAM_SIZE /* 64 KB size */ - -#define CONFIG_SYS_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */ -#define CONFIG_SYS_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#undef CONFIG_SYS_NIOS_CPU_OCI_BASE /* OCI core addr */ -#undef CONFIG_SYS_NIOS_CPU_OCI_SIZE /* size */ - -/* timer */ -#define CONFIG_SYS_NIOS_CPU_TIMER_NUMS 1 /* number of timer */ - -#define CONFIG_SYS_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CONFIG_SYS_NIOS_CPU_UART_NUMS 2 /* number of uarts */ - -#define CONFIG_SYS_NIOS_CPU_UART0 0x00000800 /* UART0 addr */ -#define CONFIG_SYS_NIOS_CPU_UART0_IRQ 17 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CONFIG_SYS_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_SB 2 /* stop bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CONFIG_SYS_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CONFIG_SYS_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -#define CONFIG_SYS_NIOS_CPU_UART1 0x000008a0 /* UART1 addr */ -#define CONFIG_SYS_NIOS_CPU_UART1_IRQ 18 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */ -#define CONFIG_SYS_NIOS_CPU_UART1_DB 8 /* data bit */ -#define CONFIG_SYS_NIOS_CPU_UART1_SB 1 /* stop bit */ -#define CONFIG_SYS_NIOS_CPU_UART1_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CONFIG_SYS_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CONFIG_SYS_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* parallel i/o */ -#define CONFIG_SYS_NIOS_CPU_PIO_NUMS 2 /* number of parports */ - -#define CONFIG_SYS_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO0_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO0_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO0_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO1_BITS 4 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO1_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CONFIG_SYS_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ -#define CONFIG_SYS_NIOS_CPU_IDE0 0x00000900 /* IDE0 addr */ -#define CONFIG_SYS_NIOS_CPU_IDE0_IRQ 25 /* IRQ */ - -/* memory accessibility */ -#undef CONFIG_SYS_NIOS_CPU_SRAM_BASE /* board SRAM addr */ -#undef CONFIG_SYS_NIOS_CPU_SRAM_SIZE /* 1 MB size */ - -#define CONFIG_SYS_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ -#define CONFIG_SYS_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CONFIG_SYS_NIOS_CPU_FLASH_BASE 0x00800000 /* board Flash addr */ -#define CONFIG_SYS_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CONFIG_SYS_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CONFIG_SYS_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */ -#define CONFIG_SYS_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ -#define CONFIG_SYS_NIOS_CPU_LAN0_IRQ 20 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ -#define CONFIG_SYS_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: openmac(2) */ - /* ex: alteramac(3) */ - -/* symbolic redefinition (undef, if not present) */ -#define CONFIG_SYS_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/ -#undef CONFIG_SYS_NIOS_CPU_USER_TIMER /* TIMERx: users choice */ - -#define CONFIG_SYS_NIOS_CPU_CFPOWER_PIO 0 /* PIO0: CF power/sw. */ -#define CONFIG_SYS_NIOS_CPU_BUTTON_PIO 1 /* PIO1: buttons */ -#undef CONFIG_SYS_NIOS_CPU_LCD_PIO /* PIOx: ASCII LCD */ -#undef CONFIG_SYS_NIOS_CPU_LED_PIO /* PIOx: LED bar */ -#undef CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO /* PIOx: 7-seg. display */ -#undef CONFIG_SYS_NIOS_CPU_RECONF_PIO /* PIOx: reconf pin */ -#undef CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO /* PIOx: CF present IRQ */ -#undef CONFIG_SYS_NIOS_CPU_CFATASEL_PIO /* PIOx: CF ATA select */ - -#endif /* __CONFIG_DK1S10_MTX_LDK_20_H */ diff --git a/include/configs/DK1S10_safe_32.h b/include/configs/DK1S10_safe_32.h deleted file mode 100644 index ced4ef2..0000000 --- a/include/configs/DK1S10_safe_32.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> - * Stephan Linz <linz@li-pro.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_DK1S10_SAFE_32_H -#define __CONFIG_DK1S10_SAFE_32_H - -/* - * NIOS CPU configuration. (PART OF configs/DK1S10.h) - * - * !!! TODO !!! TODO !!! - */ -#error *** CONFIG_SYS_ERROR: DK1S10_safe_32 have to be defined (use DK1S10_standard_32 as template) - -#endif /* __CONFIG_DK1S10_SAFE_32_H */ diff --git a/include/configs/DK1S10_standard_32.h b/include/configs/DK1S10_standard_32.h deleted file mode 100644 index e6ccaf5..0000000 --- a/include/configs/DK1S10_standard_32.h +++ /dev/null @@ -1,274 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> - * Stephan Linz <linz@li-pro.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_DK1S10_STANDARD_32_H -#define __CONFIG_DK1S10_STANDARD_32_H - -/* - * NIOS CPU configuration. (PART OF configs/DK1S10.h) - * - * Here we must define CPU dependencies. Any unsupported option have to - * be defined with zero, example CPU without data cache / OCI: - * - * #define CONFIG_SYS_NIOS_CPU_ICACHE 4096 - * #define CONFIG_SYS_NIOS_CPU_DCACHE 0 - * #define CONFIG_SYS_NIOS_CPU_OCI_BASE 0 - * #define CONFIG_SYS_NIOS_CPU_OCI_SIZE 0 - */ - -/* CPU core */ -#define CONFIG_SYS_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ -#define CONFIG_SYS_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ -#define CONFIG_SYS_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ -#define CONFIG_SYS_NIOS_CPU_REG_NUMS 256 /* number of register */ -#define CONFIG_SYS_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ -#define CONFIG_SYS_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CONFIG_SYS_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CONFIG_SYS_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ -#define CONFIG_SYS_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* on-chip extensions */ -#define CONFIG_SYS_NIOS_CPU_RAM_BASE 0x00900000 /* on chip RAM addr */ -#define CONFIG_SYS_NIOS_CPU_RAM_SIZE (64 * 1024) /* 64 KB size */ - -#define CONFIG_SYS_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ -#define CONFIG_SYS_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#define CONFIG_SYS_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ -#define CONFIG_SYS_NIOS_CPU_OCI_SIZE 256 /* size */ - -/* timer */ -#define CONFIG_SYS_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ - -#define CONFIG_SYS_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -#define CONFIG_SYS_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CONFIG_SYS_NIOS_CPU_UART_NUMS 1 /* number of uarts */ - -#define CONFIG_SYS_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ -#define CONFIG_SYS_NIOS_CPU_UART0_IRQ 25 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CONFIG_SYS_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_SB 1 /* stop bit */ -#define CONFIG_SYS_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CONFIG_SYS_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CONFIG_SYS_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* parallel i/o */ -#define CONFIG_SYS_NIOS_CPU_PIO_NUMS 8 /* number of parports */ - -#define CONFIG_SYS_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO0_BITS 4 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO1_BITS 11 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO2_BITS 8 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO3_BITS 16 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO4_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ -#define CONFIG_SYS_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO5_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO6_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CONFIG_SYS_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ -#undef CONFIG_SYS_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ -#define CONFIG_SYS_NIOS_CPU_PIO7_BITS 1 /* number of bits */ -#define CONFIG_SYS_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CONFIG_SYS_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CONFIG_SYS_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ -#define CONFIG_SYS_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ - -/* memory accessibility */ -#define CONFIG_SYS_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ -#define CONFIG_SYS_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ - -#define CONFIG_SYS_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ -#define CONFIG_SYS_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CONFIG_SYS_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ -#define CONFIG_SYS_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CONFIG_SYS_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CONFIG_SYS_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ -#define CONFIG_SYS_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ -#define CONFIG_SYS_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ -#define CONFIG_SYS_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ -#define CONFIG_SYS_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: alteramac(2) */ - -/* symbolic redefinition (undef, if not present) */ -#define CONFIG_SYS_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ -#define CONFIG_SYS_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ - -#define CONFIG_SYS_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ -#define CONFIG_SYS_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ -#define CONFIG_SYS_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ -#define CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ -#define CONFIG_SYS_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ -#define CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ -#define CONFIG_SYS_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ -#define CONFIG_SYS_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ - -#endif /* __CONFIG_DK1S10_STANDARD_32_H */ diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h index d2aa8b9..84d27b6 100644 --- a/include/configs/ELPPC.h +++ b/include/configs/ELPPC.h @@ -314,9 +314,8 @@ /* * Speed settings are board specific */ -#define CONFIG_SYS_BUS_HZ 100000000 -#define CONFIG_SYS_CPU_CLK 400000000 -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 100000000 +#define CONFIG_SYS_CPU_CLK 400000000 /* * For booting Linux, the board info and command line data diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h index bf41c13..0903536 100644 --- a/include/configs/EVB64260.h +++ b/include/configs/EVB64260.h @@ -141,8 +141,7 @@ #define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ -#define CONFIG_SYS_BUS_HZ 100000000 /* 100 MHz */ -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 100000000 /* 100 MHz */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 94695fc..9a40adc 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -513,7 +513,7 @@ /* System IO Config */ #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ -#define CONFIG_SYS_SICRL SICRL_USBDR /* Enable Internal USB Phy */ +#define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */ #define CONFIG_SYS_HID0_INIT 0x000000000 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index a9b4004..b891730 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -425,6 +425,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ETHPRIME "eTSEC1" #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +/* TBI PHY configuration for SGMII mode */ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + #endif /* CONFIG_TSEC_ENET */ /* @@ -568,7 +577,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "loadaddr=1000000\0" \ - "bootfile=uImage\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ "erase " MK_STR(TEXT_BASE) " +$filesize; " \ diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h index 971338a..890170d 100644 --- a/include/configs/P3G4.h +++ b/include/configs/P3G4.h @@ -168,8 +168,7 @@ #define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ -#define CONFIG_SYS_BUS_HZ 133000000 /* 133 MHz */ -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h index 99a8c4a..c30ac78 100644 --- a/include/configs/PCIPPC2.h +++ b/include/configs/PCIPPC2.h @@ -194,9 +194,8 @@ * For the detail description refer to the PCIPPC2 user's manual. */ #define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_BUS_HZ 100000000 /* bus speed - 100 mhz */ +#define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */ #define CONFIG_SYS_CPU_CLK 300000000 -#define CONFIG_SYS_BUS_CLK 100000000 /* * For booting Linux, the board info and command line data diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h index 66e6d24..bc67480 100644 --- a/include/configs/PCIPPC6.h +++ b/include/configs/PCIPPC6.h @@ -196,9 +196,8 @@ * For the detail description refer to the PCIPPC2 user's manual. */ #define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_BUS_HZ 100000000 /* bus speed - 100 mhz */ +#define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */ #define CONFIG_SYS_CPU_CLK 300000000 -#define CONFIG_SYS_BUS_CLK 100000000 /* * For booting Linux, the board info and command line data diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 9104f1a..eb8657b 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -419,7 +419,7 @@ | SICRH_TSOBI1 \ | SICRH_TSOBI2 ) #define CONFIG_SYS_SICRL ( SICRL_LBC \ - | SICRL_USBDR \ + | SICRL_USBDR_10 \ | SICRL_ETSEC2_A ) #define CONFIG_SYS_HID0_INIT 0x000000000 diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h index b73aaa8..fcc47a9 100644 --- a/include/configs/ZUMA.h +++ b/include/configs/ZUMA.h @@ -164,9 +164,7 @@ #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ -#define CONFIG_SYS_BUS_HZ 133000000 /* 133 MHz */ - -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index 0f58e11..160ece2 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -87,6 +87,7 @@ * Network & Ethernet Configuration */ #ifdef CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h new file mode 100644 index 0000000..357715d --- /dev/null +++ b/include/configs/da850evm.h @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on davinci_dvevm.h. Original Copyrights follow: + * + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Board + */ + +/* + * SoC Configuration + */ +#define CONFIG_MACH_DAVINCI_DA850_EVM +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) +#define CONFIG_SYS_OSCIN_FREQ 24000000 +#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ + +/* + * Memory Info + */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ +#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ + +/* memtest start addr */ +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) + +/* memtest will be run on 16MB */ +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) + +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ + +/* + * Serial Driver info + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ +#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ +#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * I2C Configuration + */ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CONFIG_SYS_I2C_SPEED 25000 +#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ + +/* + * U-Boot general configuration + */ +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "DA850-evm > " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC + +/* + * Linux Information + */ +#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100) +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS \ + "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" +#define CONFIG_BOOTDELAY 3 + +/* + * U-Boot commands + */ +#include <config_cmd_default.h> +#define CONFIG_CMD_ENV +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MEMORY + +#ifndef CONFIG_DRIVER_TI_EMAC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_PING +#endif + +#if !defined(CONFIG_USE_NAND) && \ + !defined(CONFIG_USE_NOR) && \ + !defined(CONFIG_USE_SPIFLASH) +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_SIZE (16 << 10) +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_ENV +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index 6f99ae0..2c3d88d 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -58,6 +58,7 @@ /* Network Configuration */ #define CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 0 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 5774df5..aab2afa 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -102,6 +102,7 @@ /* Network & Ethernet Configuration */ /*==================================*/ #define CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 3972ebc..875dda4 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -69,6 +69,7 @@ /* Network & Ethernet Configuration */ /*==================================*/ #define CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 94be9dc..f4e17f8 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -66,6 +66,7 @@ #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /* Network & Ethernet Configuration */ #define CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 490821a..4c01844 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -102,6 +102,7 @@ /* Network & Ethernet Configuration */ /*==================================*/ #define CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h new file mode 100644 index 0000000..c3d95a0 --- /dev/null +++ b/include/configs/edminiv2.h @@ -0,0 +1,172 @@ +/* + * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr> + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_EDMINIV2_H +#define _CONFIG_EDMINIV2_H + +/* + * Version number information + */ + +#define CONFIG_IDENT_STRING " EDMiniV2" + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#define CONFIG_FEROCEON 1 /* CPU Core subversion */ +#define CONFIG_ORION5X 1 /* SOC Family Name */ +#define CONFIG_88F5182 1 /* SOC Name */ +#define CONFIG_MACH_EDMINIV2 1 /* Machine type */ + +/* + * CLKs configurations + */ + +#define CONFIG_SYS_HZ 1000 + +/* + * Board-specific values for Orion5x MPP low level init: + * - MPPs 12 to 15 are SATA LEDs (mode 5) + * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for + * MPP16 to MPP19, mode 0 for others + */ + +#define ORION5X_MPP0_7 0x00000003 +#define ORION5X_MPP8_15 0x55550000 +#define ORION5X_MPP16_23 0x00000000 + +/* + * Board-specific values for Orion5x GPIO low level init: + * - GPIO3 is input (RTC interrupt) + * - GPIO16 is Power LED control (0 = on, 1 = off) + * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) + * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) + * - Last GPIO is 26, further bits are supposed to be 0. + * Enable mask has ones for INPUT, 0 for OUTPUT. + * Default is LED ON. + */ + +#define ORION5X_GPIO_OUT_ENABLE 0x03fcffff +#define ORION5X_GPIO_OUT_VALUE 0x03fcffff + +/* + * NS16550 Configuration + */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } + +/* + * FLASH configuration + */ + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BASE 0xfff80000 +#define CONFIG_SYS_FLASH_SECTSZ \ + {16384, 8192, 8192, 32768, \ + 65536, 65536, 65536, 65536, 65536, 65536, 65536} + +/* auto boot */ +#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define CONFIG_SYS_PROMPT "EDMiniV2> " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ +/* + * Commands configuration - using default command set for now + */ +#include <config_cmd_default.h> +/* + * Disabling some default commands for staggered bring-up + */ +#undef CONFIG_CMD_BOOTD /* no bootd since no net */ +#undef CONFIG_CMD_NET /* no net since no eth */ +#undef CONFIG_CMD_NFS /* no NFS since no net */ + +/* + * Environment variables configurations + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Other required minimal configurations + */ +#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_STACKSIZE 0x00100000 +#define CONFIG_SYS_LOAD_ADDR 0x00800000 +#define CONFIG_SYS_MEMTEST_START 0x00400000 +#define CONFIG_SYS_MEMTEST_END 0x007fffff +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 +#define CONFIG_SYS_MAXARGS 16 + +#endif /* _CONFIG_EDMINIV2_H */ diff --git a/include/configs/icon.h b/include/configs/icon.h index 3a57d69..7a4e60c 100644 --- a/include/configs/icon.h +++ b/include/configs/icon.h @@ -143,6 +143,26 @@ #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ /* + * Video options + */ +#define CONFIG_VIDEO + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_SM501 +#define CONFIG_VIDEO_SM501_32BPP +#define CONFIG_VIDEO_SM501_PCI +#define VIDEO_FB_LITTLE_ENDIAN +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CFG_CONSOLE_IS_IN_ENV +#endif + +/* * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ @@ -171,6 +191,9 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP +#ifdef CONFIG_VIDEO +#define CONFIG_CMD_BMP +#endif #define CONFIG_IBM_EMAC4_V4 /* 440SPe has this EMAC version */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index be12186..497ea42 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -46,7 +46,7 @@ #define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" #define CONFIG_SYS_OCN_CLK 133000000 /* 133 MHz */ -#define CONFIG_SYS_CONFIG_BUS_CLK 133000000 +#define CONFIG_SYS_BUS_CLK 133000000 #define CONFIG_SYS_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */ diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h index e83e1e3..e4bf57b 100644 --- a/include/configs/nios2-generic.h +++ b/include/configs/nios2-generic.h @@ -63,10 +63,10 @@ * STATUS LED */ #define CONFIG_STATUS_LED /* Enable status driver */ -#define CONFIG_EPLED /* Enable LED PIO driver */ -#define CONFIG_SYS_LEDPIO_ADDR LED_PIO_BASE +#define CONFIG_GPIO_LED /* Enable GPIO LED driver */ +#define CONFIG_GPIO /* Enable GPIO driver */ -#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ +#define STATUS_LED_BIT 0 /* Bit-0 on GPIO */ #define STATUS_LED_STATE 1 /* Blinking */ #define STATUS_LED_PERIOD (500 / CONFIG_SYS_NIOS_TMRMS) /* 500 msec */ diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h index 0749037..17ec08f 100644 --- a/include/configs/p3mx.h +++ b/include/configs/p3mx.h @@ -44,14 +44,12 @@ #define CONFIG_750FX /* 750GL/GX/FX */ #define CONFIG_HIGH_BATS /* High BATs supported */ #define CONFIG_SYS_BOARD_NAME "P3M750" -#define CONFIG_SYS_BUS_HZ 100000000 -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 100000000 #define CONFIG_SYS_TCLK 100000000 #elif defined (CONFIG_P3M7448) #define CONFIG_74xx #define CONFIG_SYS_BOARD_NAME "P3M7448" -#define CONFIG_SYS_BUS_HZ 133333333 -#define CONFIG_SYS_BUS_CLK CONFIG_SYS_BUS_HZ +#define CONFIG_SYS_BUS_CLK 133333333 #define CONFIG_SYS_TCLK 133333333 #endif #define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */ diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h index 0fd8635..04779c4 100644 --- a/include/configs/ppmc7xx.h +++ b/include/configs/ppmc7xx.h @@ -355,12 +355,10 @@ /* * Clocks config * - * CONFIG_SYS_BUS_HZ - Bus clock frequency in Hz - * CONFIG_SYS_BUS_CLK - As above (?) + * CONFIG_SYS_BUS_CLK - Bus clock frequency in Hz * CONFIG_SYS_HZ - Decrementer freq in Hz */ -#define CONFIG_SYS_BUS_HZ CONFIG_BUS_CLK #define CONFIG_SYS_BUS_CLK CONFIG_BUS_CLK #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/shannon.h b/include/configs/shannon.h index 13cc5ff..d848915 100644 --- a/include/configs/shannon.h +++ b/include/configs/shannon.h @@ -161,12 +161,13 @@ #define CONFIG_ENV_IS_IN_FLASH 1 #ifdef CONFIG_INFERNO -/* we take the last sector, 128 KB in size, but we only use 4 KB of it for stack reasons */ +/* we take the last sector, 128 KB in size, but we only use 16 KB of it for stack reasons */ #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x003E0000) /* Addr of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */ +#define CONFIG_ENV_SECT_SIZE (128 << 10) /* size of environment sector */ #else #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */ #endif /*----------------------------------------------------------------------- diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h new file mode 100644 index 0000000..0ecc5b1 --- /dev/null +++ b/include/configs/t3corp.h @@ -0,0 +1,544 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * t3corp.h - configuration for T3CORP (460GT) + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_460GT 1 /* Specific PPC460GT */ +#define CONFIG_440 1 +#define CONFIG_4xx 1 /* ... PPC4xx family */ + +#define CONFIG_HOSTNAME t3corp + +/* + * Include common defines/options for all AMCC/APM eval boards + */ +#include "amcc-common.h" + +#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_TYPES 1 /* support board types */ +#define CONFIG_FIT +#define CFG_ALT_MEMTEST + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ +#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE + +#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe mem */ +#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe */ +#define CONFIG_SYS_PCIE_BASE 0xc4000000 /* PCIe UTL regs */ + +#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000 +#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000 +#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 +#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000 + +#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit phys addr */ + +/* base address of inbound PCIe window */ +#define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit phys addr */ + +/* EBC stuff */ +#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */ +#define CONFIG_SYS_FLASH_SIZE (64 << 20) + +#define CONFIG_SYS_FPGA1_BASE 0xe0000000 +#define CONFIG_SYS_FPGA2_BASE 0xe0100000 +#define CONFIG_SYS_FPGA3_BASE 0xe0200000 + +#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ +#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 +#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000 +#define CONFIG_SYS_FLASH_BASE_PHYS \ + (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \ + | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) + +#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ +#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 + +#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */ + +#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */ + +/* + * Initial RAM & stack pointer (placed in OCM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Serial Port + */ +#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ + +/* + * Environment + */ +/* + * Define here the location of the environment variables (flash). + */ +#define CONFIG_ENV_IS_IN_FLASH /* use flash for environment vars */ + +/* + * Flash related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */ + +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors p. chip*/ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms*/ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms*/ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buff'd writes (20x faster)*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ + +#define CONFIG_ENV_SECT_SIZE 0x20000 /* sector size */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* env sector size */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +/* + * DDR2 SDRAM + */ +#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ +#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ +#undef CONFIG_PPC4xx_DDR_METHOD_A + +/* DDR1/2 SDRAM Device Control Register Data Values */ +/* Memory Queue */ +#define CONFIG_SYS_SDRAM_R0BAS (SDRAM_RXBAS_SDBA_ENCODE(0) | \ + SDRAM_RXBAS_SDSZ_256) +#define CONFIG_SYS_SDRAM_R1BAS 0x00000000 +#define CONFIG_SYS_SDRAM_R2BAS 0x00000000 +#define CONFIG_SYS_SDRAM_R3BAS 0x00000000 +#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000 +#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008 +#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00 +#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80 +#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000 + +#define CONFIG_DDR_ECC +#define CONFIG_SYS_MBYTES_SDRAM 256 + +#define CAS_LATENCY JEDEC_MA_MR_CL_DDR2_5_0_CLK + +/* DDR1/2 SDRAM Device Control Register Data Values */ +#define CONFIG_SYS_SDRAM0_MB0CF (SDRAM_RXBAS_SDAM_MODE7 | \ + SDRAM_RXBAS_SDBE_ENABLE) +#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE +#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE +#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE +#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_MCHK_GEN | \ + SDRAM_MCOPT1_PMU_OPEN | \ + SDRAM_MCOPT1_DMWD_32 | \ + SDRAM_MCOPT1_8_BANKS | \ + SDRAM_MCOPT1_DDR2_TYPE | \ + SDRAM_MCOPT1_QDEP | \ + SDRAM_MCOPT1_RWOO_DISABLED | \ + SDRAM_MCOPT1_WOOO_DISABLED | \ + SDRAM_MCOPT1_DREF_NORMAL) +#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 +#define CONFIG_SYS_SDRAM0_MODT0 SDRAM_MODT_EB0W_ENABLE +#define CONFIG_SYS_SDRAM0_MODT1 0x00000000 +#define CONFIG_SYS_SDRAM0_MODT2 0x00000000 +#define CONFIG_SYS_SDRAM0_MODT3 0x00000000 +#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \ + SDRAM_CODT_DQS_1_8_V_DDR2 | \ + SDRAM_CODT_IO_NMODE) +#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560) +#define CONFIG_SYS_SDRAM0_INITPLR0 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(80) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP)) +#define CONFIG_SYS_SDRAM0_INITPLR1 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(3) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) +#define CONFIG_SYS_SDRAM0_INITPLR2 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL)) +#define CONFIG_SYS_SDRAM0_INITPLR3 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \ + SDRAM_INITPLR_IMA_ENCODE(0)) +#define CONFIG_SYS_SDRAM0_INITPLR4 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_ENABLE | \ + JEDEC_MA_EMR_RTT_150OHM)) +#define CONFIG_SYS_SDRAM0_INITPLR5 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(200) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ + CAS_LATENCY | \ + JEDEC_MA_MR_BLEN_4 | \ + JEDEC_MA_MR_DLL_RESET)) +#define CONFIG_SYS_SDRAM0_INITPLR6 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(3) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ + SDRAM_INITPLR_IBA_ENCODE(0x0) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) +#define CONFIG_SYS_SDRAM0_INITPLR7 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CONFIG_SYS_SDRAM0_INITPLR8 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CONFIG_SYS_SDRAM0_INITPLR9 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CONFIG_SYS_SDRAM0_INITPLR10 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CONFIG_SYS_SDRAM0_INITPLR11 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ + CAS_LATENCY | \ + JEDEC_MA_MR_BLEN_4)) +#define CONFIG_SYS_SDRAM0_INITPLR12 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \ + JEDEC_MA_EMR_RDQS_DISABLE | \ + JEDEC_MA_EMR_DQS_ENABLE | \ + JEDEC_MA_EMR_RTT_150OHM | \ + JEDEC_MA_EMR_ODS_NORMAL)) +#define CONFIG_SYS_SDRAM0_INITPLR13 \ + (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \ + JEDEC_MA_EMR_RDQS_DISABLE | \ + JEDEC_MA_EMR_DQS_ENABLE | \ + JEDEC_MA_EMR_RTT_150OHM | \ + JEDEC_MA_EMR_ODS_NORMAL)) +#define CONFIG_SYS_SDRAM0_INITPLR14 SDRAM_INITPLR_DISABLE +#define CONFIG_SYS_SDRAM0_INITPLR15 SDRAM_INITPLR_DISABLE +#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \ + SDRAM_RQDC_RQFD_ENCODE(56)) +#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(599) +#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2) +#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \ + SDRAM_DLCR_DLCS_CONT_DONE | \ + SDRAM_DLCR_DLCV_ENCODE(155)) +#define CONFIG_SYS_SDRAM0_CLKTR SDRAM_CLKTR_CLKP_90_DEG_ADV +#define CONFIG_SYS_SDRAM0_WRDTR SDRAM_WRDTR_WTR_90_DEG_ADV +#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \ + SDRAM_SDTR1_RTW_2_CLK | \ + SDRAM_SDTR1_RTRO_1_CLK) +#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \ + SDRAM_SDTR2_WTR_2_CLK | \ + SDRAM_SDTR2_XSNR_32_CLK | \ + SDRAM_SDTR2_WPC_4_CLK | \ + SDRAM_SDTR2_RPC_2_CLK | \ + SDRAM_SDTR2_RP_3_CLK | \ + SDRAM_SDTR2_RRD_2_CLK) +#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \ + SDRAM_SDTR3_RC_ENCODE(11) | \ + SDRAM_SDTR3_XCS | \ + SDRAM_SDTR3_RFC_ENCODE(26)) +#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \ + CAS_LATENCY | \ + SDRAM_MMODE_BLEN_4) +#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_ENABLE | \ + SDRAM_MEMODE_RTT_150OHM) + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ + +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 + +/* + * Ethernet + */ +#define CONFIG_IBM_EMAC4_V4 1 + +#define CONFIG_HAS_ETH0 + +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ +#define CONFIG_M88E1111_PHY +/* Disable fiber since fiber/copper auto-selection doesn't seem to work */ +#define CONFIG_M88E1111_DISABLE_FIBER + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_PHY_DYNAMIC_ANEG 1 + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fc000000\0" \ + "fdt_addr=fc1e0000\0" \ + "ramdisk_addr=fc200000\0" \ + "pciconfighost=1\0" \ + "pcie_mode=RP:RP\0" \ + "" + +/* + * Commands additional to the ones defined in amcc-common.h + */ +#define CONFIG_CMD_CHIP_CONFIG +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SDRAM + +/* + * PCI stuff + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE + +/* Board-specific PCI, no PCI support, only PCIe */ +#undef CONFIG_SYS_PCI_TARGET_INIT +#undef CONFIG_SYS_PCI_MASTER_INIT + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + + +/* + * External Bus Controller (EBC) Setup + */ + +/* + * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the + * boot EBC mapping only supports a maximum of 16MBytes + * (4.ff00.0000 - 4.ffff.ffff). + * To solve this problem, the flash has to get remapped to another + * EBC address which accepts bigger regions: + * + * 0xfc00.0000 -> 4.cc00.0000 + */ + +/* Memory Bank 0 (NOR-flash) */ +#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(16) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(1) | \ + EBC_BXAP_OEN_ENCODE(1) | \ + EBC_BXAP_WBN_ENCODE(1) | \ + EBC_BXAP_WBF_ENCODE(1) | \ + EBC_BXAP_TH_ENCODE(7) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_BOOT_BASE_ADDR) | \ + EBC_BXCR_BS_16MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/* Memory Bank 1 (FPGA 1) */ +#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(5) | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(1) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_RW | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_32BIT) + +/* Memory Bank 2 (FPGA 2) */ +#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(5) | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(1) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_RW | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_32BIT) + +/* Memory Bank 3 (FPGA 3) */ +#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(5) | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(1) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_RW | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_32BIT) + +/* + * PPC4xx GPIO Configuration + */ + +#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \ +{ \ +/* GPIO Core 0 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \ +}, \ +{ \ +/* GPIO Core 1 */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \ +{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ +} \ +} + +#endif /* __CONFIG_H */ |