diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/EB+MCF-EV123.h | 16 | ||||
| -rw-r--r-- | include/configs/M52277EVB.h | 155 | ||||
| -rw-r--r-- | include/configs/M5235EVB.h | 10 | ||||
| -rw-r--r-- | include/configs/M5249EVB.h | 14 | ||||
| -rw-r--r-- | include/configs/M5253DEMO.h | 24 | ||||
| -rw-r--r-- | include/configs/M5253EVBE.h | 20 | ||||
| -rw-r--r-- | include/configs/M5272C3.h | 14 | ||||
| -rw-r--r-- | include/configs/M5275EVB.h | 14 | ||||
| -rw-r--r-- | include/configs/M5282EVB.h | 18 | ||||
| -rw-r--r-- | include/configs/M53017EVB.h | 247 | ||||
| -rw-r--r-- | include/configs/MPC8572DS.h | 63 | ||||
| -rw-r--r-- | include/configs/TASREG.h | 14 | ||||
| -rw-r--r-- | include/configs/TQM8260.h | 7 | ||||
| -rw-r--r-- | include/configs/afeb9260.h | 169 | ||||
| -rw-r--r-- | include/configs/fx12mm.h | 13 | ||||
| -rw-r--r-- | include/configs/mgsuvd.h | 3 |
16 files changed, 636 insertions, 165 deletions
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index 876ec20..a13db7c 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -178,7 +178,7 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE1 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE1 -#define CONFIG_SYS_FLASH_BASE 0xFFE00000 +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 @@ -218,17 +218,13 @@ * Memory bank definitions */ -#define CONFIG_SYS_CS0_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE 2*1024*1024 -#define CONFIG_SYS_CS0_WIDTH 16 -#define CONFIG_SYS_CS0_RO 0 -#define CONFIG_SYS_CS0_WS 6 +#define CONFIG_SYS_CS0_BASE 0xFFE00000 +#define CONFIG_SYS_CS0_CTRL 0x00001980 +#define CONFIG_SYS_CS0_MASK 0x001F0001 #define CONFIG_SYS_CS3_BASE 0xE0000000 -#define CONFIG_SYS_CS3_SIZE 1*1024*1024 -#define CONFIG_SYS_CS3_WIDTH 16 -#define CONFIG_SYS_CS3_RO 0 -#define CONFIG_SYS_CS3_WS 6 +#define CONFIG_SYS_CS0_CTRL 0x00001980 +#define CONFIG_SYS_CS3_MASK 0x000F0001 /*----------------------------------------------------------------------- * Port configuration diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index b6226c6..5d5966f 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -40,7 +40,7 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #undef CONFIG_WATCHDOG @@ -72,21 +72,50 @@ #define CONFIG_CMD_REGINFO #undef CONFIG_CMD_USB #undef CONFIG_CMD_BMP - -#define CONFIG_HOSTNAME M52277EVB +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF + +#define CONFIG_HOSTNAME M52277EVB +#define CONFIG_SYS_UBOOT_END 0x3FFFF +#define CONFIG_SYS_LOAD_ADDR2 0x40010007 +#ifdef CONFIG_SYS_STMICRO_BOOT +/* ST Micro serial flash */ #define CONFIG_EXTRA_ENV_SETTINGS \ "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ + "loadaddr=0x40010000\0" \ + "uboot=u-boot.bin\0" \ + "load=loadb ${loadaddr} ${baudrate};" \ + "loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ "upd=run load; run prog\0" \ - "prog=prot off 0 0x3ffff;" \ - "era 0 3ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ + "prog=sf probe 0:2 10000 1;" \ + "sf erase 0 30000;" \ + "sf write ${loadaddr} 0 30000;" \ "save\0" \ "" +#endif +#ifdef CONFIG_SYS_SPANSION_BOOT +#define CONFIG_EXTRA_ENV_SETTINGS \ + "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "uboot=u-boot.bin\0" \ + "load=loadb ${loadaddr} ${baudrate}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE) \ + " " MK_STR(CONFIG_SYS_UBOOT_END) ";" \ + "era " MK_STR(CONFIG_SYS_FLASH_BASE) " " \ + MK_STR(CONFIG_SYS_UBOOT_END) ";" \ + "cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE) \ + " ${filesize}; save\0" \ + "updsbf=run loadsbf; run progsbf\0" \ + "loadsbf=loadb ${loadaddr} ${baudrate};" \ + "loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ + "progsbf=sf probe 0:2 10000 1;" \ + "sf erase 0 30000;" \ + "sf write ${loadaddr} 0 30000;" \ + "" +#endif -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ /* LCD */ #ifdef CONFIG_CMD_BMP #define CONFIG_LCD @@ -102,7 +131,7 @@ #define CONFIG_DOS_PARTITION #define CONFIG_MAC_PARTITION #define CONFIG_ISO_PARTITION -#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 +#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 #define CONFIG_SYS_USB_EHCI_CPU_INIT #endif @@ -122,30 +151,53 @@ #define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* DSPI and Serial Flash */ +#define CONFIG_CF_DSPI +#define CONFIG_HARD_SPI +#define CONFIG_SYS_SER_FLASH_BASE 0x01000000 +#define CONFIG_SYS_SBFHDR_SIZE 0x7 +#ifdef CONFIG_CMD_SPI +# define CONFIG_SYS_DSPI_CS2 +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_STMICRO + +# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ + DSPI_DCTAR_CPOL | \ + DSPI_DCTAR_CPHA | \ + DSPI_DCTAR_PCSSCK_1CLK | \ + DSPI_DCTAR_PASC(0) | \ + DSPI_DCTAR_PDT(0) | \ + DSPI_DCTAR_CSSCK(0) | \ + DSPI_DCTAR_ASC(0) | \ + DSPI_DCTAR_PBR(0) | \ + DSPI_DCTAR_DT(1) | \ + DSPI_DCTAR_BR(1)) +#endif /* Input, PCI, Flexbus, and VCO */ #define CONFIG_EXTRA_CLOCK #define CONFIG_SYS_INPUT_CLKSRC 16000000 -#define CONFIG_PRAM 512 /* 512 KB */ +#define CONFIG_PRAM 2048 /* 2048 KB */ -#define CONFIG_SYS_PROMPT "-> " +#define CONFIG_SYS_PROMPT "-> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_MBAR 0xFC000000 @@ -155,17 +207,18 @@ * You should know what you are doing if you make changes here. */ -/*----------------------------------------------------------------------- +/* * Definitions for initial stack pointer and data area (in DPRAM) */ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 16) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32) +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) +#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - 32) -/*----------------------------------------------------------------------- +/* * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 @@ -177,11 +230,16 @@ #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 #define CONFIG_SYS_SDRAM_EMOD 0x81810000 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 +#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#ifdef CONFIG_CF_SBF +# define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400) +#else +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ @@ -189,24 +247,40 @@ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -/* Configuration for environment +/* + * Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OVERWRITE 1 +#ifdef CONFIG_CF_SBF +# define CONFIG_ENV_IS_IN_SPI_FLASH +# define CONFIG_ENV_SPI_CS 2 +#else +# define CONFIG_ENV_IS_IN_FLASH 1 +#endif +#define CONFIG_ENV_OVERWRITE 1 #undef CONFIG_ENV_IS_EMBEDDED /*----------------------------------------------------------------------- * FLASH organization */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -#define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000) -#define CONFIG_ENV_SECT_SIZE 0x8000 +#ifdef CONFIG_SYS_STMICRO_BOOT +# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE +# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE +# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_ENV_OFFSET 0x30000 +# define CONFIG_ENV_SIZE 0x1000 +# define CONFIG_ENV_SECT_SIZE 0x10000 +#endif +#ifdef CONFIG_SYS_SPANSION_BOOT +# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000) +# define CONFIG_ENV_SIZE 0x1000 +# define CONFIG_ENV_SECT_SIZE 0x8000 +#endif #define CONFIG_SYS_FLASH_CFI #ifdef CONFIG_SYS_FLASH_CFI - # define CONFIG_FLASH_CFI_DRIVER 1 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT @@ -214,6 +288,7 @@ # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ # define CONFIG_SYS_FLASH_CHECKSUM +# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } #endif /* @@ -229,7 +304,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 +#define CONFIG_SYS_CACHELINE_SIZE 16 /*----------------------------------------------------------------------- * Memory bank definitions @@ -243,8 +318,14 @@ * CS5 - Available */ +#ifdef CONFIG_CF_SBF +#define CONFIG_SYS_CS0_BASE 0x04000000 +#define CONFIG_SYS_CS0_MASK 0x00FF0001 +#define CONFIG_SYS_CS0_CTRL 0x00001FA0 +#else #define CONFIG_SYS_CS0_BASE 0x00000000 #define CONFIG_SYS_CS0_MASK 0x00FF0001 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 +#endif #endif /* _M52277EVB_H */ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index e6c87ef..8c66f87 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -215,7 +215,7 @@ # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ #endif -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE << 16) +#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -251,13 +251,13 @@ * CS7 - Available */ #ifdef NORFLASH_PS32BIT -# define CONFIG_SYS_CS0_BASE 0xFFC0 +# define CONFIG_SYS_CS0_BASE 0xFFC00000 # define CONFIG_SYS_CS0_MASK 0x003f0001 -# define CONFIG_SYS_CS0_CTRL 0x1D00 +# define CONFIG_SYS_CS0_CTRL 0x00001D00 #else -# define CONFIG_SYS_CS0_BASE 0xFFE0 +# define CONFIG_SYS_CS0_BASE 0xFFE00000 # define CONFIG_SYS_CS0_MASK 0x001f0001 -# define CONFIG_SYS_CS0_CTRL 0x1D80 +# define CONFIG_SYS_CS0_CTRL 0x00001D80 #endif #endif /* _M5329EVB_H */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 8699ef9..e3830e5 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -125,7 +125,7 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CSAR0 << 16) +#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) #if 0 /* test-only */ #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ @@ -170,15 +170,15 @@ */ /* CS0 - AMD Flash, address 0xffc00000 */ -#define CONFIG_SYS_CSAR0 0xffe0 -#define CONFIG_SYS_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */ +#define CONFIG_SYS_CS0_BASE 0xffe00000 +#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ -#define CONFIG_SYS_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ +#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ /* CS1 - FPGA, address 0xe0000000 */ -#define CONFIG_SYS_CSAR1 0xe000 -#define CONFIG_SYS_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */ -#define CONFIG_SYS_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ +#define CONFIG_SYS_CS1_BASE 0xe0000000 +#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ +#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ /*----------------------------------------------------------------------- * Port configuration diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 3a5c12f..378e45a 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -90,7 +90,7 @@ #define CONFIG_DRIVER_DM9000 #ifdef CONFIG_DRIVER_DM9000 -# define CONFIG_DM9000_BASE ((CONFIG_SYS_CSAR1 << 16) | 0x300) +# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) # define DM9000_IO CONFIG_DM9000_BASE # define DM9000_DATA (CONFIG_DM9000_BASE + 4) # undef CONFIG_DM9000_DEBUG @@ -202,7 +202,7 @@ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CSAR0 << 16) +#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 @@ -233,21 +233,13 @@ /* Port configuration */ #define CONFIG_SYS_FECI2C 0xF0 -#define CONFIG_SYS_CSAR0 0xFF80 -#define CONFIG_SYS_CSMR0 0x007F0021 -#define CONFIG_SYS_CSCR0 0x1D80 +#define CONFIG_SYS_CS0_BASE 0xFF800000 +#define CONFIG_SYS_CS0_MASK 0x007F0021 +#define CONFIG_SYS_CS0_CTRL 0x00001D80 -#define CONFIG_SYS_CSAR1 0xE000 -#define CONFIG_SYS_CSMR1 0x00000001 -#define CONFIG_SYS_CSCR1 0x3DD8 - -#define CONFIG_SYS_CSAR2 0 -#define CONFIG_SYS_CSMR2 0 -#define CONFIG_SYS_CSCR2 0 - -#define CONFIG_SYS_CSAR3 0 -#define CONFIG_SYS_CSMR3 0 -#define CONFIG_SYS_CSCR3 0 +#define CONFIG_SYS_CS1_BASE 0xE0000000 +#define CONFIG_SYS_CS1_MASK 0x00000001 +#define CONFIG_SYS_CS1_CTRL 0x00003DD8 /*----------------------------------------------------------------------- * Port configuration diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index c2cd62b..86de97d 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -166,7 +166,7 @@ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE 0xffe00000 +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 @@ -182,21 +182,9 @@ /* Port configuration */ #define CONFIG_SYS_FECI2C 0xF0 -#define CONFIG_SYS_CSAR0 0xFFE0 -#define CONFIG_SYS_CSMR0 0x001F0021 -#define CONFIG_SYS_CSCR0 0x1D80 - -#define CONFIG_SYS_CSAR1 0 -#define CONFIG_SYS_CSMR1 0 -#define CONFIG_SYS_CSCR1 0 - -#define CONFIG_SYS_CSAR2 0 -#define CONFIG_SYS_CSMR2 0 -#define CONFIG_SYS_CSCR2 0 - -#define CONFIG_SYS_CSAR3 0 -#define CONFIG_SYS_CSMR3 0 -#define CONFIG_SYS_CSCR3 0 +#define CONFIG_SYS_CS0_BASE 0xFFE00000 +#define CONFIG_SYS_CS0_MASK 0x001F0021 +#define CONFIG_SYS_CS0_CTRL 0x00001D80 /*----------------------------------------------------------------------- * Port configuration diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 779d373..fc73d64 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -194,12 +194,18 @@ */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -/*----------------------------------------------------------------------- +/* * FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 +#define CONFIG_SYS_FLASH_CFI +#ifdef CONFIG_SYS_FLASH_CFI +# define CONFIG_FLASH_CFI_DRIVER 1 +# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +#endif /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 1f3539e..db48d76 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -173,7 +173,7 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE 0xffe00000 +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE #ifdef CONFIG_MONITOR_IS_IN_RAM #define CONFIG_SYS_MONITOR_BASE 0x20000 @@ -211,13 +211,13 @@ /*----------------------------------------------------------------------- * Memory bank definitions */ -#define CONFIG_SYS_AR0_PRELIM (CONFIG_SYS_FLASH_BASE >> 16) -#define CONFIG_SYS_CR0_PRELIM 0x1980 -#define CONFIG_SYS_MR0_PRELIM 0x001F0001 +#define CONFIG_SYS_CS0_BASE 0xffe00000 +#define CONFIG_SYS_CS0_CTRL 0x00001980 +#define CONFIG_SYS_CS0_MASK 0x001F0001 -#define CONFIG_SYS_AR1_PRELIM 0x3000 -#define CONFIG_SYS_CR1_PRELIM 0x1900 -#define CONFIG_SYS_MR1_PRELIM 0x00070001 +#define CONFIG_SYS_CS1_BASE 0x30000000 +#define CONFIG_SYS_CS1_CTRL 0x00001900 +#define CONFIG_SYS_CS1_MASK 0x00070001 /*----------------------------------------------------------------------- * Port configuration diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index a8a2655..15590cf 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -165,7 +165,7 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE 0xffe00000 +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 @@ -212,18 +212,10 @@ /*----------------------------------------------------------------------- * Memory bank definitions */ -#define CONFIG_SYS_CS0_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE 2*1024*1024 -#define CONFIG_SYS_CS0_WIDTH 16 -#define CONFIG_SYS_CS0_RO 0 -#define CONFIG_SYS_CS0_WS 6 -/* -#define CONFIG_SYS_CS3_BASE 0xE0000000 -#define CONFIG_SYS_CS3_SIZE 1*1024*1024 -#define CONFIG_SYS_CS3_WIDTH 16 -#define CONFIG_SYS_CS3_RO 0 -#define CONFIG_SYS_CS3_WS 6 -*/ +#define CONFIG_SYS_CS0_BASE 0xFFE00000 +#define CONFIG_SYS_CS0_CTRL 0x00001980 +#define CONFIG_SYS_CS0_MASK 0x001F0001 + /*----------------------------------------------------------------------- * Port configuration */ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h new file mode 100644 index 0000000..df54c60 --- /dev/null +++ b/include/configs/M53017EVB.h @@ -0,0 +1,247 @@ +/* + * Configuation settings for the Freescale MCF53017EVB. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M53017EVB_H +#define _M53017EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF5301x /* define processor family */ +#define CONFIG_M53015 /* define processor type */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 + +/* Command line configuration */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#undef CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#define CONFIG_SYS_UNIFY_CACHE + +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_HAS_ETH1 + +# define CONFIG_SYS_FEC0_PINMUX 0 +# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE +# define CONFIG_SYS_FEC1_PINMUX 0 +# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +#define CONFIG_MCFRTC +#undef RTC_DEBUG +#define CONFIG_SYS_RTC_CNT (0x8000) +#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SPEED 80000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_UDP_CHECKSUM + +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME M53017 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 3ffff;" \ + "era 0 3ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ +#define CONFIG_SYS_PROMPT "-> " +#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +#ifdef CONFIG_CMD_KGDB +# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ +#define CONFIG_SYS_LOAD_ADDR 0x40010000 + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CLK 80000000 +#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 + +#define CONFIG_SYS_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/* + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_END 0x20000 /* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_CFG1 0x43711630 +#define CONFIG_SYS_SDRAM_CFG2 0x56670000 +#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 +#define CONFIG_SYS_SDRAM_EMOD 0x80010000 +#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 +#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) + +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CONFIG_SYS_FLASH_CFI +#ifdef CONFIG_SYS_FLASH_CFI +# define CONFIG_FLASH_CFI_DRIVER 1 +# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +#endif + +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CONFIG_ENV_OFFSET 0x8000 +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_IN_FLASH 1 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash + * CS1 - Ext SRAM + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ +#define CONFIG_SYS_CS0_BASE 0 +#define CONFIG_SYS_CS0_MASK 0x00FF0001 +#define CONFIG_SYS_CS0_CTRL 0x00001FA0 + +#define CONFIG_SYS_CS1_BASE 0xC0000000 +#define CONFIG_SYS_CS1_MASK 0x00070001 +#define CONFIG_SYS_CS1_CTRL 0x00001FA0 + +#endif /* _M53017EVB_H */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 244ecc2..c3693b8 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -158,7 +158,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Localbus non-cacheable * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable - * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable + * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable @@ -268,50 +268,49 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); CONFIG_SYS_NAND_BASE + 0x80000,\ CONFIG_SYS_NAND_BASE + 0xC0000} #define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define NAND_MAX_CHIPS 1 +#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_CMD_NAND 1 -#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) /* NAND flash config */ #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ - | OR_FCM_PGS /* Large Page*/ \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ + | OR_FCM_PGS /* Large Page*/ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ - + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ /* Serial Port - controlled on board with jumper J8 diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h index 18ffbfd..25f3a26 100644 --- a/include/configs/TASREG.h +++ b/include/configs/TASREG.h @@ -206,7 +206,7 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE 0xffc00000 +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE #if 0 /* test-only */ #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ @@ -257,15 +257,15 @@ */ /* CS0 - AMD Flash, address 0xffc00000 */ -#define CONFIG_SYS_CSAR0 0xffc0 -#define CONFIG_SYS_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */ +#define CONFIG_SYS_CS0_BASE 0xffc00000 +#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ -#define CONFIG_SYS_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ +#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ /* CS1 - FPGA, address 0xe0000000 */ -#define CONFIG_SYS_CSAR1 0xe000 -#define CONFIG_SYS_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */ -#define CONFIG_SYS_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ +#define CONFIG_SYS_CS1_BASE 0xe0000000 +#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ +#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ /*----------------------------------------------------------------------- * Port configuration diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h index 533c7ad..ac9c94e 100644 --- a/include/configs/TQM8260.h +++ b/include/configs/TQM8260.h @@ -300,6 +300,13 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +/* use CFI flash driver */ +#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) #define CONFIG_ENV_SIZE 0x08000 diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h new file mode 100644 index 0000000..755952f --- /dev/null +++ b/include/configs/afeb9260.h @@ -0,0 +1,169 @@ +/* + * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org> + * + * Configuation settings for the AFEB9260 board. + * Based on configuration for AT91SAM9260-EK + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ +#define AT91_MASTER_CLOCK 89999598 /* peripheral = main / 2 */ +#define CONFIG_SYS_HZ 1000000 /* 1us resolution */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/ +#define CONFIG_AFEB9260 1 /* on an AFEB9260 Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 + +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NAND flash */ +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 + +/* NOR flash - no real flash on this board */ +#define CONFIG_SYS_NO_FLASH 1 + +/* Ethernet */ +#define CONFIG_MACB 1 +#undef CONFIG_RMII /* We have full MII there */ +#define CONFIG_RESET_PHY_R 1 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 + +/* USB */ +#define CONFIG_USB_OHCI_NEW 1 +#define LITTLEENDIAN 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#define CONFIG_USB_STORAGE 1 + +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x21e00000 + +#undef CONFIG_SYS_USE_DATAFLASH_CS0 +#define CONFIG_SYS_USE_DATAFLASH_CS1 1 +#undef CONFIG_SYS_USE_NANDFLASH + +/* bootstrap + u-boot + env + linux in dataflash on CS1 */ +#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400) +#define CONFIG_ENV_OFFSET 0x4200 +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xa0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock2 " \ + "rw rootfstype=jffs2 panic=20" + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif + diff --git a/include/configs/fx12mm.h b/include/configs/fx12mm.h index 8481c33..5844567 100644 --- a/include/configs/fx12mm.h +++ b/include/configs/fx12mm.h @@ -25,11 +25,10 @@ * MA 02111-1307 USA */ - /* - Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec, - see http://www.em.avnet.com -*/ + * Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec, + * see http://www.em.avnet.com + */ #ifndef __CONFIG_FX12_H #define __CONFIG_FX12_H @@ -54,7 +53,7 @@ /*Misc*/ #define CONFIG_SYS_PROMPT "FX12MM:/# " /* Monitor Command Prompt */ -#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" +#define CONFIG_PREBOOT "echo U-Boot is up and running;" /*Flash*/ #define CONFIG_SYS_FLASH_SIZE (4*1024*1024) @@ -62,8 +61,6 @@ #define MTDIDS_DEFAULT "nor0=fx12mm-flash" #define MTDPARTS_DEFAULT "mtdparts=fx12mm-flash:-(user)" - #include "configs/xilinx-ppc405.h" -#endif /* __CONFIG_H */ - +#endif /* __CONFIG_H */ diff --git a/include/configs/mgsuvd.h b/include/configs/mgsuvd.h index ff52f84..fca2e55 100644 --- a/include/configs/mgsuvd.h +++ b/include/configs/mgsuvd.h @@ -329,9 +329,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,866@0" -#define OF_SOC "soc@fff00000" -#define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc/cpm/serial@a80" /* enable I2C and select the hardware/software driver */ |