diff options
Diffstat (limited to 'include/configs')
55 files changed, 2911 insertions, 267 deletions
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 9841893..d03c05b 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -132,6 +132,9 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ + +#define CFG_NAND_LEGACY + #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/Adder.h b/include/configs/Adder.h index f807546..0e6b50f 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004 Arabella Software Ltd. + * Copyright (C) 2004-2005 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> * * Support for Analogue&Micro Adder boards family. @@ -35,11 +35,13 @@ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_BAUDRATE 38400 -#define CONFIG_FEC_ENET /* Ethernet is on FEC */ -#ifdef CONFIG_FEC_ENET +#define CONFIG_ETHER_ON_FEC1 +#define CONFIG_ETHER_ON_FEC2 + +#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) #define CFG_DISCOVER_PHY #define FEC_ENET -#endif /* CONFIG_FEC_ENET */ +#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */ #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 @@ -47,7 +49,7 @@ #ifdef CONFIG_MPC852T #define CFG_8xx_CPUCLK_MAX 50000000 #else -#define CFG_8xx_CPUCLK_MAX 120000000 +#define CFG_8xx_CPUCLK_MAX 133000000 #endif /* CONFIG_MPC852T */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ @@ -62,7 +64,7 @@ #define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" +#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)" #define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ @@ -79,7 +81,7 @@ #define CFG_MAXARGS 16 /* Max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x100000 /* Default load address */ +#define CFG_LOAD_ADDR 0x400000 /* Default load address */ #define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ @@ -89,24 +91,21 @@ * RAM configuration (note that CFG_SDRAM_BASE must be zero) */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ - -#define CFG_OR1_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_ACS_DIV2) -#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V) +#define CFG_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */ -#define CFG_MAMR 0x00802114 +#define CFG_MAMR 0x00002114 /* - * 2048 SDRAM rows + * 4096 Up to 4096 SDRAM rows * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 32 PTP (pre-divider from MPTPR) * 4 Number of refresh cycles per period * 64 Refresh cycle in ms per number of rows */ -#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64)) +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00700000 /* 1 ... 7 MB in SDRAM */ +#define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */ #define CFG_RESET_ADDRESS 0x09900000 @@ -139,6 +138,8 @@ #define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CONFIG_ENV_OVERWRITE + #define CFG_OR0_PRELIM 0xFF000774 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V) diff --git a/include/configs/BMW.h b/include/configs/BMW.h index 050054d..3bd43d8 100644 --- a/include/configs/BMW.h +++ b/include/configs/BMW.h @@ -69,6 +69,10 @@ CFG_CMD_DOC | \ CFG_CMD_ELF | \ 0 ) + +/* CFG_CMD_DOC required legacy NAND support */ +#define CFG_NAND_LEGACY + #if 0 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | \ CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE) diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 6025886..1cca285 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -81,6 +81,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index efc3ada..047e2f1 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -79,6 +79,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 1347f2a..d756f44 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -100,6 +100,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 9d52815..852d94a 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -87,6 +87,9 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 946a0fd..2260327 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -98,6 +98,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 1632f37..244e45a 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -57,7 +57,7 @@ #define CONFIG_CPCI750 1 /* this is an CPCI750 board */ -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ +#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ #undef CONFIG_ECC /* enable ECC support */ @@ -84,19 +84,19 @@ * for your console driver. * * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial + * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial * cable onto the second DUART channel, change the CFG_DUART port from 1 * to 0 below. * * to use the MPSC, #define CONFIG_MPSC. If you have wired up another * mpsc channel, change CONFIG_MPSC_PORT to the desired value. */ -#define CONFIG_MPSC +#define CONFIG_MPSC #define CONFIG_MPSC_PORT 0 /* to change the default ethernet port, use this define (options: 0, 1, 2) */ #define CONFIG_NET_MULTI -#define MV_ETH_DEVS 1 +#define MV_ETH_DEVS 1 #define CONFIG_ETHER_PORT 0 #undef CONFIG_ETHER_PORT_MII /* use RMII */ @@ -118,38 +118,38 @@ #define CONFIG_SERIAL "AA000001" #define CONFIG_SERVERIP "10.0.0.79" -#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" +#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" #define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n +#define CONFIG_TESTDRAMADDRESS n #define CONFIG_TESETDRAMWALK n /* ----------------------------------------------------------------------------- */ -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ +#undef CONFIG_ALTIVEC /* undef to disable */ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_ASKENV \ - | CFG_CMD_I2C \ + | CFG_CMD_I2C \ | CFG_CMD_CACHE \ | CFG_CMD_EEPROM \ - | CFG_CMD_PCI \ + | CFG_CMD_PCI \ | CFG_CMD_ELF \ | CFG_CMD_DATE \ - | CFG_CMD_NET \ - | CFG_CMD_PING \ - | CFG_CMD_IDE \ - | CFG_CMD_FAT \ - | CFG_CMD_EXT2 \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + | CFG_CMD_IDE \ + | CFG_CMD_FAT \ + | CFG_CMD_EXT2 \ ) #define CONFIG_DOS_PARTITION @@ -159,7 +159,7 @@ #define CONFIG_USE_CPCIDVI -#ifdef CONFIG_USE_CPCIDVI +#ifdef CONFIG_USE_CPCIDVI #define CONFIG_VIDEO #define CONFIG_VIDEO_CT69000 #define CONFIG_CFB_CONSOLE @@ -174,23 +174,23 @@ */ #define CFG_I2C_EEPROM_ADDR_LEN 2 #define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_SPEED 80000 /* I2C speed default */ +#define CFG_I2C_SPEED 80000 /* I2C speed default */ #define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ /*#define CFG_MEMTEST_START 0x00400000*/ /* memtest works on */ /*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -/*#define CFG_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ +/*#define CFG_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ /* #define CFG_DRAM_TEST @@ -198,21 +198,21 @@ * CFG_DRAM_TEST - enables the following tests. * * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. + * Environment variable 'test_dram_data' must be + * set to 'y'. * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. + * addressable. Environment variable + * 'test_dram_address' must be set to 'y'. * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. + * This test takes about 6 minutes to test 64 MB. + * Environment variable 'test_dram_walk' must be + * set to 'y'. */ #define CFG_DRAM_TEST #if defined(CFG_DRAM_TEST) #define CFG_MEMTEST_START 0x00400000 /* memtest works on */ /*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ +#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ #define CFG_DRAM_TEST_DATA #define CFG_DRAM_TEST_ADDRESS #define CFG_DRAM_TEST_WALK @@ -221,10 +221,10 @@ #define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ #undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ -#define CFG_LOAD_ADDR 0x00300000 /* default load address */ +#define CFG_LOAD_ADDR 0x00300000 /* default load address */ -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ -#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ +#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ #define CFG_BUS_CLK CFG_BUS_HZ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } @@ -251,7 +251,7 @@ * To an unused memory region. The stack will remain in cache until RAM * is initialized */ -#undef CFG_INIT_RAM_LOCK +#undef CFG_INIT_RAM_LOCK /* #define CFG_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */ /* #define CFG_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */ #define CFG_INIT_RAM_ADDR 0xf1080000 /* unused memory region */ @@ -261,7 +261,7 @@ #define RELOCATE_INTERNAL_RAM_ADDR #ifdef RELOCATE_INTERNAL_RAM_ADDR -/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/ +/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/ #define CFG_INTERNAL_RAM_ADDR 0xf1080000 #endif @@ -270,16 +270,16 @@ * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 /* Dummies for BAT 4-7 */ -#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CFG_SDRAM2_BASE 0x20000000 -#define CFG_SDRAM3_BASE 0x30000000 -#define CFG_SDRAM4_BASE 0x40000000 +#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ +#define CFG_SDRAM2_BASE 0x20000000 +#define CFG_SDRAM3_BASE 0x30000000 +#define CFG_SDRAM4_BASE 0x40000000 #define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_BASE 0xfff00000 -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ /*----------------------------------------------------------------------- * FLASH related @@ -289,15 +289,15 @@ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_PROTECTION 1 /* use hardware protection */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */ +#define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */ #define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CFG_FLASH_INCREMENT 0x01000000 /* size of flash bank */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \ - CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT, \ - CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT, \ - CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT } -#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */ +#define CFG_FLASH_INCREMENT 0x01000000 /* size of flash bank */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \ + CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT, \ + CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT, \ + CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT } +#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */ /* areas to map different things with the GT in physical space */ #define CFG_DRAM_BANKS 4 @@ -308,20 +308,20 @@ /* Peripheral Device section */ /*******************************************************/ -/* We have on the cpci750 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ +/* We have on the cpci750 Board : */ +/* GT-Chipset Register Area */ +/* GT-Chipset internal SRAM 256k */ +/* SRAM on external device module */ +/* Real time clock on external device module */ +/* dobble UART on external device module */ +/* Data flash on external device module */ +/* Boot flash on external device module */ /*******************************************************/ #define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CFG_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ +#define CFG_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ -#undef MARVEL_STANDARD_CFG -#ifndef MARVEL_STANDARD_CFG +#undef MARVEL_STANDARD_CFG +#ifndef MARVEL_STANDARD_CFG /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ #define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ /*#define CFG_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */ @@ -333,11 +333,11 @@ #define CFG_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */ #define CFG_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */ -#define CFG_BOOT_SIZE _16M /* cpci750 flash 0 */ -#define CFG_DEV0_SIZE _16M /* cpci750 flash 1 */ -#define CFG_DEV1_SIZE _16M /* cpci750 flash 2 */ -#define CFG_DEV2_SIZE _16M /* cpci750 flash 3 */ -#define CFG_DEV3_SIZE _16M /* cpci750 nvram/can */ +#define CFG_BOOT_SIZE _16M /* cpci750 flash 0 */ +#define CFG_DEV0_SIZE _16M /* cpci750 flash 1 */ +#define CFG_DEV1_SIZE _16M /* cpci750 flash 2 */ +#define CFG_DEV2_SIZE _16M /* cpci750 flash 3 */ +#define CFG_DEV3_SIZE _16M /* cpci750 nvram/can */ /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ #endif @@ -346,22 +346,22 @@ #define CFG_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */ #define CFG_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */ #define CFG_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CFG_DEV3_PAR 0x8FCFFFFF /* nvram/can */ +#define CFG_DEV3_PAR 0x8FCFFFFF /* nvram/can */ #define CFG_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */ - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ + /* c 4 a 8 2 4 1 c */ + /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ /* MPP Control MV64360 Appendix P P. 632*/ -#define CFG_MPP_CONTROL_0 0x00002222 /* */ -#define CFG_MPP_CONTROL_1 0x11110000 /* */ -#define CFG_MPP_CONTROL_2 0x11111111 /* */ -#define CFG_MPP_CONTROL_3 0x00001111 /* */ -/* #define CFG_SERIAL_PORT_MUX 0x00000102*/ /* */ +#define CFG_MPP_CONTROL_0 0x00002222 /* */ +#define CFG_MPP_CONTROL_1 0x11110000 /* */ +#define CFG_MPP_CONTROL_2 0x11111111 /* */ +#define CFG_MPP_CONTROL_3 0x00001111 /* */ +/* #define CFG_SERIAL_PORT_MUX 0x00000102*/ /* */ #define CFG_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/ @@ -378,12 +378,12 @@ ECC disable non registered DRAM */ /* 31:26 25:22 21:20 19 18 17 16 */ - /* 100001 0000 010 0 0 0 0 */ + /* 100001 0000 010 0 0 0 0 */ /* refresh_count=0x400 phisical interleaving disable virtual interleaving enable */ /* 15 14 13:0 */ - /* 0 1 0x400 */ + /* 0 1 0x400 */ # define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ @@ -392,14 +392,14 @@ *----------------------------------------------------------------------- */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ /* PCI MEMORY MAP section */ #define CFG_PCI0_MEM_BASE 0x80000000 @@ -433,21 +433,21 @@ * IDE/ATA stuff *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET /* no reset for ide supported */ -#define CONFIG_IDE_PREINIT /* check for units */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET /* no reset for ide supported */ +#define CONFIG_IDE_PREINIT /* check for units */ -#define CFG_IDE_MAXBUS 2 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ +#define CFG_IDE_MAXBUS 2 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ -#define CFG_ATA_BASE_ADDR 0 -#define CFG_ATA_IDE0_OFFSET 0 -#define CFG_ATA_IDE1_OFFSET 0 +#define CFG_ATA_BASE_ADDR 0 +#define CFG_ATA_IDE0_OFFSET 0 +#define CFG_ATA_IDE1_OFFSET 0 -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ /*---------------------------------------------------------------------- @@ -551,7 +551,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization @@ -563,23 +563,23 @@ #define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ #if 0 -#define CFG_ENV_IS_IN_FLASH 0 -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_IS_IN_FLASH 0 +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x10000 #define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */ +/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */ #endif #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_EEPROM_PAGE_WRITE_BITS 5 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CFG_I2C_EEPROM_ADDR 0x050 +#define CFG_I2C_EEPROM_ADDR 0x050 #define CFG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */ #define CFG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/ #define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ #define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40) +#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40) /*----------------------------------------------------------------------- * Cache Configuration @@ -601,7 +601,7 @@ #if defined (CONFIG_750CX) || defined (CONFIG_750FX) #define L2_INIT 0 #else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) #endif @@ -612,9 +612,9 @@ * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_BOARD_ASM_INIT 1 +#define CFG_BOARD_ASM_INIT 1 #endif /* __CONFIG_H */ diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index 16a9ea5..1e9a99e 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -178,6 +178,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + /* * Miscellaneous configurable options */ diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h index a23d7e5..9a98e5c 100644 --- a/include/configs/CPU87.h +++ b/include/configs/CPU87.h @@ -189,6 +189,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + /* * Miscellaneous configurable options */ diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h new file mode 100644 index 0000000..738763b --- /dev/null +++ b/include/configs/EP88x.h @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2005 Arabella Software Ltd. + * Yuli Barcohen <yuli@arabellasw.com> + * + * Support for Embedded Planet EP88x boards. + * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MPC885 + +#define CONFIG_EP88X /* Embedded Planet EP88x board */ + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ + +/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_ETHER_ON_FEC1 /* Enable Ethernet on FEC1 */ +#define CONFIG_ETHER_ON_FEC2 /* Enable Ethernet on FEC2 */ +#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) +#define CFG_DISCOVER_PHY +#define FEC_ENET +#endif /* CONFIG_FEC_ENET */ + +#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ +#define CONFIG_8xx_CPUCLK_DEFAULT 100000000 +#define CFG_8xx_CPUCLK_MIN 40000000 +#define CFG_8xx_CPUCLK_MAX 133000000 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) + +/* This must be included AFTER the definition of CONFIG_COMMANDS */ +#include <cmd_confdefs.h> + +#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ +#define CONFIG_BOOTCOMMAND "bootm fe060000" /* Autoboot command */ +#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)" + +#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ +#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* #undef to save memory */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* Max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x400000 /* Default load address */ + +#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * RAM configuration (note that CFG_SDRAM_BASE must be zero) + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_MAX_SIZE 0x08000000 /* Up to 128 Mbyte */ + +#define CFG_MAMR 0x00805000 + +/* + * 4096 Up to 4096 SDRAM rows + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + */ +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */ + +#define CFG_RESET_ADDRESS 0x09900000 + +/*----------------------------------------------------------------------- + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */ +#ifdef CONFIG_BZIP2 +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */ +#else +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ +#endif /* CONFIG_BZIP2 */ + +/*----------------------------------------------------------------------- + * Flash organisation + */ +#define CFG_FLASH_BASE 0xFC000000 +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 512 /* Max num of sects on one chip */ + +/* Environment is in flash */ +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + +#define CFG_OR0_PRELIM 0xFC000160 +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V) + +#define CFG_DIRECT_FLASH_TFTP + +/*----------------------------------------------------------------------- + * BCSR + */ +#define CFG_OR3_PRELIM 0xFF0005B0 +#define CFG_BR3_PRELIM (0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V) + +#define CFG_BCSR 0xFA400000 + +/*----------------------------------------------------------------------- + * Internal Memory Map Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Configuration registers + */ +#ifdef CONFIG_WATCHDOG +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ + SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \ + SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ + SYPCR_SWF | SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +#define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11) + +/* TBSCR - Time Base Status and Control Register */ +#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE) + +/* PISCR - Periodic Interrupt Status and Control */ +#define CFG_PISCR PISCR_PS + +/* SCCR - System Clock and reset Control Register */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR SCCR_RTSEL + +#define CFG_DER 0 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */ + +/*----------------------------------------------------------------------- + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index de8f7ae..6613f90 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -284,6 +284,8 @@ */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + /* * Verbose help from command monitor. */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 4f62b8a..dc40ebc 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -130,6 +130,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + #undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* watchdog disabled */ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index eb627e8..f84e356 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -135,6 +135,8 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ +#define CFG_NAND_LEGACY + #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h index 65056a2..706bdb9 100644 --- a/include/configs/ISPAN.h +++ b/include/configs/ISPAN.h @@ -109,7 +109,6 @@ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL \ | CFG_CMD_ASKENV \ | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ | CFG_CMD_IMMAP \ | CFG_CMD_MII \ | CFG_CMD_PING \ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index afba5c6..596e52c 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -122,9 +122,13 @@ # define CFG_LOWBOOT16 1 #endif #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ +#if defined(CONFIG_LITE5200B) +# error CFG_LOWBOOT08 is incompatible with the Lite5200B +#else # define CFG_LOWBOOT 1 # define CFG_LOWBOOT08 1 #endif +#endif /* * Autobooting @@ -160,8 +164,12 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#if defined(CONFIG_LITE5200B) +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#else +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ #endif +#endif /* CONFIG_MPC5200 */ /* * I2C configuration */ @@ -182,6 +190,20 @@ /* * Flash configuration */ +#if defined(CONFIG_LITE5200B) +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_SIZE 0x01000000 +#if !defined(CFG_LOWBOOT) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01760000 + 0x00800000) +#else /* CFG_LOWBOOT */ +#if defined(CFG_LOWBOOT08) +# error CFG_LOWBOOT08 is incompatible with the Lite5200B +#endif +#if defined(CFG_LOWBOOT16) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01060000) +#endif +#endif /* CFG_LOWBOOT */ +#else /* !CONFIG_LITE5200B (IceCube)*/ #define CFG_FLASH_BASE 0xFF000000 #define CFG_FLASH_SIZE 0x01000000 #if !defined(CFG_LOWBOOT) @@ -194,6 +216,7 @@ #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) #endif #endif /* CFG_LOWBOOT */ +#endif /* CONFIG_LITE5200B */ #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ @@ -203,13 +226,23 @@ #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ +#if defined(CONFIG_LITE5200B) +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_BANKS_LIST {CFG_CS1_START,CFG_CS0_START} +#endif + /* * Environment settings */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 0x10000 +#if defined(CONFIG_LITE5200B) +#define CFG_ENV_SECT_SIZE 0x20000 +#else #define CFG_ENV_SECT_SIZE 0x10000 +#endif #define CONFIG_ENV_OVERWRITE 1 /* @@ -246,6 +279,9 @@ */ /* #define CONFIG_FEC_10MBIT 1 */ #define CONFIG_PHY_ADDR 0x00 +#if defined(CONFIG_LITE5200B) +#define CONFIG_FEC_MII100 1 +#endif /* * GPIO configuration @@ -288,6 +324,16 @@ #define CFG_HID0_FINAL 0 #endif +#if defined(CONFIG_LITE5200B) +#define CFG_CS1_START CFG_FLASH_BASE +#define CFG_CS1_SIZE CFG_FLASH_SIZE +#define CFG_CS1_CFG 0x00047800 +#define CFG_CS0_START (CFG_FLASH_BASE + CFG_FLASH_SIZE) +#define CFG_CS0_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_START CFG_CS0_START +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00047800 +#else /* IceCube aka Lite5200 */ #ifdef CONFIG_MPC5200_DDR #define CFG_BOOTCS_START (CFG_CS1_START + CFG_CS1_SIZE) @@ -306,6 +352,7 @@ #define CFG_CS0_SIZE CFG_FLASH_SIZE #endif /* CONFIG_MPC5200_DDR */ +#endif /*CONFIG_LITE5200B */ #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x33333333 diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index db2147b..7e57a0f 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -58,7 +58,6 @@ CFG_CMD_CACHE | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ CFG_CMD_FAT | \ @@ -87,6 +86,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " /************************************************************** diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h new file mode 100644 index 0000000..39e3d95 --- /dev/null +++ b/include/configs/MPC8349EMDS.h @@ -0,0 +1,716 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8349emds board configuration file + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define DEBUG +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC8349 1 /* MPC8349 specific */ +#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ + +/* FIXME: Real PCI support will come in a follow-up update. */ +#undef CONFIG_PCI + +#define PCI_66M +#ifdef PCI_66M +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#ifdef PCI_66M +#define CONFIG_SYS_CLK_FREQ 66000000 +#else +#define CONFIG_SYS_CLK_FREQ 33000000 +#endif +#endif + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +#define CFG_IMMRBAR 0xE0000000 + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 /* memtest region */ +#define CFG_MEMTEST_END 0x00100000 + +/* + * DDR Setup + */ +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#undef CONFIG_DDR_2T_TIMING + +#if defined(CONFIG_SPD_EEPROM) +/* + * Determine DDR configuration from I2C interface. + */ +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +#else +/* + * Manually set up DDR parameters + */ +#define CFG_DDR_SIZE 256 /* MB */ +#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) +#define CFG_DDR_TIMING_1 0x36332321 +#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ + +#if defined(CONFIG_DDR_32BIT) +/* set burst length to 8 for 32-bit data path */ +#define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ +#else +/* the default burst length is 4 - for 64-bit data path */ +#define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ +#endif +#endif + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CFG_FLASH_SIZE 8 /* flash size in MB */ +/* #define CFG_FLASH_USE_BUFFER_WRITE */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ + BR_V) /* valid */ + +#define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MID_FLASH_JUMP 0x7F000000 +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +/* + * BCSR register on local bus 32KB, 8-bit wide for MDS config reg + */ +#define CFG_BCSR 0xF8000000 +#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ +#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ +#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ +#define CFG_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xE8000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + * LCRR: DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CFG_LBC_LBCR 0x00000000 + +#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ + +#ifdef CFG_LB_SDRAM +/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ +#define CFG_LBLAWBAR2_PRELIM 0xF0000000 +#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 + */ + +#define CFG_OR2_PRELIM 0xFC006901 + +#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ + | CFG_LBC_LSDMR_BSMA1516 \ + | CFG_LBC_LSDMR_RFCR8 \ + | CFG_LBC_LSDMR_PRETOACT6 \ + | CFG_LBC_LSDMR_ACTTORW3 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC3 \ + | CFG_LBC_LSDMR_CL3 \ + ) + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) +#endif + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* TSEC */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) + +/* IO Configuration */ +#define CFG_IO_CONF (\ + IO_CONF_UART |\ + IO_CONF_TSEC1 |\ + IO_CONF_IRQ0 |\ + IO_CONF_IRQ1 |\ + IO_CONF_IRQ2 |\ + IO_CONF_IRQ3 |\ + IO_CONF_IRQ4 |\ + IO_CONF_IRQ5 |\ + IO_CONF_IRQ6 |\ + IO_CONF_IRQ7 ) + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#define CFG_PCI2_MEM_BASE 0xA0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe3000000 +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ + +#if defined(CONFIG_PCI) + +#define PCI_ALL_PCI1 +#if defined(PCI_64BIT) +#undef PCI_ALL_PCI1 +#undef PCI_TWO_PCI1 +#undef PCI_ONE_PCI1 +#endif + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +/* + * TSEC configuration + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ + +#if defined(CONFIG_TSEC_ENET) +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_GMII 1 /* MII PHY management */ +#define CONFIG_MPC83XX_TSEC1 1 +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC83XX_TSEC2 1 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C \ + | CFG_CMD_DATE) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_DATE) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#endif +#else +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_DATE \ + ) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII \ + | CFG_CMD_DATE \ + ) +#endif +#endif + +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#if 1 /*528/264*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) +#elif 0 /*396/132*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_3X1) +#elif 0 /*264/132*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_2X1) +#elif 0 /*132/132*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_1X1) +#elif 0 /*264/264 */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_1X1) +#endif + +#if defined(PCI_64BIT) +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#endif + +/* System IO Config */ +#define CFG_SICRH SICRH_TSOBI1 +#define CFG_SICRL SICRL_LDP_A + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT + +/* #define CFG_HID0_FINAL (\ + HID0_ENABLE_INSTRUCTION_CACHE |\ + HID0_ENABLE_M_BIT |\ + HID0_ENABLE_ADDRESS_BROADCAST ) */ + + +#define CFG_HID2 HID2_HBE + +/* DDR @ 0x00000000 */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#ifdef CONFIG_PCI +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT1L (0) +#define CFG_IBAT1U (0) +#define CFG_IBAT2L (0) +#define CFG_IBAT2U (0) +#endif + +/* IMMRBAR @ 0xE0000000 */ +#define CFG_IBAT3L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT3U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP) + +/* stack in DCACHE (no backing mem) @ 0xE8000000 */ +#define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +/* LBC SDRAM @ 0xF0000000 */ +#define CFG_IBAT5L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT5U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) + +/* BCSR @ 0xF8000000 */ +#define CFG_IBAT6L (CFG_BCSR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT6U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) + +/* FLASH @ 0xFE000000 */ +#define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:04:9f:ef:23:33 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 +#endif + +#define CONFIG_IPADDR 192.168.205.5 + +#define CONFIG_HOSTNAME mpc8349emds +#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx +#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=mpc8349emds\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=/tftpboot/mpc8349emds/uImage\0" \ + "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ + "update=protect off fe000000 fe03ffff; " \ + "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ + "upd=run load;run update\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h index 565f9bb..831cc5e 100644 --- a/include/configs/MPC86xADS.h +++ b/include/configs/MPC86xADS.h @@ -21,7 +21,7 @@ #define CONFIG_MPC86xADS 1 /* new ADS */ #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ -/* New MPC86xADS - pick one of these */ +/* CPU type - pick one of these */ #define CONFIG_MPC866T 1 #undef CONFIG_MPC866P #undef CONFIG_MPC859T @@ -33,7 +33,10 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 38400 -#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */ +#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */ +#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 +#define CFG_8xx_CPUCLK_MIN 40000000 +#define CFG_8xx_CPUCLK_MAX 80000000 #define CONFIG_DRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ 1 diff --git a/include/configs/MPC885ADS.h b/include/configs/MPC885ADS.h index 74318e5..1867c5b 100644 --- a/include/configs/MPC885ADS.h +++ b/include/configs/MPC885ADS.h @@ -1,44 +1,34 @@ /* * A collection of structures, addresses, and values associated with - * the Motorola DUET ADS board. Values common to all FADS family boards + * the Motorola MPC885ADS board. Values common to all FADS family boards * are in board/fads/fads.h * - * Copyright (C) 2003 Arabella Software Ltd. + * Copyright (C) 2003-2004 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> */ #ifndef __CONFIG_H #define __CONFIG_H -/* Board type */ -#define CONFIG_MPC885ADS 1 /* Duet (MPC87x/88x) ADS */ +#define CONFIG_MPC885ADS 1 /* MPC885ADS board */ #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ -#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ +#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 38400 -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ - -#define CFG_PLPRCR ((1 << PLPRCR_MFD_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) +#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ +#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 +#define CFG_8xx_CPUCLK_MIN 40000000 +#define CFG_8xx_CPUCLK_MAX 133000000 #define CONFIG_SDRAM_50MHZ 1 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - #include "fads.h" -#undef CFG_SCCR -#define CFG_SCCR (SCCR_TBS|SCCR_EBDF11) - #define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ #define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h index bf4c899..444f721 100644 --- a/include/configs/NETPHONE.h +++ b/include/configs/NETPHONE.h @@ -491,6 +491,7 @@ /****************************************************************/ /* NAND */ +#define CFG_NAND_LEGACY #define CFG_NAND_BASE NAND_BASE #define CONFIG_MTD_NAND_ECC_JFFS2 #define CONFIG_MTD_NAND_VERIFY_WRITE diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h index 529cb4c..e20e724 100644 --- a/include/configs/NETTA2.h +++ b/include/configs/NETTA2.h @@ -491,6 +491,7 @@ /****************************************************************/ /* NAND */ +#define CFG_NAND_LEGACY #define CFG_NAND_BASE NAND_BASE #define CONFIG_MTD_NAND_ECC_JFFS2 #define CONFIG_MTD_NAND_VERIFY_WRITE diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index dc6b15f..e30be09 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -387,6 +387,8 @@ /*****************************************************************************/ +#define CFG_NAND_LEGACY + #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 /* NAND */ diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h index d03706e..3a97fbc 100644 --- a/include/configs/PCIPPC2.h +++ b/include/configs/PCIPPC2.h @@ -77,6 +77,7 @@ */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY /* * Miscellaneous configurable options diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h index 92b2f7c..130beb7 100644 --- a/include/configs/PCIPPC6.h +++ b/include/configs/PCIPPC6.h @@ -79,6 +79,7 @@ */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY /* * Miscellaneous configurable options diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 9668fb0..806e95f 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -50,7 +50,6 @@ CFG_CMD_PCI | \ CFG_CMD_CACHE | \ CFG_CMD_IRQ | \ - CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_REGINFO | \ @@ -69,6 +68,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " /************************************************************** diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 54ecfa4..dd5d831 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -160,6 +160,8 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ +#define CFG_NAND_LEGACY + #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/PM520.h b/include/configs/PM520.h index e73ad51..9c241e6 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -101,6 +101,8 @@ #define ADD_DOC_CMD 0 #else #define ADD_DOC_CMD CFG_CMD_DOC +/* DoC requires legacy NAND for now */ +#define CFG_NAND_LEGACY #endif /* diff --git a/include/configs/PM826.h b/include/configs/PM826.h index 6e5e3bb..88fdb51 100644 --- a/include/configs/PM826.h +++ b/include/configs/PM826.h @@ -180,6 +180,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + /* * Disk-On-Chip configuration */ diff --git a/include/configs/PM828.h b/include/configs/PM828.h index 982a1f8..37ee977 100644 --- a/include/configs/PM828.h +++ b/include/configs/PM828.h @@ -183,6 +183,7 @@ /* * Disk-On-Chip configuration */ +#define CFG_NAND_LEGACY #define CFG_DOC_SHORT_TIMEOUT #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 7ca827f..e1155e2 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -188,34 +188,34 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ +/* + * nand device 1 on dave (PPChameleonEVB) needs more time, + * so we just introduce additional wait in nand_wait(), + * effectively for both devices. + */ +#define PPCHAMELON_NAND_TIMER_HACK + #define CFG_NAND0_BASE 0xFF400000 #define CFG_NAND1_BASE 0xFF000000 +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, CFG_NAND1_BASE } +#define NAND_BIG_DELAY_US 25 +#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ -#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ -#define SECTORSIZE 512 -#define NAND_NO_RB - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 #define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ #define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ #define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ +#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ #define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ #define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ -#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ -#define NAND_DISABLE_CE(nand) do \ +#define MACRO_NAND_DISABLE_CE(nandptr) do \ { \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + switch((unsigned long)nandptr) \ { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \ @@ -226,9 +226,9 @@ } \ } while(0) -#define NAND_ENABLE_CE(nand) do \ +#define MACRO_NAND_ENABLE_CE(nandptr) do \ { \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + switch((unsigned long)nandptr) \ { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \ @@ -239,7 +239,7 @@ } \ } while(0) -#define NAND_CTL_CLRALE(nandptr) do \ +#define MACRO_NAND_CTL_CLRALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -252,7 +252,7 @@ } \ } while(0) -#define NAND_CTL_SETALE(nandptr) do \ +#define MACRO_NAND_CTL_SETALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -265,7 +265,7 @@ } \ } while(0) -#define NAND_CTL_CLRCLE(nandptr) do \ +#define MACRO_NAND_CTL_CLRCLE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -278,7 +278,7 @@ } \ } while(0) -#define NAND_CTL_SETCLE(nandptr) do { \ +#define MACRO_NAND_CTL_SETCLE(nandptr) do { \ switch((unsigned long)nandptr) { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \ @@ -289,6 +289,17 @@ } \ } while(0) +#if 0 +#define SECTORSIZE 512 +#define NAND_NO_RB + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 + #ifdef NAND_NO_RB /* constant delay (see also tR in the datasheet) */ #define NAND_WAIT_READY(nand) do { \ @@ -303,7 +314,7 @@ #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - +#endif /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -338,16 +349,16 @@ #define CFG_SDRAM_BASE 0x00000000 /* Reserve 256 kB for Monitor */ +/* #define CFG_FLASH_BASE 0xFFFC0000 #define CFG_MONITOR_BASE CFG_FLASH_BASE #define CFG_MONITOR_LEN (256 * 1024) +*/ /* Reserve 320 kB for Monitor */ -/* #define CFG_FLASH_BASE 0xFFFB0000 #define CFG_MONITOR_BASE CFG_FLASH_BASE #define CFG_MONITOR_LEN (320 * 1024) -*/ #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index 242c837..21945a3 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -326,6 +326,8 @@ /************************************************************ * Disk-On-Chip configuration ************************************************************/ +#define CFG_NAND_LEGACY + #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ #define CFG_DOC_SHORT_TIMEOUT #define CFG_DOC_SUPPORT_2000 diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h index 6b65031..48ada0e 100644 --- a/include/configs/RPXlite.h +++ b/include/configs/RPXlite.h @@ -21,10 +21,6 @@ * MA 02111-1307 USA */ -/* - * board/config.h - configuration options, board specific - */ - /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr * U-Boot port on RPXlite board */ @@ -53,8 +49,6 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ @@ -65,6 +59,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) @@ -86,12 +81,14 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x0040000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_RESET_ADDRESS 0x09900000 -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_LOAD_ADDR 0x400000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } @@ -120,16 +117,14 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFC00000 -/*%%% #define CFG_FLASH_BASE 0xFFF00000 */ -#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_MONITOR_BASE TEXT_BASE #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#ifdef CONFIG_BZIP2 +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */ #else -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE 0xFFF00000 -/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ +#endif /* CONFIG_BZIP2 */ /* * For booting Linux, the board info and command line data @@ -147,9 +142,13 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_DIRECT_FLASH_TFTP + #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + +#define CONFIG_ENV_OVERWRITE /*----------------------------------------------------------------------- * Cache Configuration @@ -352,12 +351,12 @@ #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ #define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ +#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ +#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ #define BCSR0_COLTEST 0x20 #define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 +#define BCSR0_ETHEN 0x80 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ #define BCSR1_PCVCTL6 0x02 @@ -371,22 +370,13 @@ #define BCSR2_USBSPD 0x40 #define BCSR2_USBSUSP 0x80 -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ +#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ +#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ #define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - - -/* - * Environment setting - */ - -#define CONFIG_ETHADDR 00:10:EC:00:1D:0B -#define CONFIG_IPADDR 192.168.1.65 -#define CONFIG_SERVERIP 192.168.1.27 +#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ +#define BCSR3_D27 0x10 /* Dip Switch settings */ +#define BCSR3_D26 0x20 +#define BCSR3_D25 0x40 +#define BCSR3_D24 0x80 #endif /* __CONFIG_H */ diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h index 8cd7df1..3102547 100644 --- a/include/configs/RPXlite_DW.h +++ b/include/configs/RPXlite_DW.h @@ -45,7 +45,7 @@ */ /* #define DEBUG 1 */ -/* #ifdef DEPLOYMENT 1 */ +/* #define DEPLOYMENT 1 */ #undef CONFIG_MPC860 #define CONFIG_MPC823 1 /* This is a MPC823e CPU. */ @@ -61,23 +61,23 @@ #define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */ #ifdef DEBUG -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ #else -#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */ +#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */ #ifdef DEPLOYMENT -#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 'st')...\n" -#define CONFIG_AUTOBOOT_STOP_STR "st" +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 'st')...\n" +#define CONFIG_AUTOBOOT_STOP_STR "st" #define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 1 -#define CONFIG_BOOT_RETRY_MIN 1 +#define CONFIG_RESET_TO_RETRY 1 +#define CONFIG_BOOT_RETRY_MIN 1 #endif /* DEPLOYMENT */ #endif /* DEBUG */ /* pre-boot commands */ -#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial" +#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial" #undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -117,6 +117,36 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +#if 1 /* Enable this stuff could make image enlarge about 25KB. Mask it if you + don't want the advanced function */ + +#ifdef CONFIG_SPLASH_SCREEN +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BMP | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_REGINFO | \ + CFG_CMD_DHCP ) +#else +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_REGINFO | \ + CFG_CMD_DHCP ) +#endif /* CONFIG_SPLASH_SCREEN */ + +/* test-only */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ + +#define CONFIG_NETCONSOLE + +#endif /* 1 */ + /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -280,7 +310,7 @@ #if defined(RPXlite_64MHz) #define CFG_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */ #else -#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */ +#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */ #endif /*----------------------------------------------------------------------- @@ -446,5 +476,6 @@ #define CONFIG_SERVERIP 172.16.115.6 #define CONFIG_ROOTPATH /workspace/myfilesystem/target/ #define CONFIG_BOOTFILE uImage.rpxusb +#define CONFIG_HOSTNAME LITE_H1_DW #endif /* __CONFIG_H */ diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h index 6ae9403..45907aa 100644 --- a/include/configs/RPXsuper.h +++ b/include/configs/RPXsuper.h @@ -154,7 +154,6 @@ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ CFG_CMD_IMMAP | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_I2C | \ CFG_CMD_REGINFO & \ ~CFG_CMD_KGDB ) diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h index a170f29..dbc57e8 100644 --- a/include/configs/Rattler.h +++ b/include/configs/Rattler.h @@ -127,7 +127,6 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ | CFG_CMD_IMMAP \ | CFG_CMD_JFFS2 \ | CFG_CMD_MII \ diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h index c1c765f..a8454d9 100644 --- a/include/configs/SXNI855T.h +++ b/include/configs/SXNI855T.h @@ -183,6 +183,7 @@ */ /* NAND flash support */ +#define CFG_NAND_LEGACY #define CONFIG_MTD_NAND_ECC_JFFS2 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 5ad1939..6020998 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -161,7 +161,6 @@ CFG_CMD_ASKENV | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_JFFS2 | \ diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 3ca137e..96f3d26 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -141,6 +141,8 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ +#define CFG_NAND_LEGACY + #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index d92f81f..faf855d 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -133,6 +133,8 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ +#define CFG_NAND_LEGACY + #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index f71e691..a5085cf 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2003-2004 Arabella Software Ltd. + * Copyright (C) 2003-2005 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> * * U-Boot configuration for Zephyr Engineering ZPC.1900 board. @@ -32,11 +32,7 @@ #define CPU_ID_STR "MPC8265" #define CONFIG_CPM2 1 /* Has a CPM2 */ -#undef DEBUG - -#undef CONFIG_BOARD_EARLY_INIT_F /* Don't call board_early_init_f */ - -/* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */ +/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ #define CONFIG_ENV_OVERWRITE /* @@ -113,7 +109,6 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_ASKENV \ | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ | CFG_CMD_IMMAP \ | CFG_CMD_MII \ | CFG_CMD_PING \ @@ -154,31 +149,30 @@ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ +#define CFG_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_LOAD_ADDR 0x400000 /* default load address */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CFG_FLASH_BASE 0xFFE00000 -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ - -#define CFG_DEFAULT_IMMR 0x0F010000 - -#define CFG_IMMR 0xF0000000 #define CFG_SDRAM_BASE 0x00000000 #define CFG_SDRAM_SIZE 64 -#define CFG_FLSIMM_BASE 0xFC000000 -#define CFG_LSDRAM_BASE 0xFE000000 + +#define CFG_IMMR 0xF0000000 +#define CFG_LSDRAM_BASE 0xFC000000 +#define CFG_FLASH_BASE 0xFE000000 #define CFG_BCSR 0xFEA00000 #define CFG_EEPROM 0xFEB00000 +#define CFG_FLSIMM_BASE 0xFF000000 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLSIMM_BASE } #define BCSR_PCI_MODE 0x01 @@ -190,10 +184,10 @@ /* Hard reset configuration word */ #define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\ - HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB010 |\ - HRCW_BMS | HRCW_LBPC01 | HRCW_APPC10 |\ - HRCW_MODCK_H0101 \ - ) /* 0x16828605 */ + HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\ + HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10 |\ + HRCW_MODCK_H0111 \ + ) /* 0x16848207 */ /* No slaves */ #define CFG_HRCW_SLAVE1 0 #define CFG_HRCW_SLAVE2 0 @@ -211,7 +205,7 @@ #define CFG_RAMBOOT #endif -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ @@ -233,14 +227,14 @@ # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) +#define CFG_HID0_INIT (HID0_ICFI) +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) #define CFG_HID2 0 #define CFG_SIUMCR 0x42200000 #define CFG_SYPCR 0xFFFFFFC3 -#define CFG_BCR 0x90400000 +#define CFG_BCR 0x90000000 #define CFG_SCCR SCCR_DFBRG01 #define CFG_RMR RMR_CSRE @@ -248,18 +242,23 @@ #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) #define CFG_RCCR 0 -#define CFG_PSDMR 0x014EB45A -#define CFG_PSRT 0x0C -#define CFG_LSDMR 0x008AB552 -#define CFG_LSRT 0x0E +#define CFG_PSDMR /* 0x834DA43B */0x014DA43A +#define CFG_PSRT 0x0F/* 0x0C */ +#define CFG_LSDMR 0x0085A562 +#define CFG_LSRT 0x0F #define CFG_MPTPR 0x4000 +#define CFG_PSDRAM_BR CFG_SDRAM_BASE | 0x00000041 +#define CFG_PSDRAM_OR 0xFC0028C0 +#define CFG_LSDRAM_BR CFG_LSDRAM_BASE | 0x00001861 +#define CFG_LSDRAM_OR 0xFF803480 + #define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801 #define CFG_OR0_PRELIM 0xFFE00856 #define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801 #define CFG_OR5_PRELIM 0xFFFF03F6 -#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00000801 -#define CFG_OR6_PRELIM 0xFE000856 +#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00001801 +#define CFG_OR6_PRELIM 0xFF000856 #define CFG_BR7_PRELIM CFG_BCSR | 0x00000801 #define CFG_OR7_PRELIM 0xFFFF83F6 diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index eacc744..6d32821 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -43,6 +43,7 @@ * 2nd ethernet port you have to "undef" the following define. */ #define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */ +#define CFG_NAND_LEGACY /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/delta.h b/include/configs/delta.h new file mode 100644 index 0000000..b42a7e2 --- /dev/null +++ b/include/configs/delta.h @@ -0,0 +1,287 @@ +/* + * Configuation settings for the Delta board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ +#define CONFIG_DELTA 1 /* Delta board */ + +/* #define CONFIG_LCD 1 */ +#ifdef CONFIG_LCD +#define CONFIG_SHARP_LM8V31 +#endif +/* #define CONFIG_MMC 1 */ +#define BOARD_LATE_INIT 1 + +#undef CONFIG_SKIP_RELOCATE_UBOOT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +#undef TURN_ON_ETHERNET +#ifdef TURN_ON_ETHERNET +# define CONFIG_DRIVER_SMC91111 1 +# define CONFIG_SMC91111_BASE 0x14000300 +# define CONFIG_SMC91111_EXT_PHY +# define CONFIG_SMC_USE_32_BIT +# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */ +#endif + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */ +#ifdef TURN_ON_ETHERNET +# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) +#else +# define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_ENV | CFG_CMD_NAND) \ + & ~(CFG_CMD_NET | CFG_CMD_FLASH | CFG_CMD_IMLS)) +#endif + + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_BOOTDELAY -1 +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_IPADDR 192.168.0.21 +#define CONFIG_SERVERIP 192.168.0.250 +#define CONFIG_BOOTCOMMAND "bootm 80000" +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" +#define CONFIG_CMDLINE_TAG +#define CONFIG_TIMESTAMP + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* #define CFG_MMC_BASE 0xF0000000 */ + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa1000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */ +#define PHYS_SDRAM_3 0xa2000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */ +#define PHYS_SDRAM_4 0xa3000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */ + +#define CFG_DRAM_BASE 0xa0000000 /* at CS0 */ +#define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */ + +#undef CFG_SKIP_DRAM_SCRUB + +/* + * NAND Flash + */ +/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */ +#define CONFIG_NEW_NAND_CODE +#define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */ +#undef CFG_NAND1_BASE + +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 +#define NAND_DELAY_US 25 /* mk@tbd: could be 0, I guess */ + +/* nand timeout values */ +#define CFG_NAND_PROG_ERASE_TO 3000 +#define CFG_NAND_OTHER_TO 100 +#define CFG_NAND_SENDCMD_RETRY 3 +#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */ + +/* NAND Timing Parameters (in ns) */ +#define NAND_TIMING_tCH 10 +#define NAND_TIMING_tCS 0 +#define NAND_TIMING_tWH 20 +#define NAND_TIMING_tWP 40 + +#define NAND_TIMING_tRH 20 +#define NAND_TIMING_tRP 40 + +#define NAND_TIMING_tR 11123 +/* #define NAND_TIMING_tWHR 110 */ +#define NAND_TIMING_tWHR 100 +#define NAND_TIMING_tAR 10 + +/* NAND debugging */ +#define CFG_DFC_DEBUG1 /* usefull */ +#undef CFG_DFC_DEBUG2 /* noisy */ +#undef CFG_DFC_DEBUG3 /* extremly noisy */ + +#define CONFIG_MTD_DEBUG +#define CONFIG_MTD_DEBUG_VERBOSE 1 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NO_FLASH 1 +#ifndef CGF_NO_FLASH +/* these are required by the environment code */ +#define PHYS_FLASH_1 CFG_NAND0_BASE /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x04000000 /* 64 MB */ +#define PHYS_FLASH_BANK_SIZE 0x04000000 /* 64 MB Banks */ +#define PHYS_FLASH_SECT_SIZE (SECTORSIZE*1024) /* KB sectors (x2) */ +#endif + +/* + * GPIO settings + */ +#define CFG_GPSR0_VAL 0x00008000 +#define CFG_GPSR1_VAL 0x00FC0382 +#define CFG_GPSR2_VAL 0x0001FFFF +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPDR0_VAL 0x0060A800 +#define CFG_GPDR1_VAL 0x00FF0382 +#define CFG_GPDR2_VAL 0x0001C000 +#define CFG_GAFR0_L_VAL 0x98400000 +#define CFG_GAFR0_U_VAL 0x00002950 +#define CFG_GAFR1_L_VAL 0x000A9558 +#define CFG_GAFR1_U_VAL 0x0005AAAA +#define CFG_GAFR2_L_VAL 0xA0000000 +#define CFG_GAFR2_U_VAL 0x00000002 + +#define CFG_PSSR_VAL 0x20 + +/* + * Memory settings + */ +#define CFG_MSC0_VAL 0x23F223F2 +#define CFG_MSC1_VAL 0x3FF1A441 +#define CFG_MSC2_VAL 0x7FF97FF1 +#define CFG_MDCNFG_VAL 0x00001AC9 +#define CFG_MDREFR_VAL 0x00018018 +#define CFG_MDMRS_VAL 0x00000000 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000000 +#define CFG_MCMEM0_VAL 0x00010504 +#define CFG_MCMEM1_VAL 0x00010504 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00004715 +#define CFG_MCIO1_VAL 0x00004715 + +#define _LED 0x08000010 +#define LED_BLANK 0x08000040 + +/* + * FLASH and environment organization + */ +#ifndef CFG_NO_FLASH +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + + +/* NOTE: many default partitioning schemes assume the kernel starts at the + * second sector, not an environment. You have been warned! + */ +#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE +#endif /* #ifndef CFG_NO_FLASH */ + +/* #define CFG_ENV_IS_NOWHERE */ +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x40000 +#define CFG_ENV_SIZE 0x4000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/ezkit533.h b/include/configs/ezkit533.h new file mode 100644 index 0000000..5eda673 --- /dev/null +++ b/include/configs/ezkit533.h @@ -0,0 +1,188 @@ +#ifndef __CONFIG_EZKIT533_H__ +#define __CONFIG_EZKIT533_H__ + +#define CFG_LONGHELP 1 +#define CONFIG_BAUDRATE 57600 +#define CONFIG_STAMP 1 +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20310300 +#if 0 +#define CONFIG_MII +#define CFG_DISCOVER_PHY +#endif + +#define CONFIG_RTC_BF533 1 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 27000000 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 22 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC16M16A2TG_75 1 + +#define CONFIG_LOADS_ECHO 1 + + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DATE) +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off" + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01F00000 /* 1 ... 31 MB in DRAM */ +#define CFG_LOAD_ADDR 0x01000000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x02000000 +#define CFG_FLASH_BASE 0x20000000 + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_SIZE 0x4000 +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) + +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_FLASH0_BASE 0x20000000 +#define CFG_FLASH1_BASE 0x20200000 +#define CFG_FLASH2_BASE 0x20280000 +#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x20020000 +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ + +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 11 + + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#define POLL_MODE 1 +#define FLASH_TOT_SECT 40 +#define FLASH_SIZE 0x220000 +#define CFG_FLASH_SIZE 0x220000 + +/* + * Initialize PSD4256 registers for using I2C + */ +#define CONFIG_MISC_INIT_R + +/* + * I2C settings + * By default PF1 is used as SDA and PF0 as SCL on the Stamp board + */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +/* + * Software (bit-bang) I2C driver configuration + */ +#define PF_SCL PF0 +#define PF_SDA PF1 + +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE + + +#define __ADSPLPBLACKFIN__ 1 +#define __ADSPBF533__ 1 + +/* 0xFF, 0x7BB07BB0, 0x22547BB0 */ +/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ + ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) +#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ + B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) +*/ +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0x7BB07BB0 +#define AMBCTL1VAL 0xFFC27BB0 + +#define CONFIG_VDSP 1 + +#ifdef CONFIG_VDSP +#define ET_EXEC_VDSP 0x8 +#define SHT_STRTAB_VDSP 0x1 +#define ELFSHDRSIZE_VDSP 0x2C +#define VDSP_ENTRY_ADDR 0xFFA00000 +#endif + +#endif diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h index 6c08043..4f83b19 100644 --- a/include/configs/gw8260.h +++ b/include/configs/gw8260.h @@ -305,7 +305,6 @@ CFG_CMD_BEDBUG | \ CFG_CMD_ELF | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_REGINFO | \ CFG_CMD_IMMAP | \ CFG_CMD_MII) diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h new file mode 100644 index 0000000..d4dee3b --- /dev/null +++ b/include/configs/mcc200.h @@ -0,0 +1,281 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5200 +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MCC200 1 /* ... on MCC200 board */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ + +#define CONFIG_MISC_INIT_R + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CONFIG_MII 1 + +#define CONFIG_DOS_PARTITION + +/* USB */ +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define CONFIG_USB_STORAGE + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + ADD_USB_CMD | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=mcc200\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=/tftpboot/mcc200/uImage\0" \ + "baudrate=115200\0" \ + "load=tftp 200000 /tftpboot/mcc200/u-boot.bin\0" \ + "update=protect off FFF00000 +${filesize};" \ + "era FFF00000 +${filesize};" \ + "cp.b 200000 FFF00000 ${filesize}\0" \ + "serverip=192.168.1.1\0" \ + "ipaddr=192.168.133.144\0" \ + "netmask=255.255.0.0\0" \ + "unlock=yes\0" \ + "ethaddr=00:02:44:7D:73:3B\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#define CFG_PROMPT_HUSH_PS2 "> " + +/* + * IPB Bus clocking configuration. + */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x58 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* + * RTC configuration + */ +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + +/* + * Flash configuration (8,16 or 32 MB) + * TEXT base always at 0xFFF00000 + * ENV_ADDR always at 0xFFF40000 + * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!) + * 0xFE000000 for 32 MB + * 0xFF000000 for 16 MB + * 0xFF800000 for 8 MB + */ +#define CFG_FLASH_BASE 0xfc000000 +#define CFG_FLASH_SIZE 0x04000000 + +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ + +/* + * Memory map + */ +#define CFG_MBAR 0xf0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 1 + +/* + * GPIO configuration + */ +/* 0x10000004 = 32MB SDRAM */ +/* 0x90000004 = 64MB SDRAM */ +#define CFG_GPS_PORT_CONFIG 0x10000004 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x0004fb00 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00005000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/netstar.h b/include/configs/netstar.h new file mode 100644 index 0000000..697796a --- /dev/null +++ b/include/configs/netstar.h @@ -0,0 +1,265 @@ +/* + * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl + * + * Configuation settings for the TI OMAP NetStar board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/omap1510.h> + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP1510 1 /* which is in a 5910 */ + +/* Input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */ +#define CONFIG_XTAL_FREQ 12000000 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_MISC_INIT_R /* There is nothing to really init */ +#define BOARD_LATE_INIT /* but we flash the LEDs here */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CFG_DEVICE_NULLDEV 1 /* enable null device */ +#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +/* + * FLASH organization + */ +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MAX_FLASH_BANKS 1 +#if (PHYS_SDRAM_1_SIZE == SZ_32M) +/*#if 1*/ +#define CFG_FLASH_CFI /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER /* Use the common driver */ +#define CFG_FLASH_EMPTY_INFO +#define CFG_MAX_FLASH_SECT 128 +#else +#define PHYS_FLASH_1_SIZE SZ_1M +#define CFG_MAX_FLASH_SECT 19 +#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* in ticks */ +#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) +#endif + +#define CFG_MONITOR_BASE PHYS_FLASH_1 +#define CFG_MONITOR_LEN SZ_256K + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH +#define ENV_IS_SOLITARY +#define CFG_ENV_ADDR 0x4000 +#define CFG_ENV_SIZE SZ_8K +#define CFG_ENV_SECT_SIZE SZ_8K +#define CFG_ENV_ADDR_REDUND 0x6000 +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE +#define CONFIG_ENV_OVERWRITE + +/* + * Size of malloc() pool + */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +/* XXX #define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)*/ +#define CFG_MALLOC_LEN SZ_4M + +/* + * The stack size is set up in start.S using the settings below + */ +/* XXX #define CONFIG_STACKSIZE SZ_8K /XXX* regular stack */ +#define CONFIG_STACKSIZE SZ_1M /* regular stack */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC91111_BASE 0x04000300 + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */ +#define CFG_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */ + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*#define CONFIG_SKIP_RELOCATE_UBOOT*/ +/*#define CONFIG_SKIP_LOWLEVEL_INIT */ + +/* + * NAND flash + */ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE 0x04000000 + (2 << 23) + +/* + * JFFS2 partitions (mtdparts command line support) + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0" +#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)" + +#if 0 +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_BOOTD | \ + CFG_CMD_DHCP | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_LOADB | \ + CFG_CMD_NET | \ + CFG_CMD_MEMORY | \ + CFG_CMD_PING | \ + CFG_CMD_RUN) + +#else +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_BOOTD | \ + CFG_CMD_DHCP | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_NAND | \ + CFG_CMD_IMI | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_LOADB | \ + CFG_CMD_NET | \ + CFG_CMD_MEMORY | \ + CFG_CMD_PING | \ + CFG_CMD_RUN) + +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ +#endif + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +#define CONFIG_LOOPW + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ +#define CFG_AUTOLOAD "n" /* No autoload */ +#define CONFIG_BOOTCOMMAND "run nboot" +#define CONFIG_PREBOOT "run setup" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "setup=setenv bootargs console=ttyS0,$baudrate " \ + "$mtdparts\0" \ + "ospart=0\0" \ + "setpart=" \ + "if test -n $swapos; then " \ + "if test $ospart -eq 0; then chpart nand0,1; else chpart nand0,0; fi; "\ + "setenv swapos; saveenv; " \ + "else " \ + "chpart nand0,$ospart; " \ + "fi\0" \ + "nfsargs=setenv bootargs $bootargs " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ + "nfsroot=$rootpath root=/dev/nfs\0" \ + "flashargs=run setpart;setenv bootargs $bootargs " \ + "root=/dev/mtdblock$partition ro " \ + "rootfstype=jffs2\0" \ + "initrdargs=setenv bootargs $bootargs " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ + "iboot=bootp;run initrdargs;tftp;bootm\0" \ + "fboot=run flashargs;fsload /boot/uImage;bootm\0" \ + "nboot=bootp;run nfsargs;tftp;bootm\0" + +#if 0 /* feel free to disable for development */ +#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ +#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot in %d sec...\n" +#define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */ +#define CONFIG_BOOT_RETRY_TIME 30 +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "# " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE + +#define CFG_MEMTEST_START PHYS_SDRAM_1 +#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */ + +/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. + * This time is further subdivided by a local divisor. + */ +#define CFG_TIMERBASE OMAP1510_TIMER1_BASE +#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) + +#define OMAP5910_DPLL_DIV 1 +#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \ + (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) + +#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */ +#define OMAP5910_LCD_DIV 2 /* CKL/4 */ +#define OMAP5910_ARM_DIV 0 /* CKL/1 */ +#define OMAP5910_DSP_DIV 0 /* CKL/1 */ +#define OMAP5910_TC_DIV 1 /* CKL/2 */ +#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */ +#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */ + +#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */ +#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \ + (OMAP5910_LCD_DIV << 2) | \ + (OMAP5910_ARM_DIV << 4) | \ + (OMAP5910_DSP_DIV << 6) | \ + (OMAP5910_TC_DIV << 8) | \ + (OMAP5910_DSP_MMU_DIV << 10) | \ + (OMAP5910_ARM_TIM_SEL << 12)) + +#endif /* __CONFIG_H */ diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h index 75792221..d671dcc 100644 --- a/include/configs/ppmc8260.h +++ b/include/configs/ppmc8260.h @@ -279,7 +279,6 @@ #define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ CFG_CMD_ELF | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_REGINFO | \ CFG_CMD_MEMTEST | \ CFG_CMD_MII | \ diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 4e0cfdb..97b52fa 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -507,7 +507,6 @@ # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ CFG_CMD_ELF | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_I2C | \ CFG_CMD_SPI | \ CFG_CMD_SDRAM | \ @@ -520,7 +519,6 @@ # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ CFG_CMD_ELF | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_I2C | \ CFG_CMD_SPI | \ CFG_CMD_SDRAM | \ diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h index 180ce05..9cf0654 100644 --- a/include/configs/sbc8260.h +++ b/include/configs/sbc8260.h @@ -448,7 +448,6 @@ #ifdef CONFIG_ETHER_ON_FCC # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_IMMAP | \ @@ -459,7 +458,6 @@ #else # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_IMMAP | \ diff --git a/include/configs/stamp.h b/include/configs/stamp.h new file mode 100644 index 0000000..248ca70 --- /dev/null +++ b/include/configs/stamp.h @@ -0,0 +1,333 @@ +/* + * U-boot - stamp.h Configuration file for STAMP board + * having BF533 processor + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_STAMP_H__ +#define __CONFIG_STAMP_H__ + +/* + * Board settings + * + */ + +#define __ADSPLPBLACKFIN__ 1 +#define __ADSPBF533__ 1 +#define CONFIG_STAMP 1 +#define CONFIG_RTC_BF533 1 + +/* FLASH/ETHERNET uses the same address range */ +#define SHARED_RESOURCES 1 + +#define CONFIG_VDSP 1 + +/* + * Clock settings + * + */ + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 11059200 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 45 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 6 + +/* + * Network Settings + */ +/* network support */ +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME STAMP +#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs + +/* To remove hardcoding and enable MAC storage in EEPROM */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ + +/* + * Command settings + * + */ + +#define CFG_LONGHELP 1 + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ +#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DATE) +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot 0x1000000 linux;" \ + "run ramargs;run addip;bootelf\0" \ + "nfsboot=tftpboot 0x1000000 linux;" \ + "run nfsargs;run addip;bootelf\0" \ + "flashboot=bootm 0x20100000\0" \ + "" + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Console settings + * + */ + +#define CONFIG_BAUDRATE 57600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_PROMPT "stamp>" /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_LOADS_ECHO 1 + +/* + * Network settings + * + */ + +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20300300 +/* To remove hardcoding and enable MAC storage in EEPROM */ +/* #define HARDCODE_MAC 1 */ + +/* + * Flash settings + * + */ + +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET + +#define CFG_ENV_IS_IN_FLASH 1 + +#define CFG_FLASH_BASE 0x20000000 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_ENV_ADDR 0x20020000 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ + +#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ +#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ + +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 11 + +/* + * following timeouts shall be used once the + * Flash real protection is enabled + */ +#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ + +/* + * I2C settings + * By default PF2 is used as SDA and PF3 as SCL on the Stamp board + */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +/* + * Software (bit-bang) I2C driver configuration + */ +#define PF_SCL PF3 +#define PF_SDA PF2 + +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE + +/* + * Compact Flash settings + */ + +/* Enabled below option for CF support */ +/* #define CONFIG_STAMP_CF 1 */ + +#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE) + +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_DOS_PARTITION 1 + +/* + * IDE/ATA stuff + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0x20200000 +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ + +#define CFG_ATA_STRIDE 2 +#endif + +/* + * SDRAM settings + * + */ + +#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC64M4A2FB_7E 1 + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x07EFFFFF /* 1 ... 127 MB in DRAM */ +#define CFG_LOAD_ADDR 0x01000000 /* default load address */ + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x08000000 + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) + +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HZ 1000 /* 1ms time tick */ + +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_SIZE 0x4000 +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) + +#define CFG_LARGE_IMAGE_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ + +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +/* + * FLASH organization and environment definitions + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* 0xFF, 0xBBC3BBc3, 0x99B39983 */ +/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ + B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) +#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ + B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) +*/ +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0xBBC3BBC3 +#define AMBCTL1VAL 0x99B39983 +#define CF_AMBCTL1VAL 0x99B3ffc2 + +#ifdef CONFIG_VDSP +#define ET_EXEC_VDSP 0x8 +#define SHT_STRTAB_VDSP 0x1 +#define ELFSHDRSIZE_VDSP 0x2C +#define VDSP_ENTRY_ADDR 0xFFA00000 +#endif + +#endif diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h index 7118f3f..92ee8cb 100644 --- a/include/configs/svm_sc8xx.h +++ b/include/configs/svm_sc8xx.h @@ -141,6 +141,7 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY /* * Miscellaneous configurable options diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h index d312b65..e5d4397 100644 --- a/include/configs/utx8245.h +++ b/include/configs/utx8245.h @@ -91,7 +91,6 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}" | CFG_CMD_ENV | CFG_CMD_CONSOLE \ | CFG_CMD_LOADS | CFG_CMD_LOADB \ | CFG_CMD_IMI | CFG_CMD_CACHE \ - | CFG_CMD_RUN | CFG_CMD_ECHO \ | CFG_CMD_REGINFO | CFG_CMD_NET\ | CFG_CMD_DHCP | CFG_CMD_I2C \ | CFG_CMD_DATE) diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h new file mode 100644 index 0000000..4232d50 --- /dev/null +++ b/include/configs/zylonite.h @@ -0,0 +1,256 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * Configuation settings for the Zylonite board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ +#define CONFIG_ZYLONITE 1 /* Zylonite board */ + +/* #define CONFIG_LCD 1 */ +#ifdef CONFIG_LCD +#define CONFIG_SHARP_LM8V31 +#endif +/* #define CONFIG_MMC 1 */ +#define BOARD_LATE_INIT 1 + +#undef CONFIG_SKIP_RELOCATE_UBOOT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +#undef TURN_ON_ETHERNET +#ifdef TURN_ON_ETHERNET +# define CONFIG_DRIVER_SMC91111 1 +# define CONFIG_SMC91111_BASE 0x14000300 +# define CONFIG_SMC91111_EXT_PHY +# define CONFIG_SMC_USE_32_BIT +# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */ +#endif + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */ +#ifdef TURN_ON_ETHERNET +# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) +#else +# define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET) +#endif + + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_BOOTDELAY -1 +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_IPADDR 192.168.0.21 +#define CONFIG_SERVERIP 192.168.0.250 +#define CONFIG_BOOTCOMMAND "bootm 80000" +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" +#define CONFIG_CMDLINE_TAG +#define CONFIG_TIMESTAMP + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0x9c000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x9c400000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* #define CFG_MMC_BASE 0xF0000000 */ + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ +#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +#define FPGA_REGS_BASE_PHYSICAL 0x08000000 + +/* + * GPIO settings + */ +#define CFG_GPSR0_VAL 0x00008000 +#define CFG_GPSR1_VAL 0x00FC0382 +#define CFG_GPSR2_VAL 0x0001FFFF +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPDR0_VAL 0x0060A800 +#define CFG_GPDR1_VAL 0x00FF0382 +#define CFG_GPDR2_VAL 0x0001C000 +#define CFG_GAFR0_L_VAL 0x98400000 +#define CFG_GAFR0_U_VAL 0x00002950 +#define CFG_GAFR1_L_VAL 0x000A9558 +#define CFG_GAFR1_U_VAL 0x0005AAAA +#define CFG_GAFR2_L_VAL 0xA0000000 +#define CFG_GAFR2_U_VAL 0x00000002 + +#define CFG_PSSR_VAL 0x20 + +/* + * Memory settings + */ +#define CFG_MSC0_VAL 0x23F223F2 +#define CFG_MSC1_VAL 0x3FF1A441 +#define CFG_MSC2_VAL 0x7FF97FF1 +#define CFG_MDCNFG_VAL 0x00001AC9 +#define CFG_MDREFR_VAL 0x00018018 +#define CFG_MDMRS_VAL 0x00000000 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000000 +#define CFG_MCMEM0_VAL 0x00010504 +#define CFG_MCMEM1_VAL 0x00010504 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00004715 +#define CFG_MCIO1_VAL 0x00004715 + +#define _LED 0x08000010 +#define LED_BLANK 0x08000040 + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* NOTE: many default partitioning schemes assume the kernel starts at the + * second sector, not an environment. You have been warned! + */ +#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) +#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE +#define CFG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16) + + +/* + * FPGA Offsets + */ +#define WHOAMI_OFFSET 0x00 +#define HEXLED_OFFSET 0x10 +#define BLANKLED_OFFSET 0x40 +#define DISCRETELED_OFFSET 0x40 +#define CNFG_SWITCHES_OFFSET 0x50 +#define USER_SWITCHES_OFFSET 0x60 +#define MISC_WR_OFFSET 0x80 +#define MISC_RD_OFFSET 0x90 +#define INT_MASK_OFFSET 0xC0 +#define INT_CLEAR_OFFSET 0xD0 +#define GP_OFFSET 0x100 + +#endif /* __CONFIG_H */ |