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-rw-r--r--include/configs/MPC8569MDS.h3
-rw-r--r--include/configs/P1022DS.h1
-rw-r--r--include/configs/P1023RDS.h10
-rw-r--r--include/configs/P2020COME.h576
-rw-r--r--include/configs/P2041RDB.h21
-rw-r--r--include/configs/P3041DS.h1
-rw-r--r--include/configs/P3060QDS.h48
-rw-r--r--include/configs/P5020DS.h1
-rw-r--r--include/configs/PMC440.h2
-rw-r--r--include/configs/corenet_ds.h22
-rw-r--r--include/configs/eNET.h5
-rw-r--r--include/configs/io64.h566
-rw-r--r--include/configs/p1_p2_rdb_pc.h5
13 files changed, 1235 insertions, 26 deletions
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index ab27b98..7a5d86d 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -510,7 +510,8 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000
/*
* BOOTP options
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 1158fec..70d751d 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -345,7 +345,6 @@
/* SATA */
#define CONFIG_LIBATA
#define CONFIG_FSL_SATA
-#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h
index 013a6ac..e057b1f 100644
--- a/include/configs/P1023RDS.h
+++ b/include/configs/P1023RDS.h
@@ -526,12 +526,14 @@ extern unsigned long get_clock_freq(void);
#ifndef CONFIG_NAND
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
#else
-#define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000
#endif
-#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h
new file mode 100644
index 0000000..db88b68
--- /dev/null
+++ b/include/configs/P2020COME.h
@@ -0,0 +1,576 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* The P2020COME board is only booted via the Freescale On-Chip ROM */
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+
+#define CONFIG_SYS_TEXT_BASE 0xf8f80000
+#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD 1
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH 1
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
+#define CONFIG_P2020 1
+#define CONFIG_P2020COME 1
+#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
+#define CONFIG_MP
+
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#if defined(CONFIG_PCI)
+#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
+#define CONFIG_PCIE3 1 /* PCIE controller 3 (slot 3) */
+
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
+#endif /* #if defined(CONFIG_PCI) */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_PCI)
+#define CONFIG_E1000 1 /* E1000 pci Ethernet card */
+#endif
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+
+/*
+ * For P2020COME DDRCLK and SYSCLK are from the same oscillator
+ * For DA phase the SYSCLK is 66MHz
+ * For EA phase the SYSCLK is 100MHz
+ */
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
+
+#define CONFIG_HWCONFIG
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch prediction */
+
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x1fffffff
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+
+
+
+
+
+
+ /*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE (512 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR \
+ + CONFIG_SYS_L2_SIZE)
+
+#define CONFIG_SYS_CCSRBAR 0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+
+#define CONFIG_SYS_SDRAM_SIZE 2048ULL /* DDR size on P2020COME */
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+
+#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
+#define CONFIG_SYS_DDR_SBE 0x00ff0000
+
+#define CONFIG_SYS_SPD_BUS_NUM 1
+#define SPD_EEPROM_ADDRESS 0x53
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x7fff_ffff DDR3 2G Cacheable
+ * 0x8000_0000 0x9fff_ffff PCI Express 3 Mem 1G non-cacheable
+ * 0xa000_0000 0xbfff_ffff PCI Express 2 Mem 1G non-cacheable
+ * 0xc000_0000 0xdfff_ffff PCI Express 1 Mem 1G non-cacheable
+ * 0xffc1_0000 0xffc1_ffff PCI Express 3 IO 64K non-cacheable
+ * 0xffc2_0000 0xffc2_ffff PCI Express 2 IO 64K non-cacheable
+ * 0xffc3_0000 0xffc3_ffff PCI Express 1 IO 64K non-cacheable
+ *
+ * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
+ * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+
+/* There is no NOR Flash on P2020COME */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* the assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+ - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+/* new uImage format support */
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+
+/* I2C */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR2 0x18
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#if defined(CONFIG_PCI)
+
+/* controller 3, Slot 3, tgtid 3, Base address 8000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc10000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc10000
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#undef CONFIG_RTL8139
+
+#ifdef CONFIG_RTL8139
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x) (x)
+#define _IO_BASE 0x00000000
+#endif
+
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
+
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 2
+#define TSEC3_PHY_ADDR 1
+
+#undef CONFIG_VSC7385_ENET
+
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_RAMBOOT_SDCARD)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_SIZE 0x2000
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+ #define CONFIG_ENV_IS_IN_SPI_FLASH
+ #define CONFIG_ENV_SPI_BUS 0
+ #define CONFIG_ENV_SPI_CS 0
+ #define CONFIG_ENV_SPI_MAX_HZ 10000000
+ #define CONFIG_ENV_SPI_MODE 0
+ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+ #define CONFIG_ENV_SECT_SIZE 0x10000
+ #define CONFIG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#endif
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_MMC 1
+
+#ifdef CONFIG_MMC
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#endif /* CONFIG_MMC */
+
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Misc Extra Settings */
+#define CONFIG_SYS_64BIT_VSPRINTF 1
+#define CONFIG_SYS_64BIT_STRTOUL 1
+#define CONFIG_CMD_DHCP 1
+
+#define CONFIG_CMD_DATE 1
+#define CONFIG_RTC_M41T62 1
+#define CONFIG_SYS_RTC_BUS_NUM 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+ /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
+
+#define CONFIG_HOSTNAME unknown
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH u-boot.bin
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ecc=on\0" \
+ "bootcmd=run sdboot\0" \
+ "sdboot=setenv bootargs root=/dev/mmcblk0p2 rw " \
+ "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
+ "$othbootargs; mmcinfo; " \
+ "ext2load mmc 0:2 $loadaddr /boot/$bootfile; " \
+ "ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; " \
+ "bootm $loadaddr - $fdtaddr\0" \
+ "sdfatboot=setenv bootargs root=/dev/ram rw " \
+ "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
+ "$othbootargs; mmcinfo; " \
+ "fatload mmc 0:1 $loadaddr $bootfile; " \
+ "fatload mmc 0:1 $fdtaddr $fdtfile; " \
+ "fatload mmc 0:1 $ramdiskaddr $ramdiskfile; " \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
+ "usbboot=setenv bootargs root=/dev/sda1 rw " \
+ "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
+ "$othbootargs; " \
+ "usb start; " \
+ "ext2load usb 0:1 $loadaddr /boot/$bootfile; " \
+ "ext2load usb 0:1 $fdtaddr /boot/$fdtfile; " \
+ "bootm $loadaddr - $fdtaddr\0" \
+ "usbfatboot=setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs; " \
+ "usb start; " \
+ "fatload usb 0:2 $loadaddr $bootfile; " \
+ "fatload usb 0:2 $fdtaddr $fdtfile; " \
+ "fatload usb 0:2 $ramdiskaddr $ramdiskfile; " \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
+ "usbext2boot=setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs; " \
+ "usb start; " \
+ "ext2load usb 0:4 $loadaddr $bootfile; " \
+ "ext2load usb 0:4 $fdtaddr $fdtfile; " \
+ "ext2load usb 0:4 $ramdiskaddr $ramdiskfile; " \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
+ "upgradespi=sf probe 0; " \
+ "setenv startaddr 0; " \
+ "setenv erasesize a0000; " \
+ "tftp 1000000 $tftppath/$uboot_spi; " \
+ "sf erase $startaddr $erasesize; " \
+ "sf write 1000000 $startaddr $filesize; " \
+ "sf erase 100000 120000\0" \
+ "clearspienv=sf probe 0;sf erase 100000 20000\0" \
+ "othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0" \
+ "netdev=eth0\0" \
+ "rootdelaysecond=15\0" \
+ "uboot_nor=u-boot-nor.bin\0" \
+ "uboot_spi=u-boot-p2020.spi\0" \
+ "uboot_sd=u-boot-p2020.bin\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=rootfs-dev.ext2.img\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=uImage-2.6.32-p2020.dtb\0" \
+ "tftppath=p2020\0"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "usb start;" \
+ "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
+ "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $tftppath/$bootfile;" \
+ "tftp $fdtaddr $tftppath/$fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $tftppath/$ramdiskfile;" \
+ "tftp $loadaddr $tftppath/$bootfile;" \
+ "tftp $fdtaddr $tftppath/$fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 6d45bb1..a48055e 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -414,21 +414,25 @@ unsigned long get_board_sys_clk(unsigned long dummy);
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
* about 545KB (1089 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
*/
-#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
#endif
-#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
@@ -446,10 +450,9 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#endif /* CONFIG_PCI */
/* SATA */
-#define CONFIG_FSL_SATA_V2
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
#define CONFIG_FSL_SATA
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LIBATA
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
index 57d5de5..98e7a42 100644
--- a/include/configs/P3041DS.h
+++ b/include/configs/P3041DS.h
@@ -32,7 +32,6 @@
#define CONFIG_MMC
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#define CONFIG_SYS_DPAA_RMAN
diff --git a/include/configs/P3060QDS.h b/include/configs/P3060QDS.h
new file mode 100644
index 0000000..8006547
--- /dev/null
+++ b/include/configs/P3060QDS.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * P3060 QDS board configuration file
+ */
+#define CONFIG_P3060QDS
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P3060
+#define CONFIG_FSL_QIXIS
+
+#define CONFIG_NAND_FSL_ELBC
+
+#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
+
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_SPI_FLASH_SST
+
+#include "corenet_ds.h"
+
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+
+/* There is a PCA9547 8-channel I2C-bus multiplexer on P3060QDS board */
+#define CONFIG_I2C_MUX
+#define CONFIG_I2C_MULTI_BUS
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
index a9cee23..4afc4f1 100644
--- a/include/configs/P5020DS.h
+++ b/include/configs/P5020DS.h
@@ -32,7 +32,6 @@
#define CONFIG_MMC
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#define CONFIG_SYS_FSL_RAID_ENGINE
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index bee74aa..ed47a87 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -432,6 +432,8 @@
#define CONFIG_SYS_PCI_MASTER_INIT
#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
+#define CONFIG_PCI_BOOTDELAY 0
+
/* PCI identification */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index bc0aeeb..7925b95 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -168,7 +168,11 @@
#define CONFIG_DDR_SPD
#define CONFIG_FSL_DDR3
+#ifdef CONFIG_P3060QDS
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#else
#define CONFIG_SYS_SPD_BUS_NUM 1
+#endif
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
@@ -474,21 +478,25 @@
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
* about 545KB (1089 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
*/
-#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130)
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
#endif
-#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
@@ -637,7 +645,7 @@
#define CONFIG_BAUDRATE 115200
-#if defined(CONFIG_P4080DS)
+#if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS)
#define __USB_PHY_TYPE ulpi
#else
#define __USB_PHY_TYPE utmi
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index 70c74f6..d5c9cad 100644
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -105,6 +105,7 @@
#define CONFIG_CMD_SETGETDCR
#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_XIMG
+#define CONFIG_CMD_ZBOOT
#define CONFIG_BOOTDELAY 15
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
@@ -153,6 +154,10 @@
#undef CONFIG_SYS_GENERIC_TIMER
#define CONFIG_SYS_PCAT_INTERRUPTS
#define CONFIG_SYS_NUM_IRQS 16
+#define CONFIG_SYS_PC_BIOS
+#define CONFIG_SYS_PCI_BIOS
+#define CONFIG_SYS_X86_REALMODE
+#define CONFIG_SYS_X86_ISR_TIMER
/*-----------------------------------------------------------------------
* Memory organization:
diff --git a/include/configs/io64.h b/include/configs/io64.h
new file mode 100644
index 0000000..51b2dd1
--- /dev/null
+++ b/include/configs/io64.h
@@ -0,0 +1,566 @@
+/*
+ * (C) Copyright 2011
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * based on kilauea.h
+ * by Stefan Roese, DENX Software Engineering, sr@denx.de.
+ * and Grant Erickson <gerickson@nuovations.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * io64.h - configuration for Guntermann & Drunck Io64 (405EX)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_IO64 1 /* Board is Io64 */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405EX 1 /* Specifc 405EX support*/
+#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
+#endif
+
+/*
+ * CHIP_21 errata
+ */
+#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME io64
+#define CONFIG_IDENT_STRING " io64 0.01"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
+#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE 0xFC000000
+#define CONFIG_SYS_NVRAM_BASE 0xF0000000
+#define CONFIG_SYS_FPGA0_BASE 0xF0100000
+#define CONFIG_SYS_FPGA1_BASE 0xF0108000
+#define CONFIG_SYS_LATCH_BASE 0xF0200000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & Stack Pointer Configuration Options
+ *
+ * There are traditionally three options for the primordial
+ * (i.e. initial) stack usage on the 405-series:
+ *
+ * 1) On-chip Memory (OCM) (i.e. SRAM)
+ * 2) Data cache
+ * 3) SDRAM
+ *
+ * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
+ * the latter of which is less than desireable since it requires
+ * setting up the SDRAM and ECC in assembly code.
+ *
+ * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
+ * select on the External Bus Controller (EBC) and then select a
+ * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
+ * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
+ * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
+ * physical SDRAM to use (3).
+ *-----------------------------------------------------------------------*/
+
+#define CONFIG_SYS_INIT_DCACHE_CS 4
+
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+#define CONFIG_SYS_INIT_RAM_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + (1 << 30)) /* 1 GiB */
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
+
+#define CONFIG_SYS_INIT_RAM_SIZE \
+ (4 << 10) /* 4 KiB */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * If the data cache is being used for the primordial stack and global
+ * data area, the POST word must be placed somewhere else. The General
+ * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
+ * its compare and mask register contents across reset, so it is used
+ * for the POST word.
+ */
+
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+# define CONFIG_SYS_POST_WORD_ADDR \
+ (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
+#else
+# define CONFIG_SYS_INIT_EXTRA_SIZE 16
+# define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
+# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX 1 /* Use UART0 */
+#define CONFIG_SYS_BASE_BAUD 691200
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/* Gbit PHYs */
+#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
+
+#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 12) /* MDIO is GPIO12 */
+#define CONFIG_SYS_MDC_PIN (0x80000000 >> 13) /* MDC is GPIO13 */
+
+#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy0"
+
+#define CONFIG_SYS_MDIO1_PIN (0x80000000 >> 2) /* MDIO is GPIO2 */
+#define CONFIG_SYS_MDC1_PIN (0x80000000 >> 3) /* MDC is GPIO3 */
+
+#define CONFIG_SYS_GBIT_MII1_BUSNAME "io_miiphy1"
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MBYTES_SDRAM (128) /* 128MB */
+
+/*
+ * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
+ *
+ * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
+ * SDRAM Controller DDR autocalibration values and takes a lot longer
+ * to run than Method_B.
+ * (See the Method_A and Method_B algorithm discription in the file:
+ * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
+ * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
+ *
+ * DDR Autocalibration Method_B is the default.
+ */
+#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION
+#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION
+#undef CONFIG_PPC4xx_DDR_METHOD_A
+
+#define CONFIG_SYS_SDRAM0_MB0CF_BASE ((0 << 20) + CONFIG_SYS_SDRAM_BASE)
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
+ SDRAM_RXBAS_SDSZ_128MB | \
+ SDRAM_RXBAS_SDAM_MODE2 | \
+ SDRAM_RXBAS_SDBE_ENABLE)
+#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
+ SDRAM_MCOPT1_4_BANKS | \
+ SDRAM_MCOPT1_DDR2_TYPE | \
+ SDRAM_MCOPT1_QDEP | \
+ SDRAM_MCOPT1_DCOO_DISABLED)
+#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
+#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
+ SDRAM_MODT_EB0R_ENABLE)
+#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
+#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
+ SDRAM_CODT_CKLZ_36OHM | \
+ SDRAM_CODT_DQS_1_8_V_DDR2 | \
+ SDRAM_CODT_IO_NMODE)
+#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
+#define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(80) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
+#define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(3) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
+#define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
+ SDRAM_INITPLR_IMA_ENCODE(0))
+#define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
+ JEDEC_MA_EMR_RTT_75OHM))
+#define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+ JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
+ JEDEC_MA_MR_BLEN_4 | \
+ JEDEC_MA_MR_DLL_RESET))
+#define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(3) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
+ SDRAM_INITPLR_IBA_ENCODE(0x0) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(26) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+ JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
+ JEDEC_MA_MR_BLEN_4))
+#define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
+ JEDEC_MA_EMR_RDQS_DISABLE | \
+ JEDEC_MA_EMR_DQS_DISABLE | \
+ JEDEC_MA_EMR_RTT_DISABLED | \
+ JEDEC_MA_EMR_ODS_NORMAL))
+#define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
+ SDRAM_INITPLR_IMWT_ENCODE(2) | \
+ SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+ SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
+ SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
+ JEDEC_MA_EMR_RDQS_DISABLE | \
+ JEDEC_MA_EMR_DQS_DISABLE | \
+ JEDEC_MA_EMR_RTT_DISABLED | \
+ JEDEC_MA_EMR_ODS_NORMAL))
+#define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
+#define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
+#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
+ SDRAM_RQDC_RQFD_ENCODE(56))
+#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
+#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
+#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
+ SDRAM_DLCR_DLCS_CONT_DONE | \
+ SDRAM_DLCR_DLCV_ENCODE(165))
+#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
+#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
+#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
+ SDRAM_SDTR1_RTW_2_CLK | \
+ SDRAM_SDTR1_WTWO_1_CLK | \
+ SDRAM_SDTR1_RTRO_1_CLK)
+#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
+ SDRAM_SDTR2_WTR_2_CLK | \
+ SDRAM_SDTR2_XSNR_32_CLK | \
+ SDRAM_SDTR2_WPC_4_CLK | \
+ SDRAM_SDTR2_RPC_2_CLK | \
+ SDRAM_SDTR2_RP_3_CLK | \
+ SDRAM_SDTR2_RRD_2_CLK)
+#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \
+ SDRAM_SDTR3_RC_ENCODE(12) | \
+ SDRAM_SDTR3_XCS | \
+ SDRAM_SDTR3_RFC_ENCODE(21))
+#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
+ SDRAM_MMODE_DCL_DDR2_5_0_CLK | \
+ SDRAM_MMODE_BLEN_4)
+#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
+ SDRAM_MEMODE_RTT_75OHM)
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+
+#define CONFIG_PCA9698 1 /* NXP PCA9698 */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
+
+/* Temp sensor/hwmon/dtt */
+#define CONFIG_DTT_LM63 1 /* National LM63 */
+#define CONFIG_DTT_SENSORS { 0x18, 0x4c, 0x4e } /* Sensor addresses */
+#define CONFIG_DTT_PWM_LOOKUPTABLE \
+ { { 40, 10 }, { 43, 13 }, { 46, 16 }, \
+ { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT 0xa10
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+#define CONFIG_M88E1111_PHY 1
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
+#define CONFIG_PHY_ADDR 0x12 /* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0 1
+
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 0x13
+
+/* Debug messages for the DDR autocalibration */
+#define CONFIG_AUTOCALIB "silent\0"
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_PPC_OLD \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ "logversion=2\0" \
+ "kernel_addr=fc000000\0" \
+ "fdt_addr=fc1e0000\0" \
+ "ramdisk_addr=fc200000\0" \
+ "pciconfighost=1\0" \
+ "pcie_mode=RP:RP\0" \
+ ""
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CHIP_CONFIG
+#define CONFIG_CMD_DTT
+
+#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
+
+/* POST support */
+#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
+ CONFIG_SYS_POST_CPU | \
+ CONFIG_SYS_POST_ETHER | \
+ CONFIG_SYS_POST_I2C | \
+ CONFIG_SYS_POST_MEMORY_ON | \
+ CONFIG_SYS_POST_UART)
+
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
+ CONFIG_SYS_NS16550_COM2 }
+
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+
+/* Memory Bank 0 (NOR-flash) */
+#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(11) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(0) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(2) | \
+ EBC_BXAP_TH_ENCODE(2) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
+ EBC_BXCR_BS_64MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 1 (NVRAM/Uart) */
+#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_ENABLED | \
+ EBC_BXAP_FWT_ENCODE(8) | \
+ EBC_BXAP_BWT_ENCODE(4) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(1) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(2) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_8BIT)
+
+/* Memory Bank 2 (FPGA) */
+#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(5) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(2) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(0) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 3 (Latches) */
+#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
+ EBC_BXAP_FWT_ENCODE(8) | \
+ EBC_BXAP_BWT_ENCODE(4) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(1) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(2) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* EBC peripherals */
+
+#define CONFIG_SYS_FPGA_BASE(k) \
+ (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
+
+#define CONFIG_SYS_FPGA_DONE(k) \
+ (k ? 0x0040 : 0x0080)
+
+#define CONFIG_SYS_FPGA_COUNT 2
+
+#define CONFIG_SYS_LATCH0_RESET 0xffff
+#define CONFIG_SYS_LATCH0_BOOT 0xffff
+#define CONFIG_SYS_LATCH1_RESET 0xffbf
+#define CONFIG_SYS_LATCH1_BOOT 0xffff
+
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO */ \
+{ \
+/* GPIO Core 0 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO0 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO3 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO6 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO8 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO9 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO10 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO11 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO12 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO13 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO14 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO15 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO16 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO17 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO18 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO19 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO20 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO21 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO22 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO23 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO24 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_0 }, /* GPIO25 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO26 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO27 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO28 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO29 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO30 */ \
+{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO31 */ \
+} \
+}
+
+#define CONFIG_SYS_GPIO_STARTUP_FINISHED 15
+#define CONFIG_SYS_GPIO_STARTUP_FINISHED_N 14
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 5a69902..8e8fa16 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -677,8 +677,9 @@
#ifdef CONFIG_QE
/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
-#define CONFIG_SYS_QE_FW_LENGTH 0x10000
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#endif /* CONFIG_QE */
#ifdef CONFIG_P1025RDB
generated by cgit v1.1 at 2024-12-23 16:14:39 +0000