diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/TQM823L.h | 38 | ||||
| -rw-r--r-- | include/configs/TQM823M.h | 38 | ||||
| -rw-r--r-- | include/configs/TQM850L.h | 38 | ||||
| -rw-r--r-- | include/configs/TQM850M.h | 38 | ||||
| -rw-r--r-- | include/configs/TQM855L.h | 38 | ||||
| -rw-r--r-- | include/configs/TQM855M.h | 38 | ||||
| -rw-r--r-- | include/configs/TQM860L.h | 38 | ||||
| -rw-r--r-- | include/configs/TQM860M.h | 38 | ||||
| -rw-r--r-- | include/configs/TQM862L.h | 46 | ||||
| -rw-r--r-- | include/configs/TQM862M.h | 46 |
10 files changed, 40 insertions, 356 deletions
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index c12f000..b1aced0 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -262,15 +262,8 @@ *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else /* up to 66 MHz we use a 1:1 clock */ #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -279,17 +272,9 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 66 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * PCMCIA stuff @@ -358,19 +343,8 @@ /* * FLASH timing: */ -#if defined(CONFIG_80MHz) -/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -#elif defined(CONFIG_66MHz) -/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_3_CLK | OR_EHTR | OR_BI) -#else /* 50 MHz */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -431,13 +405,9 @@ * 66 Mhz => 66.000.000 / Divider = 129 * 80 Mhz => 80.000.000 / Divider = 156 */ -#if defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 /* * For 16 MBit, refresh rates could be 31.3 us diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 7ca9153..0c2dbec 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -254,15 +254,8 @@ *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else /* up to 66 MHz we use a 1:1 clock */ #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -271,17 +264,9 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 66 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * PCMCIA stuff @@ -350,19 +335,8 @@ /* * FLASH timing: */ -#if defined(CONFIG_80MHz) -/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -#elif defined(CONFIG_66MHz) -/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_3_CLK | OR_EHTR | OR_BI) -#else /* 50 MHz */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -423,13 +397,9 @@ * 66 Mhz => 66.000.000 / Divider = 129 * 80 Mhz => 80.000.000 / Divider = 156 */ -#if defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 /* * For 16 MBit, refresh rates could be 31.3 us diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 2952447..d6784c8 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -245,15 +245,8 @@ *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else /* up to 66 MHz we use a 1:1 clock */ #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -262,17 +255,9 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 66 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * PCMCIA stuff @@ -341,19 +326,8 @@ /* * FLASH timing: */ -#if defined(CONFIG_80MHz) -/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -#elif defined(CONFIG_66MHz) -/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_3_CLK | OR_EHTR | OR_BI) -#else /* 50 MHz */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -414,13 +388,9 @@ * 66 Mhz => 66.000.000 / Divider = 129 * 80 Mhz => 80.000.000 / Divider = 156 */ -#if defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 /* * For 16 MBit, refresh rates could be 31.3 us diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index d565300..e825ac9 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -244,15 +244,8 @@ *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else /* up to 66 MHz we use a 1:1 clock */ #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -261,17 +254,9 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 66 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * PCMCIA stuff @@ -340,19 +325,8 @@ /* * FLASH timing: */ -#if defined(CONFIG_80MHz) -/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -#elif defined(CONFIG_66MHz) -/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_3_CLK | OR_EHTR | OR_BI) -#else /* 50 MHz */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -413,13 +387,9 @@ * 66 Mhz => 66.000.000 / Divider = 129 * 80 Mhz => 80.000.000 / Divider = 156 */ -#if defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 /* * For 16 MBit, refresh rates could be 31.3 us diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 2608119..9c06d48 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -248,15 +248,8 @@ *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else /* up to 66 MHz we use a 1:1 clock */ #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -265,17 +258,9 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 66 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * PCMCIA stuff @@ -344,19 +329,8 @@ /* * FLASH timing: */ -#if defined(CONFIG_80MHz) -/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -#elif defined(CONFIG_66MHz) -/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_3_CLK | OR_EHTR | OR_BI) -#else /* 50 MHz */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -417,13 +391,9 @@ * 66 Mhz => 66.000.000 / Divider = 129 * 80 Mhz => 80.000.000 / Divider = 156 */ -#if defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 /* * For 16 MBit, refresh rates could be 31.3 us diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index cb4a16a..82a855b 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -283,15 +283,8 @@ *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else /* up to 66 MHz we use a 1:1 clock */ #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -300,17 +293,9 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 66 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * PCMCIA stuff @@ -379,19 +364,8 @@ /* * FLASH timing: */ -#if defined(CONFIG_80MHz) -/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -#elif defined(CONFIG_66MHz) -/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_3_CLK | OR_EHTR | OR_BI) -#else /* 50 MHz */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -452,13 +426,9 @@ * 66 Mhz => 66.000.000 / Divider = 129 * 80 Mhz => 80.000.000 / Divider = 156 */ -#if defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 /* * For 16 MBit, refresh rates could be 31.3 us diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index ba2198f..adac808 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -249,15 +249,8 @@ *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else /* up to 66 MHz we use a 1:1 clock */ #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -266,17 +259,9 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 66 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * PCMCIA stuff @@ -345,19 +330,8 @@ /* * FLASH timing: */ -#if defined(CONFIG_80MHz) -/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -#elif defined(CONFIG_66MHz) -/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_3_CLK | OR_EHTR | OR_BI) -#else /* 50 MHz */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -418,13 +392,9 @@ * 66 Mhz => 66.000.000 / Divider = 129 * 80 Mhz => 80.000.000 / Divider = 156 */ -#if defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 /* * For 16 MBit, refresh rates could be 31.3 us diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 3f6edb8..1e9abc8 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -250,15 +250,8 @@ *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else /* up to 66 MHz we use a 1:1 clock */ #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -267,17 +260,9 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 66 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) -#endif /* CONFIG_80MHz */ /*----------------------------------------------------------------------- * PCMCIA stuff @@ -346,19 +331,8 @@ /* * FLASH timing: */ -#if defined(CONFIG_80MHz) -/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -#elif defined(CONFIG_66MHz) -/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_3_CLK | OR_EHTR | OR_BI) -#else /* 50 MHz */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -419,13 +393,9 @@ * 66 Mhz => 66.000.000 / Divider = 129 * 80 Mhz => 80.000.000 / Divider = 156 */ -#if defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 /* * For 16 MBit, refresh rates could be 31.3 us diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index 84570c1..595d4a2 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -252,16 +252,8 @@ *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit - * - * If this is a 80 MHz or 100 MHz CPU, - * set PLL multiplication factor to 5 (5 * 16 = 80, 5 * 20 = 100) */ -#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) -#define CFG_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else /* up to 66 MHz we use a 1:1 clock */ #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CONFIG_80MHz | CONFIG_100MHz */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -270,17 +262,9 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) /* use 16/20 MHz * 5 */ -#define CFG_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 66 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) -#endif /* CONFIG_80MHz | CONFIG_100MHz */ /*----------------------------------------------------------------------- * PCMCIA stuff @@ -349,24 +333,8 @@ /* * FLASH timing: */ -#if defined(CONFIG_100MHz) -/* 100 MHz CPU - 50 MHz bus: - * ACS = 01, TRLX = 0, CSNT = 0, SCY = 7, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV4 | OR_SCY_7_CLK | OR_BI) -#elif defined(CONFIG_80MHz) -/* 80 MHz CPU - 40 MHz bus: - * ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -#elif defined(CONFIG_66MHz) -/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_3_CLK | OR_EHTR | OR_BI) -#else /* 50 MHz */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -428,15 +396,9 @@ * 80 Mhz => 80.000.000 / Divider = 156 * 100 Mhz => 100.000.000 / Divider = 195 */ -#if defined(CONFIG_100MHz) -#define CFG_MAMR_PTA 195 -#elif defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 /* * For 16 MBit, refresh rates could be 31.3 us diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 914e28a..7ab8559 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -253,16 +253,8 @@ *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit - * - * If this is a 80 MHz or 100 MHz CPU, - * set PLL multiplication factor to 5 (5 * 16 = 80, 5 * 20 = 100) */ -#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) -#define CFG_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else /* up to 66 MHz we use a 1:1 clock */ #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CONFIG_80MHz | CONFIG_100MHz */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -271,17 +263,9 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) /* use 16/20 MHz * 5 */ -#define CFG_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 66 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) -#endif /* CONFIG_80MHz | CONFIG_100MHz */ /*----------------------------------------------------------------------- * PCMCIA stuff @@ -350,24 +334,8 @@ /* * FLASH timing: */ -#if defined(CONFIG_100MHz) -/* 100 MHz CPU - 50 MHz bus: - * ACS = 01, TRLX = 0, CSNT = 0, SCY = 7, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV4 | OR_SCY_7_CLK | OR_BI) -#elif defined(CONFIG_80MHz) -/* 80 MHz CPU - 40 MHz bus: - * ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -#elif defined(CONFIG_66MHz) -/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_3_CLK | OR_EHTR | OR_BI) -#else /* 50 MHz */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -429,15 +397,9 @@ * 80 Mhz => 80.000.000 / Divider = 156 * 100 Mhz => 100.000.000 / Divider = 195 */ -#if defined(CONFIG_100MHz) -#define CFG_MAMR_PTA 195 -#elif defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 /* * For 16 MBit, refresh rates could be 31.3 us |