diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/ASH405.h | 2 | ||||
| -rw-r--r-- | include/configs/BUBINGA405EP.h | 4 | ||||
| -rw-r--r-- | include/configs/MPC8266ADS.h | 44 | ||||
| -rw-r--r-- | include/configs/SXNI855T.h | 47 | ||||
| -rw-r--r-- | include/configs/sc520_cdp.h | 78 | ||||
| -rw-r--r-- | include/configs/sc520_spunk.h | 212 | ||||
| -rw-r--r-- | include/configs/sc520_spunk_rel.h | 32 | ||||
| -rw-r--r-- | include/configs/utx8245.h | 191 |
8 files changed, 499 insertions, 111 deletions
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 398bf76..5468fe2 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -279,7 +279,7 @@ /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x92015480 -//#define CFG_EBC_PB0AP 0x08055880 /* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ +/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ diff --git a/include/configs/BUBINGA405EP.h b/include/configs/BUBINGA405EP.h index 176a84a..f776a32 100644 --- a/include/configs/BUBINGA405EP.h +++ b/include/configs/BUBINGA405EP.h @@ -29,7 +29,7 @@ #define __CONFIG_H /* Debug options */ -//#define __DEBUG_START_FROM_SRAM__ +/*#define __DEBUG_START_FROM_SRAM__ */ @@ -259,7 +259,7 @@ #endif -//#define CFG_MONITOR_LEN (200 * 1024) /* Reserve 200 kB for Monitor */ +/*#define CFG_MONITOR_LEN (200 * 1024) /XXX* Reserve 200 kB for Monitor */ #define CFG_MONITOR_LEN (192 * 1024) /* Reserve 200 kB for Monitor */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index e0159a2..414d515 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -27,7 +27,18 @@ */ /* - * Config header file for a MPC8260ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm + * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm + */ + +/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + !! !! + !! This configuration requires JP3 to be in position 1-2 to work !! + !! To make it work for the default, the TEXT_BASE define in !! + !! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !! + !! 0xfff00000 !! + !! The CFG_HRCW_MASTER define below must also be changed to match !! + !! !! + !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */ #ifndef __CONFIG_H @@ -375,6 +386,7 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */ /* 0x0EB2B645 */ #define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\ ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 ) |\ @@ -382,8 +394,10 @@ ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ ) +/* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3) */ +/* #define CFG_HRCW_MASTER 0x0cb23645 */ -/* This value should actually be situated in the first 256 bytes of the FLASH +/* This value should actually be situated in the first 256 bytes of the FLASH which on the standard MPC8266ADS board is at address 0xFF800000 The linker script places it at 0xFFF00000 instead. @@ -395,8 +409,7 @@ - Rune - */ -/* #define CFG_HRCW_MASTER 0x0cb23645 */ +*/ /* no slaves */ #define CFG_HRCW_SLAVE1 0 @@ -436,7 +449,24 @@ #endif -#define CFG_HID0_INIT 0 +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +/*#define CFG_HID0_INIT 0 */ +#define CFG_HID0_INIT (HID0_ICE |\ + HID0_DCE |\ + HID0_ICFI |\ + HID0_DCI |\ + HID0_IFEM |\ + HID0_ABE) + #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) #define CFG_HID2 0 @@ -519,7 +549,7 @@ #define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ #define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ -#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL +#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL #define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ #define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) @@ -530,7 +560,7 @@ */ #define CFG_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */ -#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ +#define CFG_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */ #define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL #define CFG_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */ #define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO) diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h index a7f0c21..bdaf683 100644 --- a/include/configs/SXNI855T.h +++ b/include/configs/SXNI855T.h @@ -143,11 +143,52 @@ #define CFG_DISCOVER_PHY -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_EEPROM | CFG_CMD_DATE) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_NAND | \ + CFG_CMD_DATE) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +/* NAND flash support */ +#define CONFIG_MTD_NAND_ECC_JFFS2 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +/* DFBUSY is available on Port C, bit 12; 0 if busy */ +#define NAND_WAIT_READY(nand) \ + while (!(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x0008)); +#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr)) +#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr)) +#define WRITE_NAND(d, adr) \ + do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0) +#define READ_NAND(adr) (*(volatile uint8_t *)(adr)) +#define CLE_LO 0x01 /* 0 selects CLE mode (CLE high) */ +#define ALE_LO 0x02 /* 0 selects ALE mode (ALE high) */ +#define CE_LO 0x04 /* 1 selects chip (CE low) */ +#define nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0) +#define NAND_DISABLE_CE(nand) \ + nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO) +#define NAND_ENABLE_CE(nand) \ + nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO) +#define NAND_CTL_CLRALE(nandptr) \ + nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO) +#define NAND_CTL_SETALE(nandptr) \ + nand_setcr((nandptr) + 1, CE_LO | CLE_LO) +#define NAND_CTL_CLRCLE(nandptr) \ + nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO) +#define NAND_CTL_SETCLE(nandptr) \ + nand_setcr((nandptr) + 1, CE_LO | ALE_LO) + /* * Miscellaneous configurable options */ @@ -329,7 +370,7 @@ * These preliminary values are also the final values. */ #define CFG_OR_TIMING_FPGA \ - (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK | OR_EHTR) + (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX) #define CFG_BR1_PRELIM ((CFG_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) #define CFG_OR1_PRELIM (((-CFG_FPGA_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_FPGA) @@ -338,7 +379,7 @@ * These preliminary values are also the final values. */ #define CFG_OR_TIMING_DFLASH \ - (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR) + (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX) #define CFG_BR4_PRELIM ((CFG_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) #define CFG_OR4_PRELIM (((-CFG_DFLASH_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_DFLASH) diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index e7d6c79..292b4bf 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -34,6 +34,8 @@ */ #define CONFIG_X86 1 /* This is a X86 CPU */ +#define CONFIG_SC520 1 /* Include support for AMD SC520 */ +#define CONFIG_ALI152X 1 /* Include support for Ali 152x SIO */ #define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */ #define CFG_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */ @@ -63,16 +65,9 @@ #define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024) -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CFG_ENV_IS_NOWHERE 1 -#undef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_INEEPROM - #define CONFIG_BAUDRATE 9600 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_EEPROM) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -86,8 +81,6 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* */ /* * Miscellaneous configurable options @@ -104,7 +97,7 @@ #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR 0x38000000 /* default load address */ +#define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_HZ 1024 /* incrementer freq: 1kHz */ @@ -117,26 +110,36 @@ */ #define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of DRAM */ - -#define PHYS_FLASH_1 0x38000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - /*----------------------------------------------------------------------- * FLASH and environment organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ + + +#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ /* timeout values are in ticks */ #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x7a0000) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CONFIG_SPI_EEPROM /* Support for SPI EEPROMs (AT25128) */ +#define CONFIG_MW_EEPROM /* Support for MicroWire EEPROMs (AT93LC46) */ + + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Environment in EEPROM */ +#define CFG_ENV_IS_IN_EEPROM 1 +#define CONFIG_SPI +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment EEPROM 16k is SPI is used or 128 bytes if MW is used*/ +#define CFG_ENV_OFFSET 0 +#define CONFIG_SC520_CDP_USE_SPI /* Store configuration in the SPI part */ +#undef CONFIG_SC520_CDP_USE_MW /* Store configuration in the MicroWire part */ +#define CONFIG_SPI_X 1 +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* */ /*----------------------------------------------------------------------- * Device drivers @@ -146,19 +149,20 @@ #define CONFIG_PCNET_79C973 #define CONFIG_PCNET_79C975 #define PCNET_HAS_PROM 1 + /************************************************************ * IDE/ATA stuff ************************************************************/ -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ +#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ #define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ -#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ +//#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ #define CFG_ATA_REG_OFFSET 0 /* reg offset */ #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ +#define CFG_ATA_BASE_ADDR 0 -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_LED /* no led for ide supported */ #undef CONFIG_IDE_RESET /* reset for ide unsupported... */ #undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */ @@ -176,23 +180,13 @@ #define CONFIG_ISO_PARTITION /* Experimental */ /************************************************************ - * Keyboard support + * Video/Keyboard support ************************************************************/ -#define CONFIG_ISA_KEYBOARD +#define CONFIG_VIDEO /* To enable video controller support */ +#define CONFIG_I8042_KBD +#define CFG_ISA_IO 0 + -#if 0 -/************************************************************ - * Video support - ************************************************************/ -#define CONFIG_VIDEO /*To enable video controller support */ -#define CONFIG_VIDEO_CT69000 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */ -#endif /************************************************************ * RTC @@ -207,4 +201,10 @@ #define CONFIG_PCI_PNP /* pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW +#define CFG_FIRST_PCI_IRQ 10 +#define CFG_SECOND_PCI_IRQ 9 +#define CFG_THIRD_PCI_IRQ 11 +#define CFG_FORTH_PCI_IRQ 15 + + #endif /* __CONFIG_H */ diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h new file mode 100644 index 0000000..4d5a568 --- /dev/null +++ b/include/configs/sc520_spunk.h @@ -0,0 +1,212 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_X86 1 /* This is a X86 CPU */ +#define CONFIG_SC520 1 /* Include support for AMD SC520 */ + +#define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */ +#define CFG_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */ +#define CFG_SDRAM_RAS_CAS_DELAY 3 /* 3T */ + +/* define at most one of these */ +#undef CFG_SDRAM_CAS_LATENCY_2T +#define CFG_SDRAM_CAS_LATENCY_3T + +#define CFG_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ +#define CFG_RESET_GENERIC 1 /* use tripple-fault to reset cpu */ +#undef CFG_RESET_SC520 /* use SC520 MMCR's to reset cpu */ +#undef CFG_TIMER_SC520 /* use SC520 swtimers */ +#define CFG_TIMER_GENERIC 1 /* use the i8254 PIT timers */ +#undef CFG_TIMER_TSC /* use the Pentium TSC timers */ + +#define CFG_STACK_SIZE 0x8000 /* Size of bootloader stack */ + +#define CONFIG_SHOW_BOOT_PROGRESS 1 +#define CONFIG_LAST_STAGE_INIT 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024) + + +#define CONFIG_BAUDRATE 9600 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_PCMCIA | CFG_CMD_EEPROM) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_BOOTDELAY 15 +#define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7936k(root),256k(uboot) " +#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1024 /* incrementer freq: 1kHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of DRAM */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + + +#define CONFIG_SPI_EEPROM /* SPI EEPROMs such as AT25010 or AT25640 */ +#define CONFIG_MW_EEPROM /* MicroWire EEPROMS such as AT93LC46 */ +#define CONFIG_DS1722 /* Dallas DS1722 SPI Temperature probe */ + + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + + +#if 0 +/* Environment in flash */ +#define CFG_ENV_IS_IN_FLASH 1 +# define CFG_ENV_ADDR (0x387a0000) /* Addr of Environment Sector */ +# define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector (or 0x10000) */ +# define CFG_ENV_OFFSET 0 + +#else +/* Environment in EEPROM */ + +# define CFG_ENV_IS_IN_EEPROM 1 +# define CONFIG_SPI +# define CONFIG_SPI_X 1 +# define CFG_ENV_SIZE 0x2000 /* Total Size of Environment EEPROM */ +# define CFG_ENV_OFFSET 0x1c00 + +#endif + +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* */ + +/*----------------------------------------------------------------------- + * Device drivers + */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_EEPRO100 + +/************************************************************ + * IDE/ATA stuff + ************************************************************/ +#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ +#define CFG_ATA_BASE_ADDR 0 +#define CFG_ATA_IDE0_OFFSET 0x01f0 /* ide0 offset */ +#define CFG_ATA_IDE1_OFFSET 0xe000 /* ide1 offset */ +#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ +#define CFG_ATA_REG_OFFSET 0 /* reg offset */ +#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ + +#define CFG_FISRT_PCMCIA_BUS 1 + +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* reset for ide unsupported... */ +#undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */ + +#define CONFIG_IDE_TI_CARDBUS +#define CFG_PCMCIA_CIS_WIN 0x27f00000 +#define CFG_PCMCIA_CIS_WIN_SIZE 0x00100000 +#define CFG_PCMCIA_IO_WIN 0xe000 +#define CFG_PCMCIA_IO_WIN_SIZE 16 + +/************************************************************ + * DISK Partition support + ************************************************************/ +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION /* Experimental */ + + + + +/************************************************************ + * RTC + ***********************************************************/ +#define CONFIG_RTC_MC146818 +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * PCI stuff + */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW + +#define CFG_FIRST_PCI_IRQ 9 +#define CFG_SECOND_PCI_IRQ 10 +#define CFG_THIRD_PCI_IRQ 11 +#define CFG_FORTH_PCI_IRQ 12 + + +#endif /* __CONFIG_H */ diff --git a/include/configs/sc520_spunk_rel.h b/include/configs/sc520_spunk_rel.h new file mode 100644 index 0000000..2d53530 --- /dev/null +++ b/include/configs/sc520_spunk_rel.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _outer_config +#define _outer_config + +#include "sc520_spunk.h" + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "fsload boot/vmlinuz ; bootm" + +#endif diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h index 5aec47a..80cfe8a 100644 --- a/include/configs/utx8245.h +++ b/include/configs/utx8245.h @@ -51,16 +51,39 @@ #define CONFIG_UTX8245 1 #define DEBUG 1 +#define CONFIG_IDENT_STRING " [UTX5] " + #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 57600 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTDELAY 2 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" -#define CONFIG_BOOTCOMMAND "bootm FF920000 FF800000" /* autoboot command */ +#define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */ -#define CONFIG_ETHADDR 41:52:4c:61:00:01 /* MAC address */ -#define CONFIG_SERVERIP 10.8.17.105 +#define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */ +#define CONFIG_SERVERIP 10.8.17.105 /* Spree */ +#define CFG_TFTP_LOADADDR 10000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=FFA00000\0" \ + "ramdisk_addr=FF800000\0" \ + "u-boot_startaddr=FFB00000\0" \ + "u-boot_endaddr=FFB2FFFF\0" \ + "nfsargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/nfs rw \ +nfsroot=$(nfsrootip):$(rootpath) ip=dhcp\0" \ + "ramargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/ram0\0" \ + "smargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/mtdblock1 ro\0" \ + "fwargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/sda2 ro\0" \ + "nfsboot=run nfsargs;bootm $(kernel_addr)\0" \ + "ramboot=run ramargs;bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "smboot=run smargs;bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "fwboot=run fwargs;bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "update_u-boot=tftp $(loadaddr) /bdi2000/u-boot.bin;protect off \ +$(u-boot_startaddr) $(u-boot_endaddr);era $(u-boot_startaddr) \ +$(u-boot_endaddr);cp.b $(loadaddr) $(u-boot_startaddr) $(filesize);\ +protect on $(u-boot_startaddr) $(u-boot_endaddr)" + #define CONFIG_ENV_OVERWRITE #define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_BDI | CFG_CMD_PCI \ @@ -70,7 +93,8 @@ | CFG_CMD_IMI | CFG_CMD_CACHE \ | CFG_CMD_RUN | CFG_CMD_ECHO \ | CFG_CMD_REGINFO | CFG_CMD_NET\ - | CFG_CMD_DHCP) + | CFG_CMD_DHCP | CFG_CMD_I2C \ + | CFG_CMD_DATE) /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -80,9 +104,9 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) @@ -101,12 +125,20 @@ #define CONFIG_PCI_SCAN_SHOW #define CONFIG_NET_MULTI #define CONFIG_EEPRO100 +#define CONFIG_EEPRO100_SROM_WRITE + +#define PCI_ENET0_IOADDR 0xF0000000 +#define PCI_ENET0_MEMADDR 0xF0000000 -#define PCI_ENET0_IOADDR 0x80000000 +#define PCI_FIREWIRE_IOADDR 0xF1000000 +#define PCI_FIREWIRE_MEMADDR 0xF1000000 +/* +#define PCI_ENET0_IOADDR 0xFE000000 #define PCI_ENET0_MEMADDR 0x80000000 + #define PCI_FIREWIRE_IOADDR 0x81000000 #define PCI_FIREWIRE_MEMADDR 0x81000000 - +*/ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -114,12 +146,13 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x10000000 /* amount of SDRAM */ - +#define CFG_MAX_RAM_SIZE 0x10000000 /* 256MB */ +/*#define CFG_VERY_BIG_RAM 1 */ -/* even though FLASHP_BASE is FF800000, with 2MB on RCS0, the - * reset vector is actually located at FF800100, but the 8245 - * takes care of us. +/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector + * is actually located at FFF00100. Therefore, U-Boot is + * physically located at 0xFFB0_0000, but is also mirrored at + * 0xFFF0_0000. */ #define CFG_RESET_ADDRESS 0xFFF00100 @@ -132,17 +165,19 @@ /*#define CFG_DRAM_TEST 1 */ #define CFG_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */ -#define CFG_MEMTEST_END 0x0ff8ffa8 /* in SDRAM, skips exception */ +#define CFG_MEMTEST_END 0x0ff8ffa7 /* in SDRAM, skips exception */ /* vectors and U-Boot */ /*-------------------------------------------------------------------- * Definitions for initial stack pointer and data area *------------------------------------------------------------------*/ -#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for */ +#define CFG_INIT_DATA_SIZE 128 /* Size in bytes reserved for */ /* initial data */ #define CFG_INIT_RAM_ADDR 0x40000000 #define CFG_INIT_RAM_END 0x1000 +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_GBL_DATA_SIZE 128 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) /*-------------------------------------------------------------------- @@ -153,10 +188,16 @@ #define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) +#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2) +# define CFG_NS16550_CLK get_bus_freq(0) +#else +# define CFG_NS16550_CLK 33000000 +#endif #define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) #define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) +#define CFG_NS16550_COM3 0xFF000000 +#define CFG_NS16550_COM4 0xFF000008 /*-------------------------------------------------------------------- * Low Level Configuration Settings @@ -168,46 +209,61 @@ #define CONFIG_SYS_CLK_FREQ 33000000 #define CFG_HZ 1000 -#define CFG_ETH_DEV_FN 0x7800 -#define CFG_ETH_IOBASE 0x00104000 +/*#define CFG_ETH_DEV_FN 0x7800 */ +/*#define CFG_ETH_IOBASE 0x00104000 */ + +/*-------------------------------------------------------------------- + * I2C Configuration + *------------------------------------------------------------------*/ +#if 1 +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#endif +#define CONFIG_RTC_PCF8563 1 /* enable I2C support for */ + /* Philips PCF8563 RTC */ +#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ /*-------------------------------------------------------------------- * Memory Control Configuration Register values * - see sec. 4.12 of MPC8245 UM *------------------------------------------------------------------*/ -/* MCCR1 */ +/**** MCCR1 ****/ #define CFG_ROMNAL 0 -#define CFG_ROMFAL 2 /* (tacc=70ns)*mem_freq - 2 */ -#define CFG_BANK0_ROW 2 /* SDRAM bank 7-0 row address */ -#define CFG_BANK1_ROW 2 /* bit count */ -#define CFG_BANK2_ROW 0 -#define CFG_BANK3_ROW 0 -#define CFG_BANK4_ROW 0 +#define CFG_ROMFAL 10 /* (tacc=70ns)*mem_freq - 2, + mem_freq = 100MHz */ + +#define CFG_BANK7_ROW 0 /* SDRAM bank 7-0 row address */ +#define CFG_BANK6_ROW 0 /* bit count */ #define CFG_BANK5_ROW 0 -#define CFG_BANK6_ROW 0 -#define CFG_BANK7_ROW 0 +#define CFG_BANK4_ROW 0 +#define CFG_BANK3_ROW 0 +#define CFG_BANK2_ROW 0 +#define CFG_BANK1_ROW 2 +#define CFG_BANK0_ROW 2 -/* MCCR2, refresh interval clock cycles */ +/**** MCCR2, refresh interval clock cycles ****/ #define CFG_REFINT 480 /* 33 MHz SDRAM clock was 480 */ -/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4 */ +/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ #define CFG_BSTOPRE 1023 /* burst to precharge[0..9], */ /* sets open page interval */ -/* MCCR3 */ -#define CFG_REFREC 5 /* Refresh to activate interval, trc */ +/**** MCCR3 ****/ +#define CFG_REFREC 7 /* Refresh to activate interval, trc */ -/* MCCR4 */ +/**** MCCR4 ****/ #define CFG_PRETOACT 2 /* trp */ -#define CFG_ACTTOPRE 7 /* trcd + (burst length - 1) + tdrl */ +#define CFG_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */ #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */ #define CFG_ACTORW 2 /* trcd min */ #define CFG_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */ #define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 1 +#define CFG_EXTROM 0 /* we don't need extended ROM space */ #define CFG_REGDIMM 0 /* calculate according to formula in sec. 6-22 of 8245 UM */ @@ -216,10 +272,18 @@ /* was 45 */ #define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */ - /* bottom 3 bits MUST be 0 */ + /* bits 7,6, and 3-0 MUST be 0 */ +#if 0 #define CFG_DLL_MAX_DELAY 0x04 +#else +#define CFG_DLL_MAX_DELAY 0 +#endif +#if 0 /* need for 33MHz SDRAM */ #define CFG_DLL_EXTEND 0x80 +#else +#define CFG_DLL_EXTEND 0 +#endif #define CFG_PCI_HOLD_DEL 0x20 @@ -255,29 +319,34 @@ #define CFG_BANK7_END 0x3fffffff #define CFG_BANK7_ENABLE 0 -/*-------------------------------------------------------------------- - * 4.4 - Output Driver Control Register - *------------------------------------------------------------------*/ +/*--------------------------------------------------------------------*/ +/* 4.4 - Output Driver Control Register */ +/*--------------------------------------------------------------------*/ #define CFG_ODCR 0xe5 -/*-------------------------------------------------------------------- - * 4.8 - Error Handling Registers - *------------------------------------------------------------------*/ +/*--------------------------------------------------------------------*/ +/* 4.8 - Error Handling Registers */ +/*-------------------------------CFG_SDMODE_BURSTLEN-------------------------------------*/ #define CFG_ERRENR1 0x11 /* enable SDRAM refresh overflow error */ /* SDRAM 0-256 MB */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +/*#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */ #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) /* stack in dcache */ #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +#define CFG_IBAT2L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT2U (CFG_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP) + /* PCI memory */ -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) +/*#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */ +/*#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */ -/* Flash, config addrs, etc. */ +/*Flash, config addrs, etc. */ #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) @@ -298,26 +367,30 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- - * FLASH organization (AMD AM29LV116D) - */ + * FLASH organization + *----------------------------------------------------------------------*/ #define CFG_FLASH_BASE 0xFF800000 +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - /* Warning: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ +/* NOTE: environment is not EMBEDDED in the u-boot code. + It's stored in flash in its own separate sector. */ #define CFG_ENV_IS_IN_FLASH 1 +#if 1 /* AMD AM29LV033C */ +#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */ +#define CFG_ENV_ADDR 0xFFBF0000 /* flash sector SA63 */ +#define CFG_ENV_SECT_SIZE (64*1024) /* Size of the Environment Sector */ +#else /* AMD AM29LV116D */ +#define CFG_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */ #define CFG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */ -#define CFG_ENV_SIZE 0x2000 /* Size of the Environment */ +#define CFG_ENV_SECT_SIZE (8*1024) /* Size of the Environment Sector */ +#endif /* #if */ + +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Size of the Environment */ #define CFG_ENV_OFFSET 0 /* starting right at the beginning */ -#define CFG_ENV_SECT_SIZE 0x2000 /* Size of the Environment Sector */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #if CFG_MONITOR_BASE >= CFG_FLASH_BASE #undef CFG_RAMBOOT |