diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/DU405.h | 2 | ||||
| -rw-r--r-- | include/configs/KAREF.h | 309 | ||||
| -rw-r--r-- | include/configs/METROBOX.h | 377 | ||||
| -rw-r--r-- | include/configs/MIP405.h | 2 | ||||
| -rw-r--r-- | include/configs/PCI405.h | 1 | ||||
| -rw-r--r-- | include/configs/PIP405.h | 2 | ||||
| -rw-r--r-- | include/configs/VCMA9.h | 2 | ||||
| -rw-r--r-- | include/configs/WUH405.h | 1 | ||||
| -rw-r--r-- | include/configs/hmi1001.h | 18 | ||||
| -rw-r--r-- | include/configs/stxxtc.h | 592 |
10 files changed, 1303 insertions, 3 deletions
diff --git a/include/configs/DU405.h b/include/configs/DU405.h index b917092..a251298 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -32,12 +32,14 @@ * High Level Configuration Options * (easy to change) */ +#define CONFIG_IDENT_STRING " $Name: $" #define CONFIG_405GP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_DU405 1 /* ...on a DU405 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h new file mode 100644 index 0000000..331131a --- /dev/null +++ b/include/configs/KAREF.h @@ -0,0 +1,309 @@ +/* + * (C) Copyright 2004 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference + * design. + ***********************************************************************/ + +/* + * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $ + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */ +#define CONFIG_440GX 1 /* Specifc GX support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ +#undef CFG_DRAM_TEST /* Disable-takes long time!*/ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +#define CONFIG_VERY_BIG_RAM 1 +#define CONFIG_VERSION_VARIABLE + +#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design" + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ + +#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) +#define CFG_KAREF_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000) +#define CFG_OFEM_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08400000) +#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000) +#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700) + +/* Here for completeness */ +#define CFG_OFEMAC_BASE (CFG_PERIPHERAL_BASE + 0x08600000) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_BAUDRATE 9600 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * NVRAM/RTC + * + * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. + * The DS1743 code assumes this condition (i.e. -- it assumes the base + * address for the RTC registers is: + * + * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE + * + *----------------------------------------------------------------------*/ +#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/ +#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 8 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/ +#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C hardware support */ +#undef CONFIG_SOFT_I2C /* I2C !bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */ + + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ +#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ +#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ +#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */ + +#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */ +#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR) + +#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/*----------------------------------------------------------------------- + * Networking + *----------------------------------------------------------------------*/ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ +#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ +#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */ +#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */ +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ +#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ +#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */ +#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */ +#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ + + +/*----------------------------------------------------------------------- + * Console/Commands/Parser + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_I2C | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_PING | \ + CFG_CMD_DIAG | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_ELF | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT) + +/* Include NetConsole support */ +#define CONFIG_NETCONSOLE + +/* Include auto complete with tabs */ +#define CONFIG_AUTO_COMPLETE 1 +#define CFG_AUTO_COMPLETE 1 +#define CFG_ALT_MEMTEST 1 /* use real memory test */ + + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "KaRefDes=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */ +#define CFG_PROMPT_HUSH_PS2 "> " + + +/*----------------------------------------------------------------------- + * Console Buffer + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) + /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of cmd args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */ + +/*----------------------------------------------------------------------- + * Memory Test + *----------------------------------------------------------------------*/ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/*----------------------------------------------------------------------- + * Compact Flash (in true IDE mode) + *----------------------------------------------------------------------*/ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xF0000000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/ +#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */ + +#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride + to get to the correct offset */ +#define CONFIG_DOS_PARTITION 1 /* Include dos partition */ + +/*----------------------------------------------------------------------- + * PCI + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices */ +#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ +#define CFG_PCI_TARGET_INIT /* let board init pci target*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ +#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */ +#endif + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CFG_LOAD_ADDR 0x8000000 /* default load address */ +#define CFG_EXTBDINFO 1 /* use extended board_info */ + +#define CFG_HZ 100 /* decr freq: 1 ms ticks */ + + +#endif /* __CONFIG_H */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h new file mode 100644 index 0000000..2b4a33f --- /dev/null +++ b/include/configs/METROBOX.h @@ -0,0 +1,377 @@ +/* + * (C) Copyright 2004 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * METROBOX.h - configuration Sandburst MetroBox + ***********************************************************************/ + +/* + * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $ + * + * + * $Log: METROBOX.h,v $ + * Revision 1.21 2005/06/03 15:05:25 tsawyer + * MB rev 2.0.3 KA rev 0.0.7. Add CONFIG_VERSION_VARIABLE, Add fakeled to MB + * + * Revision 1.20 2005/04/11 20:51:11 tsawyer + * fix ethernet + * + * Revision 1.19 2005/04/06 15:13:36 tsawyer + * Update appropriate files to coincide with u-boot 1.1.3 + * + * Revision 1.18 2005/03/10 14:16:02 tsawyer + * add def'n for cis8201 short etch option. + * + * Revision 1.17 2005/03/09 19:49:51 tsawyer + * Remove KGDB to allow use of 2nd serial port + * + * Revision 1.16 2004/12/02 19:00:23 tsawyer + * Add misc_init_f to turn on i2c-1 and all four fans before sdram init + * + * Revision 1.15 2004/09/15 18:04:12 tsawyer + * add multiple serial port support + * + * Revision 1.14 2004/09/03 15:27:51 tsawyer + * All metrobox boards are at 66.66 sys clock + * + * Revision 1.13 2004/08/05 20:27:46 tsawyer + * Remove system ace definitions, add net console support + * + * Revision 1.12 2004/07/29 20:00:13 tsawyer + * Add i2c bus 1 + * + * Revision 1.11 2004/07/21 13:44:18 tsawyer + * SystemACE is out, CF direct to local bus is in + * + * Revision 1.10 2004/06/29 19:08:55 tsawyer + * Add CONFIG_MISC_INIT_R + * + * Revision 1.9 2004/06/28 21:30:53 tsawyer + * Fix default BOOTARGS + * + * Revision 1.8 2004/06/17 15:51:08 tsawyer + * auto complete + * + * Revision 1.7 2004/06/17 15:08:49 tsawyer + * Add autocomplete + * + * Revision 1.6 2004/06/15 12:33:57 tsawyer + * debugging checkpoint + * + * Revision 1.5 2004/06/12 19:48:28 tsawyer + * Debugging checkpoint + * + * Revision 1.4 2004/06/02 13:03:06 tsawyer + * Fix eth addrs + * + * Revision 1.3 2004/05/18 19:56:10 tsawyer + * Change default bootcommand to pImage.metrobox + * + * Revision 1.2 2004/05/18 14:13:44 tsawyer + * Add bringup values for bootargs and bootcommand. + * Remove definition of ipaddress and serverip addresses. + * + * Revision 1.1 2004/04/16 15:08:54 tsawyer + * Initial Revision + * + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_METROBOX 1 /* Board is Metrobox */ +#define CONFIG_440GX 1 /* Specifc GX support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ +#undef CFG_DRAM_TEST /* Disable-takes long time!*/ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +#define CONFIG_VERY_BIG_RAM 1 +#define CONFIG_VERSION_VARIABLE + +#define CONFIG_IDENT_STRING " Sandburst Metrobox" + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ + +#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) +#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000) +#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000) +#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_BAUDRATE 9600 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * NVRAM/RTC + * + * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. + * The DS1743 code assumes this condition (i.e. -- it assumes the base + * address for the RTC registers is: + * + * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE + * + *----------------------------------------------------------------------*/ +#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/ +#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 8 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/ +#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C hardware support */ +#undef CONFIG_SOFT_I2C /* I2C !bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */ + + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ +#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ +#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ +#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */ + +#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */ +#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR) + +#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none " +#define CONFIG_BOOTCOMMAND "tftp 8000000 pImage.metrobox;bootm 8000000" +#define CONFIG_BOOTDELAY 5 /* disable autoboot */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/*----------------------------------------------------------------------- + * Networking + *----------------------------------------------------------------------*/ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ +#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ +#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */ +#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */ +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ +#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ +#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */ +#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */ +#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ + + +/*----------------------------------------------------------------------- + * Console/Commands/Parser + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_I2C | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_PING | \ + CFG_CMD_DIAG | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_ELF | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT) + +/* tbs 09-March-2005 Removed to be able to use 2nd serial */ +/* CFG_CMD_KGDB | \ */ + + +/* Include NetConsole support */ +#define CONFIG_NETCONSOLE + +/* Include auto complete with tabs */ +#define CONFIG_AUTO_COMPLETE 1 +#define CFG_AUTO_COMPLETE 1 +#define CFG_ALT_MEMTEST 1 /* use real memory test */ + + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "MetroBox=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */ +#define CFG_PROMPT_HUSH_PS2 "> " + + +/*----------------------------------------------------------------------- + * Console Buffer + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) + /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of cmd args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */ + +/*----------------------------------------------------------------------- + * Memory Test + *----------------------------------------------------------------------*/ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/*----------------------------------------------------------------------- + * Compact Flash (in true IDE mode) + *----------------------------------------------------------------------*/ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xF0000000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/ +#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */ + +#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride + to get to the correct offset */ +#define CONFIG_DOS_PARTITION 1 /* Include dos partition */ + +/*----------------------------------------------------------------------- + * PCI + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices */ +#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ +#define CFG_PCI_TARGET_INIT /* let board init pci target*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ +#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */ +#endif + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CFG_LOAD_ADDR 0x8000000 /* default load address */ +#define CFG_EXTBDINFO 1 /* use extended board_info */ + +#define CFG_HZ 100 /* decr freq: 1 ms ticks */ + + +#endif /* __CONFIG_H */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 0af9c68..6c2f17d 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -128,7 +128,7 @@ #define CONFIG_BAUDRATE 9600 /* STD Baudrate */ #define CONFIG_BOOTDELAY 5 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */ +/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 2671125..469d88f 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -32,6 +32,7 @@ * High Level Configuration Options * (easy to change) */ +#define CONFIG_IDENT_STRING " $Name: esd_PCI405_05_07_28 $" #define CONFIG_405GP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index dbec242..9ac5715 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -112,7 +112,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */ +/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index bde12e1..3f29190 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -138,7 +138,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */ +/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ #define CONFIG_NETMASK 255.255.255.0 diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index b4dfdf4..5c9950f 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -32,6 +32,7 @@ * High Level Configuration Options * (easy to change) */ +#define CONFIG_IDENT_STRING " $Name: $" #define CONFIG_405EP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index 7f9fea5..9da15ed 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -65,6 +65,7 @@ CFG_CMD_I2C | \ CFG_CMD_IDE | \ CFG_CMD_NFS | \ + CFG_CMD_PCI | \ CFG_CMD_SNTP) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -307,4 +308,21 @@ #define CONFIG_ATAPI 1 +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +#define CONFIG_PCI_SCAN_SHOW 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + #endif /* __CONFIG_H */ diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h new file mode 100644 index 0000000..a0e1ba7 --- /dev/null +++ b/include/configs/stxxtc.h @@ -0,0 +1,592 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com + * U-Boot port on STx XTc 8xx board + * Mostly copied from Panto's NETTA2 board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC875 1 /* This is a MPC875 CPU */ +#define CONFIG_STXXTC 1 /* ...on a STx XTc board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ + +#define CONFIG_XIN 10000000 /* 10 MHz input xtal */ + +/* Select one of few clock rates defined later in this file. +*/ +/* #define MPC8XX_HZ 50000000 */ +#define MPC8XX_HZ 66666666 + +#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +#define CONFIG_AUTOSCRIPT +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) + +#undef CONFIG_MAC_PARTITION +#undef CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define FEC_ENET 1 /* eth.c needs it that way... */ +#undef CFG_DISCOVER_PHY +#define CONFIG_MII 1 +#undef CONFIG_RMII + +#define CONFIG_ETHER_ON_FEC1 1 +#define CONFIG_FEC1_PHY 1 /* phy address of FEC */ +#undef CONFIG_FEC1_PHY_NORXERR + +#define CONFIG_ETHER_ON_FEC2 1 +#define CONFIG_FEC2_PHY 3 +#undef CONFIG_FEC2_PHY_NORXERR + +#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_NAND | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_MII | \ + CFG_CMD_NFS) + +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_MISC_INIT_R + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "xtc> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif + +/* yes this is weird, I know :) */ +#define CFG_MONITOR_BASE (CFG_FLASH_BASE | 0x00F00000) +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +#define CFG_RESET_ADDRESS 0x80000000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x10000 + +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000) +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 0x4000 + +#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x00010000) +#define CFG_ENV_OFFSET_REDUND 0 +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + 0x2000000 } + +#define CFG_FLASH_PROTECTION + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + */ + +#if CONFIG_XIN == 10000000 + +#if MPC8XX_HZ == 50000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 66666666 +#define CFG_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#else +#error unsupported CPU freq for XIN = 10MHz +#endif +#else +#error unsupported freq for XIN (must be 10MHz) +#endif + + +/* + *----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + * + * Note: When TBS == 0 the timebase is independent of current cpu clock. + */ + +#define SCCR_MASK SCCR_EBDF11 +#if MPC8XX_HZ > 66666666 +#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00 | SCCR_EBDF01) +#else +#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) +#endif + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ + +#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */ + +#define CFG_REMAP_OR_AM 0x80000000 +#define CFG_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) + +#define CFG_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CFG_OR_TIMING_FLASH) +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) + +/* + * BR4 and OR4 (SDRAM) + * + */ +#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) + +#define CFG_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) +#define CFG_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) + +/* + * Memory Periodic Timer Prescaler + */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_MAMR_PTA 234 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ + +/****************************************************************/ + +#define NAND_SIZE 0x00010000 /* 64K */ +#define NAND_BASE 0xF1000000 + +/****************************************************************/ + +/* NAND */ +#define CFG_NAND_BASE NAND_BASE +#define CONFIG_MTD_NAND_ECC_JFFS2 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_MTD_NAND_UNSAFE + +#define CFG_MAX_NAND_DEVICE 1 +#undef NAND_NO_RB + +#define SECTORSIZE 512 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */ +#define NAND_DISABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \ + } while(0) + +#define NAND_ENABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \ + } while(0) + +#define NAND_CTL_CLRALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \ + } while(0) + +#define NAND_CTL_SETALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \ + } while(0) + +#define NAND_CTL_CLRCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \ + } while(0) + +#define NAND_CTL_SETCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \ + } while(0) + +#ifndef NAND_NO_RB +#define NAND_WAIT_READY(nand) \ + do { \ + int _tries = 0; \ + while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \ + if (++_tries > 100000) \ + break; \ + } while (0) +#else +#define NAND_WAIT_READY(nand) udelay(12) +#endif + +#define WRITE_NAND_COMMAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND_ADDRESS(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define READ_NAND(adr) \ + ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) + +/*****************************************************************************/ + +#define CFG_DIRECT_FLASH_TFTP +#define CFG_DIRECT_NAND_TFTP + +/*****************************************************************************/ + +/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB, + * CxOE and CxRESET. We use the CxOE. + */ +#define STATUS_LED_BIT 0x00000080 /* bit 24 */ + +#define STATUS_LED_PERIOD (CFG_HZ / 2) +#define STATUS_LED_STATE STATUS_LED_BLINKING + +#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ +#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +#ifndef __ASSEMBLY__ + +/* LEDs */ + +/* led_id_t is unsigned int mask */ +typedef unsigned int led_id_t; + +#define __led_toggle(_msk) \ + do { \ + ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \ + } while(0) + +#define __led_set(_msk, _st) \ + do { \ + if ((_st)) \ + ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \ + else \ + ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \ + } while(0) + +#define __led_init(msk, st) __led_set(msk, st) + +#endif + +/******************************************************************************/ + +#define CFG_CONSOLE_IS_IN_ENV 1 +#define CFG_CONSOLE_OVERWRITE_ROUTINE 1 +#define CFG_CONSOLE_ENV_OVERWRITE 1 + +/******************************************************************************/ + +/* use board specific hardware */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_SHOW_ACTIVITY + +/*****************************************************************************/ + +#define CONFIG_AUTO_COMPLETE 1 +#define CONFIG_CRC32_VERIFY 1 +#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 + +/* Note: change below for your network setting!!! + * This was done just to facilitate manufacturing test and configuration. + */ +#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a + +#define CONFIG_SERVERIP 192.168.08.1 +#define CONFIG_IPADDR 192.168.08.85 +#define CONFIG_GATEWAYIP 192.168.08.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_HOSTNAME stx_xtc +#define CONFIG_ROOTPATH /xtcroot +#define CONFIG_BOOTFILE uImage +#define CONFIG_LOADADDR 0x1000000 + + +#endif /* __CONFIG_H */ |