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-rw-r--r--include/configs/ls1043a_common.h13
-rw-r--r--include/configs/ls1043aqds.h24
2 files changed, 37 insertions, 0 deletions
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 35d9750..8900dae 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -121,6 +121,7 @@
#endif
/* IFC */
+#ifndef CONFIG_SD_BOOT_QSPI
#define CONFIG_FSL_IFC
/*
* CONFIG_SYS_FLASH_BASE has the final address (core view)
@@ -139,6 +140,7 @@
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#endif
+#endif
/* I2C */
#define CONFIG_CMD_I2C
@@ -205,9 +207,11 @@
#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
#define CONFIG_SPI_FLASH_SST /* cs1 */
#define CONFIG_SPI_FLASH_EON /* cs2 */
+#ifndef CONFIG_SD_BOOT_QSPI
#define CONFIG_SF_DEFAULT_BUS 1
#define CONFIG_SF_DEFAULT_CS 0
#endif
+#endif
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
@@ -216,9 +220,18 @@
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 1000000
+#define CONFIG_ENV_SPI_MODE 0x03
+#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
/* FMan fireware Pre-load address */
#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
+#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index e6725e3..60d189b 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -85,8 +85,13 @@ unsigned long get_board_ddr_clk(void);
#endif
#ifdef CONFIG_SD_BOOT
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
+#else
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
#endif
+#endif
/* LPUART */
#ifdef CONFIG_LPUART
@@ -113,6 +118,7 @@ unsigned long get_board_ddr_clk(void);
/*
* IFC Definitions
*/
+#ifndef CONFIG_SD_BOOT_QSPI
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
@@ -196,6 +202,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#endif
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
@@ -203,6 +210,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
#endif
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#endif
+
/*
* QIXIS Definitions
*/
@@ -219,6 +232,7 @@ unsigned long get_board_ddr_clk(void);
#define QIXIS_LBMAP_ALTBANK 0x04
#define QIXIS_LBMAP_NAND 0x09
#define QIXIS_LBMAP_SD 0x00
+#define QIXIS_LBMAP_SD_QSPI 0xff
#define QIXIS_RCW_SRC_NAND 0x106
#define QIXIS_RCW_SRC_SD 0x040
#define QIXIS_RST_CTL_RESET 0x41
@@ -347,6 +361,16 @@ unsigned long get_board_ddr_clk(void);
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
+/* QSPI device */
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_FSL_QSPI
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE (1 << 24)
+#define FSL_QSPI_FLASH_NUM 2
+#endif
+#endif
+
/*
* Miscellaneous configurable options
*/