diff options
Diffstat (limited to 'include/configs')
32 files changed, 836 insertions, 77 deletions
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 8234a82..75ea125 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -611,9 +611,8 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 -#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 +#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 +#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index 5e988c2..7cfda50 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -79,10 +79,6 @@ #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 @@ -202,6 +198,7 @@ /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ @@ -386,6 +383,10 @@ #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 /* * General PCI @@ -543,13 +544,12 @@ #endif #ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 #define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_ETHPRIME "FM1@DTSEC4" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif @@ -627,9 +627,9 @@ #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index aafa813..ed9ca8a 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -79,10 +79,6 @@ #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 @@ -202,6 +198,7 @@ /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ @@ -394,6 +391,10 @@ #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 /* * General PCI @@ -551,8 +552,11 @@ #endif #ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 + #define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_ETHPRIME "FM1@DTSEC4" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif @@ -631,9 +635,9 @@ #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h new file mode 100644 index 0000000..88d27db --- /dev/null +++ b/include/configs/arcangel4-be.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_ARCANGEL4_H_ +#define _CONFIG_ARCANGEL4_H_ + +/* + * CPU configuration + */ +#define CONFIG_SYS_BIG_ENDIAN +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_CLK_FREQ 70000000 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ + +#define CONFIG_ARCH_EARLY_INIT_R + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x81000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_SYS_NO_FLASH + +/* + * UART configuration + * + */ +#define CONFIG_ARC_SERIAL +#define CONFIG_ARC_UART_BASE 0xC0FC1000 +#define CONFIG_BAUDRATE 115200 + +/* + * Command line configuration + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyARC0,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "arcangel4# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#endif /* _CONFIG_ARCANGEL4_H_ */ diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h new file mode 100644 index 0000000..4579eb9 --- /dev/null +++ b/include/configs/arcangel4.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_ARCANGEL4_H_ +#define _CONFIG_ARCANGEL4_H_ + +/* + * CPU configuration + */ +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_CLK_FREQ 70000000 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ + +#define CONFIG_ARCH_EARLY_INIT_R + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x81000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_SYS_NO_FLASH + +/* + * UART configuration + * + */ +#define CONFIG_ARC_SERIAL +#define CONFIG_ARC_UART_BASE 0xC0FC1000 +#define CONFIG_BAUDRATE 115200 + +/* + * Command line configuration + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyARC0,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "arcangel4# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#endif /* _CONFIG_ARCANGEL4_H_ */ diff --git a/include/configs/axs101.h b/include/configs/axs101.h new file mode 100644 index 0000000..af2e63b --- /dev/null +++ b/include/configs/axs101.h @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_AXS101_H_ +#define _CONFIG_AXS101_H_ + +/* + * CPU configuration + */ +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_CLK_FREQ 750000000 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* dwgmac doesn't work with D$ enabled now */ +#define CONFIG_SYS_DCACHE_OFF + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ + +#define CONFIG_ARCH_EARLY_INIT_R + +#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000 +#define ARC_APB_PERIPHERAL_BASE 0xF0000000 +#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000) +#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000) + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x81000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ +#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* + * NAND Flash configuration + */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000) +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* + * UART configuration + * + * CONFIG_CONS_INDEX = 1 - Debug UART + * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB + */ +#define CONFIG_CONS_INDEX 4 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#if (CONFIG_CONS_INDEX == 1) + /* Debug UART */ +# define CONFIG_SYS_NS16550_CLK 33333000 +#else + /* FPGA UARTs use different clock */ +# define CONFIG_SYS_NS16550_CLK 33333333 +#endif +#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000) +#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000) +#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000) +#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000) +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_BAUDRATE 115200 +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C +#define CONFIG_DW_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_ENV_EEPROM_BUS 2 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0 +#define CONFIG_SYS_I2C_BASE 0xE001D000 +#define CONFIG_SYS_I2C_BASE1 0xE001E000 +#define CONFIG_SYS_I2C_BASE2 0xE001F000 +#define CONFIG_SYS_I2C_BUS_MAX 3 +#define IC_CLK 50 + +/* + * EEPROM configuration + */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1) +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 32 + +/* + * SD/MMC configuration + */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DWMMC +#define CONFIG_DOS_PARTITION + +/* + * Ethernet PHY configuration + */ +#define CONFIG_PHYLIB +#define CONFIG_MII +#define CONFIG_PHY_GIGE + +/* + * Ethernet configuration + */ +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_AUTONEG +#define CONFIG_DW_SEARCH_PHY +#define CONFIG_NET_MULTI + +/* + * Command line configuration + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_RARP + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_IN_EEPROM +#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyS3,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "axs# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Misc utility configuration + */ +#define CONFIG_BOUNCE_BUFFER + +#endif /* _CONFIG_AXS101_H_ */ diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 1a43e1b..12192ff 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -72,12 +72,13 @@ #define CONFIG_NET_MULTI #define CONFIG_HOSTNAME "bf609-ezkit" #define CONFIG_DESIGNWARE_ETH +#define CONFIG_PHY_ADDR 1 #define CONFIG_DW_PORTS 1 -#define CONFIG_DW_AUTONEG #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_MII +#define CONFIG_PHYLIB /* i2c Settings */ #define CONFIG_BFIN_TWI_I2C diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 4abb03e..e80d1a6 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -30,6 +30,10 @@ #define V_PROMPT "Tegra30 (Cardhu) # " #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu" +#define BOARD_EXTRA_ENV_SETTINGS \ + "board_name=cardhu-a04\0" \ + "fdtfile=tegra30-cardhu-a04.dtb\0" + /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI #define CONFIG_TEGRA_ENABLE_UARTA diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 04ae3ca..86574c8 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -73,6 +73,8 @@ #define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SUPPORT_EMMC_BOOT + /* USB xHCI HOST */ #define CONFIG_CMD_USB #define CONFIG_USB_HOST diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 2a15ad4..517f46a 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -99,11 +99,16 @@ #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */ +#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS +#define CONFIG_KM_UBI_PART_BOOT_OPTS "" +#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */ + #ifndef CONFIG_KM_UBI_PARTITION_NAME_APP /* one flash chip only called boot */ /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ # define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT + "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ + CONFIG_KM_UBI_PART_BOOT_OPTS # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ "ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0" #else /* CONFIG_KM_UBI_PARTITION_NAME_APP */ @@ -111,7 +116,8 @@ /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ /* app: CONFIG_KM_UBI_PARTITION_NAME_APP */ # define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT " " \ + "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ + CONFIG_KM_UBI_PART_BOOT_OPTS " " \ "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ "ubiattach=if test ${boot_bank} -eq 0; then; " \ @@ -135,8 +141,8 @@ * - 'release': for a standalone system kernel/rootfs from flash */ #define CONFIG_KM_DEF_ENV_BOOTTARGETS \ - "subbootcmds=ubiattach ubicopy cramfsloadfdt cramfsloadkernel " \ - "flashargs add_default addpanic boot\0" \ + "subbootcmds=ubiattach ubicopy cramfsloadfdt set_fdthigh " \ + "cramfsloadkernel flashargs add_default addpanic boot\0"\ "develop=" \ "tftp 200000 scripts/develop-${arch}.txt && " \ "env import -t 200000 ${filesize} && " \ @@ -220,6 +226,7 @@ CONFIG_KM_DEF_ENV_FLASH_BOOT \ CONFIG_KM_DEF_ENV_CONSTANTS \ "altbootcmd=run bootcmd\0" \ + "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ "bootcmd=km_checkbidhwk && " \ "setenv bootcmd \'if km_checktestboot; then; " \ "setenv boot_bank ${test_bank}; else; " \ @@ -229,6 +236,10 @@ "run ${subbootcmds}; reset\' && " \ "saveenv && saveenv && boot\0" \ "bootlimit=3\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ + "fdt_addr_r="__stringify(CONFIG_KM_FDT_ADDR) "\0" \ "init=/sbin/init-overlay.sh\0" \ "load_addr_r="__stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ "load=tftpboot ${load_addr_r} ${u-boot}\0" \ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index 2cebb2b..763c5ba 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -70,11 +70,6 @@ #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" #define CONFIG_KM_DEF_ENV_CPU \ - "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ - "cramfsloadfdt=" \ - "cramfsload ${fdt_addr_r} " \ - "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ - "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ "update=" \ "protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\ @@ -82,6 +77,7 @@ "cp.b ${load_addr_r} " __stringify(BOOTFLASH_START) \ " ${filesize} && " \ "protect on " __stringify(BOOTFLASH_START) " +${filesize}\0"\ + "set_fdthigh=true\0" \ "" #endif /* __CONFIG_KEYMILE_POWERPC_H */ diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index e74f85f..6d77680 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -70,7 +70,8 @@ #define CONFIG_KM_PHRAM 0x17F000 #define CONFIG_KM_CRAMFS_ADDR 0x2400000 -#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */ +#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 3098KBytes */ +#define CONFIG_KM_FDT_ADDR 0x23E0000 /* 128KBytes */ /* architecture specific default bootargs */ #define CONFIG_KM_DEF_BOOT_ARGS_CPU \ @@ -78,15 +79,17 @@ " boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}" #define CONFIG_KM_DEF_ENV_CPU \ - "boot=bootm ${load_addr_r} - -\0" \ - "cramfsloadfdt=true\0" \ "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0" \ CONFIG_KM_UPDATE_UBOOT \ + "set_fdthigh=setenv fdt_high ${kernelmem}\0" \ "" #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #define CONFIG_MISC_INIT_R +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT + /* * NS16550 Configuration */ @@ -289,10 +292,15 @@ int get_scl(void); " ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0" #endif +#ifndef CONFIG_KM_BOARD_EXTRA_ENV +#define CONFIG_KM_BOARD_EXTRA_ENV "" +#endif + /* * Default environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_BOARD_EXTRA_ENV \ CONFIG_KM_DEF_ENV \ CONFIG_KM_NEW_ENV \ "arch=arm\0" \ diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 2466649..0d24f78 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -15,6 +15,10 @@ #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" +/* an additionnal option is required for UBI as subpage access is + * supported in u-boot */ +#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" + #define CONFIG_NAND_ECC_BCH /* common KM defines */ @@ -148,8 +152,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ -#define CONFIG_BOOTCOUNT_LIMIT - /* * Local Bus Definitions */ @@ -206,8 +208,13 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ +/* bootcounter in QRIO */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20) + #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_F #define CONFIG_MISC_INIT_R #define CONFIG_LAST_STAGE_INIT @@ -263,7 +270,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ /* I2C */ + #define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ #define CONFIG_SYS_NUM_I2C_BUSES 3 #define CONFIG_SYS_I2C_MAX_HOPS 1 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ @@ -276,6 +286,12 @@ unsigned long get_board_sys_clk(unsigned long dummy); {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ } +#ifndef __ASSEMBLY__ +void set_sda(int state); +void set_scl(int state); +int get_sda(void); +int get_scl(void); +#endif #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ @@ -286,6 +302,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ #define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE 0 @@ -420,6 +437,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); "update=" \ "sf probe 0;sf erase 0 +${filesize};" \ "sf write ${load_addr_r} 0 ${filesize};\0" \ + "set_fdthigh=true\0" \ "" #define CONFIG_HW_ENV_SETTINGS \ diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 74c7232..2cde177 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -45,11 +45,19 @@ #define CONFIG_KM_DISABLE_PCIE #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ -/* KM_NUSA */ -#elif defined(CONFIG_KM_NUSA) +/* KM_NUSA / KM_SUGP1 */ +#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1) #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ + +# if defined(CONFIG_KM_NUSA) #define CONFIG_IDENT_STRING "\nKeymile NUSA" #define CONFIG_HOSTNAME kmnusa +# elif defined(CONFIG_KM_SUGP1) +#define CONFIG_IDENT_STRING "\nKeymile SUGP1" +#define CONFIG_HOSTNAME kmsugp1 +#define KM_PCIE_RESET_MPP7 +#endif + #undef CONFIG_SYS_KWD_CONFIG #define CONFIG_SYS_KWD_CONFIG \ $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg @@ -97,6 +105,9 @@ #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ #define CONFIG_IDENT_STRING "\nKeymile SUV31" #define CONFIG_HOSTNAME kmsuv31 +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \ + $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg #define CONFIG_KM_ENV_IS_IN_SPI_NOR #define CONFIG_KM_FPGA_CONFIG diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h index 4158c8d..8bb3571 100644 --- a/include/configs/kmp204x.h +++ b/include/configs/kmp204x.h @@ -13,6 +13,11 @@ #define CONFIG_HOSTNAME kmlion1 #define CONFIG_KM_BOARD_NAME "kmlion1" +/* KMCOGE4 */ +#elif defined(CONFIG_KMCOGE4) +#define CONFIG_HOSTNAME kmcoge4 +#define CONFIG_KM_BOARD_NAME "kmcoge4" + #else #error ("Board not supported") #endif @@ -42,6 +47,7 @@ #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_LBAPP1_BR_PRELIM /* Local bus app1 Options */ #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_LBAPP1_OR_PRELIM +#endif /* App2 Local bus */ #define CONFIG_SYS_LBAPP2_BASE 0xE0000000 @@ -63,6 +69,5 @@ #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM /* Local bus app2 Options */ #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index aa8d59d..486787e 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -200,7 +200,8 @@ # define CONFIG_SYS_MAX_FLASH_SECT 512 /* hardware flash protection */ # define CONFIG_SYS_FLASH_PROTECTION - +/* use buffered writes (20x faster) */ +# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 # ifdef RAMENV # define CONFIG_ENV_IS_NOWHERE 1 # define CONFIG_ENV_SIZE 0x1000 @@ -446,4 +447,64 @@ # undef CONFIG_PHYLIB #endif +/* SPL part */ +#define CONFIG_SPL +#define CONFIG_CMD_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT + +#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds" + +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_NOR_SUPPORT + +/* for booting directly linux */ +#define CONFIG_SPL_OS_BOOT + +#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \ + 0x60000) +#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ + 0x40000) +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ + 0x1000000) + +/* SP location before relocation, must use scratch RAM */ +/* BRAM start */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x0 +/* BRAM size - will be generated */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +/* Stack pointer prior relocation, must situated at on-chip RAM */ +#define CONFIG_SYS_SPL_MALLOC_END (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100 + +/* + * The main reason to do it in this way is that MALLOC_START + * can't be defined - common/spl/spl.c + */ +#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0) +# define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_SPL_MALLOC_END - \ + CONFIG_SYS_SPL_MALLOC_SIZE) +# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_START +#else +# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_END +#endif + +/* Just for sure that there is a space for stack */ +#define CONFIG_SPL_STACK_SIZE 0x100 + +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ + CONFIG_SYS_INIT_RAM_ADDR - \ + GENERATED_GBL_DATA_SIZE - \ + CONFIG_SYS_SPL_MALLOC_SIZE - \ + CONFIG_SPL_STACK_SIZE) + #endif /* __CONFIG_H */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index f4ff5cd..e44ec88 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -31,7 +31,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MISC_INIT_R #define CONFIG_MXC_GPIO -#define CONFIG_MV_UDC +#define CONFIG_CI_UDC #define CONFIG_USBD_HS #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 51dff23..783b7c3 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -37,6 +37,7 @@ #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART #define CONFIG_HSMMC2_8BIT +#define CONFIG_SUPPORT_EMMC_BOOT /* Required support for the TCA642X GPIO we have on the uEVM */ #define CONFIG_TCA642X diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h index 0b7add7..976ceaa 100644 --- a/include/configs/rpi_b.h +++ b/include/configs/rpi_b.h @@ -123,6 +123,7 @@ "scriptaddr=0x00000000\0" \ "kernel_addr_r=0x01000000\0" \ "fdt_addr_r=0x02000000\0" \ + "fdtfile=bcm2835-rpi-b.dtb\0" \ "ramdisk_addr_r=0x02100000\0" \ "boot_targets=mmc0\0" \ \ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 0590d20..991c43e 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -34,6 +34,7 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING @@ -113,8 +114,13 @@ #define CONFIG_UBIFS_OPTION "rootflags=bulk_read,no_chk_data_crc" +#define CONFIG_MISC_COMMON +#define CONFIG_MISC_INIT_R + #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_UPDATEB \ "updatek=" \ @@ -208,8 +214,8 @@ /* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get_nr(j4, 3) -#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get_nr(j4, 0) +#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get(j4, 3) +#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get(j4, 0) #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index d9e4c56..67921e9 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -124,6 +124,9 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + #define CONFIG_EXTRA_ENV_SETTINGS \ "updateb=" \ "onenand erase 0x0 0x100000;" \ @@ -229,8 +232,8 @@ /* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6) +#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7) +#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6) #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ @@ -253,10 +256,10 @@ */ #define CONFIG_SOFT_SPI #define CONFIG_SOFT_SPI_MODE SPI_MODE_3 -#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_part2_get_nr(y3, 1) -#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_part2_get_nr(y3, 3) -#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_part2_get_nr(y3, 0) -#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_part2_get_nr(y4, 3) +#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_get(2, y3, 1) +#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_get(2, y3, 3) +#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_get(2, y3, 0) +#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_get(2, y4, 3) #define SPI_DELAY udelay(1) #undef SPI_INIT @@ -269,16 +272,43 @@ void universal_spi_sda(int bit); int universal_spi_read(void); #endif +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +#define CONFIG_MISC_INIT_R + +/* Download menu - Samsung common */ +#define CONFIG_LCD_MENU +#define CONFIG_LCD_MENU_BOARD + +/* Download menu - definitions for check keys */ +#ifndef __ASSEMBLY__ +#include <power/max8998_pmic.h> + +#define KEY_PWR_PMIC_NAME "MAX8998_PMIC" +#define KEY_PWR_STATUS_REG MAX8998_REG_STATUS1 +#define KEY_PWR_STATUS_MASK (1 << 7) +#define KEY_PWR_INTERRUPT_REG MAX8998_REG_IRQ1 +#define KEY_PWR_INTERRUPT_MASK (1 << 7) + +#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0) +#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1) +#endif /* __ASSEMBLY__ */ + +/* LCD console */ +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK + /* * LCD Settings */ #define CONFIG_EXYNOS_FB #define CONFIG_LCD #define CONFIG_CMD_BMP -#define CONFIG_BMP_32BPP +#define CONFIG_BMP_16BPP #define CONFIG_LD9040 #define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((520 * 120 * 4) + (1 << 12)) +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #endif /* __CONFIG_H */ diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h index a85eb1c..8cce34a 100644 --- a/include/configs/sansa_fuze_plus.h +++ b/include/configs/sansa_fuze_plus.h @@ -56,7 +56,7 @@ #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */ +#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 23f7ad7..e090a37 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -17,11 +17,9 @@ /* Ethernet driver configuration */ #define CONFIG_MII #define CONFIG_DESIGNWARE_ETH -#define CONFIG_DW_SEARCH_PHY -#define CONFIG_DW0_PHY 1 #define CONFIG_NET_MULTI +#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ -#define CONFIG_DW_AUTONEG #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ /* USBD driver configuration */ diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h index 7f4dc58..28dddcc 100644 --- a/include/configs/spear6xx_evb.h +++ b/include/configs/spear6xx_evb.h @@ -37,6 +37,9 @@ #define CONFIG_SYS_FSMC_NAND_8BIT #define CONFIG_SYS_NAND_BASE 0xD2000000 +/* Ethernet PHY configuration */ +#define CONFIG_PHY_NATSEMI + /* Environment Settings */ #define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index a3242fe..e1a3bbc 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -99,6 +99,7 @@ BOOTCMDS_DHCP #define CONFIG_BOOTCOMMAND \ + "set usb_need_init; " \ "for target in ${boot_targets}; do run bootcmd_${target}; done" #endif @@ -129,10 +130,15 @@ "stderr=serial" STDOUT_LCD "\0" \ "" +#ifndef BOARD_EXTRA_ENV_SETTINGS +#define BOARD_EXTRA_ENV_SETTINGS +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ - BOOTCMDS_COMMON + BOOTCMDS_COMMON \ + BOARD_EXTRA_ENV_SETTINGS #if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) #define CONFIG_FDT_SPI diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h new file mode 100644 index 0000000..0a4541b --- /dev/null +++ b/include/configs/tegra124-common.h @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA124_COMMON_H_ +#define _TEGRA124_COMMON_H_ + +#include "tegra-common.h" + +/* Cortex-A15 uses a cache line size of 64 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ + +/* + * High Level Configuration Options + */ +#define CONFIG_TEGRA124 /* is an NVIDIA Tegra124 core */ + +/* Environment information, boards can override if required */ +#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ +#define CONFIG_STACKBASE 0x82800000 /* 40MB */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_SYS_TEXT_BASE 0x8010E000 + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x82100000\0" + +/* Defines for SPL */ +#define CONFIG_SPL_TEXT_BASE 0x80108000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 +#define CONFIG_SPL_STACK 0x800ffffc + +/* Total I2C ports on Tegra124 */ +#define TEGRA_I2C_NUM_CONTROLLERS 5 + +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 + +#endif /* _TEGRA124_COMMON_H_ */ diff --git a/include/configs/trats.h b/include/configs/trats.h index fdd8b46..718107a 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -147,15 +147,23 @@ ""PARTS_BOOT" part 0 2;" \ ""PARTS_ROOT" part 0 5;" \ ""PARTS_DATA" part 0 6;" \ - ""PARTS_UMS" part 0 7\0" + ""PARTS_UMS" part 0 7;" \ + "params.bin mmc 0x38 0x8\0" #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ - "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ + "run loaduimage;" \ + "if run loaddtb; then " \ + "bootm 0x40007FC0 - ${fdtaddr};" \ + "fi;" \ + "bootm 0x40007FC0;\0" \ "updatemmc=" \ "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \ "mmc boot 0 1 1 0\0" \ @@ -178,7 +186,7 @@ "mmcboot=" \ "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ - "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ + "run bootk\0" \ "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \ "boottrace=setenv opts initcall_debug; run bootcmd\0" \ "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ @@ -217,7 +225,6 @@ "setenv spl_imgaddr;" \ "setenv spl_addr_tmp;\0" \ "fdtaddr=40800000\0" \ - "fdtfile=exynos4210-trats.dtb\0" /* Miscellaneous configurable options */ @@ -287,8 +294,8 @@ #include <asm/arch/gpio.h> /* I2C FG */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part2_get_nr(y4, 1) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part2_get_nr(y4, 0) +#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1) +#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0) #define CONFIG_POWER #define CONFIG_POWER_I2C @@ -306,16 +313,43 @@ #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_USB_CABLE_CHECK +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +#define CONFIG_MISC_INIT_R + +/* Download menu - Samsung common */ +#define CONFIG_LCD_MENU +#define CONFIG_LCD_MENU_BOARD + +/* Download menu - definitions for check keys */ +#ifndef __ASSEMBLY__ +#include <power/max8997_pmic.h> + +#define KEY_PWR_PMIC_NAME "MAX8997_PMIC" +#define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1 +#define KEY_PWR_STATUS_MASK (1 << 0) +#define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 +#define KEY_PWR_INTERRUPT_MASK (1 << 0) + +#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0) +#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1) +#endif /* __ASSEMBLY__ */ + +/* LCD console */ +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK + /* LCD */ #define CONFIG_EXYNOS_FB #define CONFIG_LCD #define CONFIG_CMD_BMP -#define CONFIG_BMP_32BPP +#define CONFIG_BMP_16BPP #define CONFIG_FB_ADDR 0x52504000 #define CONFIG_S6E8AX0 #define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12)) +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_GADGET_MASS_STORAGE diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 83633b0..e30c428 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -152,6 +152,9 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + /* Tizen - partitions definitions */ #define PARTS_CSA "csa" #define PARTS_BOOT "boot" @@ -178,11 +181,16 @@ ""PARTS_BOOT" part 0 2;" \ ""PARTS_ROOT" part 0 5;" \ ""PARTS_DATA" part 0 6;" \ - ""PARTS_UMS" part 0 7\0" + ""PARTS_UMS" part 0 7;" \ + "params.bin mmc 0x38 0x8\0" #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ - "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ + "run loaduimage;" \ + "if run loaddtb; then " \ + "bootm 0x40007FC0 - ${fdtaddr};" \ + "fi;" \ + "bootm 0x40007FC0;\0" \ "updatemmc=" \ "mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \ "mmc boot 0 1 1 0\0" \ @@ -196,7 +204,7 @@ "mmcboot=" \ "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ - "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ + "run bootk\0" \ "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ "boottrace=setenv opts initcall_debug; run bootcmd\0" \ "verify=n\0" \ @@ -237,7 +245,6 @@ "setenv spl_imgaddr;" \ "setenv spl_addr_tmp;\0" \ "fdtaddr=40800000\0" \ - "fdtfile=exynos4412-trats2.dtb\0" /* * Miscellaneous configurable options @@ -277,7 +284,6 @@ #define CONFIG_EFI_PARTITION #define CONFIG_PARTITION_UUIDS -#define CONFIG_MISC_INIT_R #define CONFIG_BOARD_EARLY_INIT_F /* I2C */ @@ -318,16 +324,43 @@ int get_soft_i2c_sda_pin(void); #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_USB_CABLE_CHECK +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +#define CONFIG_MISC_INIT_R + +/* Download menu - Samsung common */ +#define CONFIG_LCD_MENU +#define CONFIG_LCD_MENU_BOARD + +/* Download menu - definitions for check keys */ +#ifndef __ASSEMBLY__ +#include <power/max77686_pmic.h> + +#define KEY_PWR_PMIC_NAME "MAX77686_PMIC" +#define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1 +#define KEY_PWR_STATUS_MASK (1 << 0) +#define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1 +#define KEY_PWR_INTERRUPT_MASK (1 << 1) + +#define KEY_VOL_UP_GPIO exynos4x12_gpio_get(2, x2, 2) +#define KEY_VOL_DOWN_GPIO exynos4x12_gpio_get(2, x3, 3) +#endif /* __ASSEMBLY__ */ + +/* LCD console */ +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK + /* LCD */ #define CONFIG_EXYNOS_FB #define CONFIG_LCD #define CONFIG_CMD_BMP -#define CONFIG_BMP_32BPP +#define CONFIG_BMP_16BPP #define CONFIG_FB_ADDR 0x52504000 #define CONFIG_S6E8AX0 #define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 250 * 4) + (1 << 12)) +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_GADGET_MASS_STORAGE diff --git a/include/configs/venice2.h b/include/configs/venice2.h new file mode 100644 index 0000000..91808e9 --- /dev/null +++ b/include/configs/venice2.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2013-2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/sizes.h> + +#include "tegra124-common.h" + +/* Enable fdt support for Venice2. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra124-venice2 +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra124 (Venice2) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/x600.h b/include/configs/x600.h index 39540e3..00b938a 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -74,10 +74,9 @@ /* Ethernet config options */ #define CONFIG_MII #define CONFIG_DESIGNWARE_ETH -#define CONFIG_DW_SEARCH_PHY #define CONFIG_NET_MULTI +#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ -#define CONFIG_DW_AUTONEG #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h index 022bc95..8e6b365 100644 --- a/include/configs/xfi3.h +++ b/include/configs/xfi3.h @@ -55,7 +55,7 @@ #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */ +#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index e7a8e9f..9b6db04 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -164,7 +164,7 @@ "fatload mmc 0 ${load_addr} ${fit_image} && " \ "bootm ${load_addr}\0" \ "jtagboot=echo TFTPing FIT to RAM... && " \ - "tftp ${load_addr} ${fit_image} && " \ + "tftpboot ${load_addr} ${fit_image} && " \ "bootm ${load_addr}\0" #define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */ @@ -228,6 +228,8 @@ # define CONFIG_SYS_MMC_MAX_DEVICE 1 #endif +#define CONFIG_SYS_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot.lds" + /* Commands */ #include <config_cmd_default.h> |