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-rw-r--r--include/configs/bf537-stamp.h44
-rw-r--r--include/configs/bfin_adi_common.h3
-rw-r--r--include/configs/blackstamp.h9
-rw-r--r--include/configs/canyonlands.h2
-rw-r--r--include/configs/cm-bf561.h5
-rw-r--r--include/configs/smdk6400.h3
6 files changed, 35 insertions, 31 deletions
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 0a86e83..98300db 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -151,36 +151,28 @@
/*
* NAND Settings
*/
-/* #define CONFIG_BF537_NAND */
-#ifdef CONFIG_BF537_NAND
-# define CONFIG_CMD_NAND
-#endif
-
-#define CONFIG_SYS_NAND_ADDR 0x20212000
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND_ADDR
+/* #define CONFIG_NAND_PLAT */
+#define CONFIG_SYS_NAND_BASE 0x20212000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define SECTORSIZE 512
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define BFIN_NAND_READY PF3
-
-#define NAND_WAIT_READY(nand) \
+
+#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
+#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
+#define BFIN_NAND_READY PF3
+#define BFIN_NAND_WRITE(addr, cmd) \
do { \
- int timeout = 0; \
- while (!(*pPORTFIO & PF3)) \
- if (timeout++ > 100000) \
- break; \
+ bfin_write8(addr, cmd); \
+ SSYNC(); \
} while (0)
-#define BFIN_NAND_CLE (1 << 2) /* A2 -> Command Enable */
-#define BFIN_NAND_ALE (1 << 1) /* A1 -> Address Enable */
-#define WRITE_NAND_COMMAND(d, adr) bfin_write8(adr | BFIN_NAND_CLE, d)
-#define WRITE_NAND_ADDRESS(d, adr) bfin_write8(adr | BFIN_NAND_ALE, d)
-#define WRITE_NAND(d, adr) bfin_write8(adr, d)
-#define READ_NAND(adr) bfin_read8(adr)
+#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
+#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
+#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTFIO() & BFIN_NAND_READY)
+#define NAND_PLAT_INIT() \
+ do { \
+ bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~BFIN_NAND_READY); \
+ bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~BFIN_NAND_READY); \
+ bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | BFIN_NAND_READY); \
+ } while (0)
/*
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 4149a29..1ca2e51 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -38,6 +38,9 @@
# define CONFIG_CMD_USB_STORAGE
# define CONFIG_DOS_PARTITION
# endif
+# ifdef CONFIG_NAND_PLAT
+# define CONFIG_CMD_NAND
+# endif
# ifdef CONFIG_POST
# define CONFIG_CMD_DIAG
# endif
diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h
index 1e4c716..887f3fb 100644
--- a/include/configs/blackstamp.h
+++ b/include/configs/blackstamp.h
@@ -83,10 +83,9 @@
#endif
#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x4000
+#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x40000
-#define ENV_IS_EMBEDDED_CUSTOM
/*
* SDRAM settings & memory map
@@ -245,9 +244,9 @@
* Serial Flash Infomation
*/
#define CONFIG_BFIN_SPI
-/* For the M25P64 SCK Should be Kept < 20Mhz */
-#define CONFIG_ENV_SPI_MAX_HZ 20000000
-#define CONFIG_SF_DEFAULT_SPEED 20000000
+/* For the M25P64 SCK Should be Kept < 15Mhz */
+#define CONFIG_ENV_SPI_MAX_HZ 15000000
+#define CONFIG_SF_DEFAULT_SPEED 15000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index d814012..48c5198 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -132,9 +132,11 @@
*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
#else
#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
+#define CONFIG_SYS_NOR_CS 3 /* NOR chip connected to CSx */
#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
#endif
diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h
index 53a2580..1153f11 100644
--- a/include/configs/cm-bf561.h
+++ b/include/configs/cm-bf561.h
@@ -60,8 +60,13 @@
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
+/* The next 2 lines are for use with DEV-BF5xx */
#define CONFIG_DRIVER_SMC91111 1
#define CONFIG_SMC91111_BASE 0x28000300
+/* The next 3 lines are for use with EXT-BF5xx-USB-ETH2 */
+/* #define CONFIG_DRIVER_SMC911X 1 */
+/* #define CONFIG_DRIVER_SMC911X_BASE 0x24080000 // AMS1 */
+/* #define CONFIG_DRIVER_SMC911X_32_BIT 1 */
#define CONFIG_HOSTNAME cm-bf561
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:cf */
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index cac58cf..018f576 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -209,6 +209,9 @@
/* total memory available to uboot */
#define CONFIG_SYS_UBOOT_SIZE (1024 * 1024)
+/* Put environment copies after the end of U-Boot owned RAM */
+#define CONFIG_NAND_ENV_DST (CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE)
+
#ifdef CONFIG_ENABLE_MMU
#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000
#define CONFIG_BOOTCOMMAND "nand read 0xc0018000 0x60000 0x1c0000;" \