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-rw-r--r--include/configs/ATUM8548.h2
-rw-r--r--include/configs/DU440.h438
-rw-r--r--include/configs/MPC8349EMDS.h9
-rw-r--r--include/configs/MPC8540ADS.h1
-rw-r--r--include/configs/MPC8540EVAL.h2
-rw-r--r--include/configs/MPC8541CDS.h1
-rw-r--r--include/configs/MPC8544DS.h2
-rw-r--r--include/configs/MPC8548CDS.h1
-rw-r--r--include/configs/MPC8555CDS.h1
-rw-r--r--include/configs/MPC8560ADS.h1
-rw-r--r--include/configs/MPC8568MDS.h1
-rw-r--r--include/configs/MPC8610HPCD.h1
-rw-r--r--include/configs/MPC8641HPCN.h1
-rw-r--r--include/configs/PM854.h1
-rw-r--r--include/configs/PM856.h1
-rw-r--r--include/configs/PMC440.h4
-rw-r--r--include/configs/SBC8540.h1
-rw-r--r--include/configs/TQM85xx.h2
-rw-r--r--include/configs/hcu4.h115
-rw-r--r--include/configs/hcu5.h136
-rw-r--r--include/configs/kilauea.h2
-rw-r--r--include/configs/makalu.h2
-rw-r--r--include/configs/sbc8548.h1
-rw-r--r--include/configs/sbc8560.h1
-rw-r--r--include/configs/stxgp3.h1
-rw-r--r--include/configs/stxssa.h1
26 files changed, 626 insertions, 103 deletions
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index f7020b4..c14376e 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -63,6 +63,8 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
#define CONFIG_SYS_CLK_FREQ 33000000
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
new file mode 100644
index 0000000..4fb6921
--- /dev/null
+++ b/include/configs/DU440.h
@@ -0,0 +1,438 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
+ *
+ * based on the Sequoia board configuration by
+ * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ **********************************************************************
+ * DU440.h - configuration for esd's DU440 board (Power PC440EPx)
+ **********************************************************************
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_DU440 1 /* Board is esd DU440 */
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
+
+#define CFG_BOOT_BASE_ADDR 0xf0000000
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_NAND0_ADDR 0xd0000000 /* NAND Flash */
+#define CFG_NAND1_ADDR 0xd0100000 /* NAND Flash */
+#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+#define CFG_PCI_IOBASE 0xe8000000
+
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+
+#define CFG_USB2D0_BASE 0xe0000100
+#define CFG_USB_DEVICE 0xe0000000
+#define CFG_USB_HOST 0xe0000400
+
+/*
+ * Initial RAM & stack pointer
+ */
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
+#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*
+ * Serial Port
+ */
+/* TODO: external clock oscillator will be removed */
+#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Video Port
+ */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SMI_LYNXEM
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
+#define CFG_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
+#define CFG_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
+#define CFG_CONSOLE_IS_IN_ENV
+#define CFG_ISA_IO CFG_PCI_IOBASE
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
+
+/*
+ * FLASH related
+ */
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
+#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_OFFSET 0 /* environment starts at */
+ /* the beginning of the EEPROM */
+#define CFG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
+#endif
+
+/*
+ * DDR SDRAM
+ */
+#define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
+#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
+#if 0
+#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
+#endif
+#define CONFIG_DDR_ECC /* Use ECC when available */
+#define SPD_EEPROM_ADDRESS {0x50}
+#define CONFIG_PROG_SDRAM_TLB
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CONFIG_I2C_CMD_TREE 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+#define CFG_SPD_BUS_NUM 0
+#define IIC1_MCP3021_ADDR 0x4d
+#define IIC1_USB2507_ADDR 0x2c
+#ifdef CONFIG_I2C_MULTI_BUS
+#define CFG_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}}
+#endif
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR 0x54
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
+
+#define CFG_EEPROM_WREN 1
+#define CFG_I2C_BOOT_EEPROM_ADDR 0x52
+
+/*
+ * standard dtt sensor configuration - bottom bit will determine local or
+ * remote sensor of the TMP401
+ */
+#define CONFIG_DTT_SENSORS { 0, 1 }
+
+/*
+ * The PMC440 uses a TI TMP401 temperature sensor. This part
+ * is basically compatible to the ADM1021 that is supported
+ * by U-Boot.
+ *
+ * - i2c addr 0x4c
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT ouput disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
+ * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
+ */
+#define CONFIG_DTT_ADM1021
+#define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
+
+/*
+ * RTC stuff
+ */
+#define CONFIG_RTC_DS1338
+#define CFG_I2C_RTC_ADDR 0x68
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethrotate=no\0" \
+ "hostname=du440\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_self=run ramargs addip addtty optargs;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
+ "bootm\0" \
+ "rootpath=/tftpboot/du440/target_root_du440\0" \
+ "img=/tftpboot/du440/uImage\0" \
+ "kernel_addr=FFC00000\0" \
+ "ramdisk_addr=FFE00000\0" \
+ "initrd_high=30000000\0" \
+ "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
+ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
+ "cp.b 100000 FFFA0000 60000\0" \
+ ""
+#if 0
+#define CONFIG_BOOTCOMMAND "run flash_self"
+#endif
+
+#define CONFIG_PREBOOT /* enable preboot variable */
+
+#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#ifndef __ASSEMBLY__
+int du440_phy_addr(int devnum);
+#endif
+
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_GIGE 1 /* Include GbE detection */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 128
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR du440_phy_addr(1)
+
+/*
+ * USB
+ */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CFG_OHCI_BE_CONTROLLER
+
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST
+#define CFG_USB_OHCI_SLOT_NAME "du440"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * PCI stuff
+ */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+#define CFG_FLASH CFG_FLASH_BASE
+
+#define CFG_CPLD_BASE 0xC0000000
+#define CFG_CPLD_RANGE 0x00000010
+#define CFG_DUMEM_BASE 0xC0100000
+#define CFG_DUMEM_RANGE 0x00100000
+#define CFG_DUIO_BASE 0xC0200000
+#define CFG_DUIO_RANGE 0x00010000
+
+#define CFG_NAND0_CS 2 /* NAND chip connected to CSx */
+#define CFG_NAND1_CS 3 /* NAND chip connected to CSx */
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x04017200
+#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
+
+/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
+#define CFG_EBC_PB1AP 0x018003c0
+#define CFG_EBC_PB1CR (CFG_CPLD_BASE | 0x18000)
+
+/* Memory Bank 2 (NAND-FLASH) initialization */
+#define CFG_EBC_PB2AP 0x018003c0
+#define CFG_EBC_PB2CR (CFG_NAND0_ADDR | 0x1c000)
+
+/* Memory Bank 3 (NAND-FLASH) initialization */
+#define CFG_EBC_PB3AP 0x018003c0
+#define CFG_EBC_PB3CR (CFG_NAND1_ADDR | 0x1c000)
+
+/* Memory Bank 4 (DUMEM, 1MB) initialization */
+#define CFG_EBC_PB4AP 0x018053c0
+#define CFG_EBC_PB4CR (CFG_DUMEM_BASE | 0x18000)
+
+/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
+#define CFG_EBC_PB5AP 0x018053c0
+#define CFG_EBC_PB5CR (CFG_DUIO_BASE | 0x18000)
+
+/*
+ * NAND FLASH
+ */
+#define CFG_MAX_NAND_DEVICE 2
+#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
+#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+#define CFG_NAND_BASE_LIST {CFG_NAND0_ADDR + CFG_NAND0_CS, \
+ CFG_NAND1_ADDR + CFG_NAND1_CS}
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#if 0
+#define CONFIG_SHOW_ACTIVITY 1
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 437a9a5..07f2f30 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -355,6 +355,15 @@
#define CFG_I2C_OFFSET 0x3000
#define CFG_I2C2_OFFSET 0x3100
+/* SPI */
+#define CONFIG_HARD_SPI /* SPI with hardware support */
+#undef CONFIG_SOFT_SPI /* SPI bit-banged */
+
+/* GPIOs. Used as SPI chip selects */
+#define CFG_GPIO1_PRELIM
+#define CFG_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
+#define CFG_GPIO1_DAT 0xC0000000 /* Both are active LOW */
+
/* TSEC */
#define CFG_TSEC1_OFFSET 0x24000
#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index afce7fb..5ea7b25 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -55,6 +55,7 @@
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 2868dcb..bf64f27 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -43,6 +43,8 @@
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+
/* Using Localbus SDRAM to emulate flash before we can program the flash,
* normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
* Not availabe for EVAL board
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index c83382f..7334088 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -47,6 +47,7 @@
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* When initializing flash, if we cannot find the manufacturer ID,
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 5a96db5..a894209 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -42,6 +42,8 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 90beb25..a3db9f4 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -55,6 +55,7 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* When initializing flash, if we cannot find the manufacturer ID,
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 76d673c..93877ae 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -47,6 +47,7 @@
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* When initializing flash, if we cannot find the manufacturer ID,
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 5f10555..08884b3 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -52,6 +52,7 @@
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 2b089d9..a12d193 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -49,6 +49,7 @@
/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* When initializing flash, if we cannot find the manufacturer ID,
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index ac4b3e1..a53953c 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -493,6 +493,7 @@
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index ab875f0..985182f 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -555,6 +555,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index f0d0399..819bee7 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -51,6 +51,7 @@
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index ae2645c..8902f42 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -51,6 +51,7 @@
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 67bf4b1..e8b405a 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -385,7 +385,7 @@
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@@ -503,7 +503,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 3ca85b8..2bbfe9a 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -56,6 +56,7 @@
#undef CONFIG_PCI /* pci ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index f3b1a53..dd0654b 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -50,6 +50,8 @@
#define CONFIG_CPM2 1 /* has CPM2 */
#endif
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+
/*
* sysclk for MPC85xx
*
diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h
index b43b228..cb51406 100644
--- a/include/configs/hcu4.h
+++ b/include/configs/hcu4.h
@@ -46,8 +46,8 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
-#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
@@ -67,7 +67,7 @@
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
/*-----------------------------------------------------------------------
* Serial Port
@@ -82,8 +82,8 @@
* set Linux BASE_BAUD to 403200.
*/
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CONFIG_SERIAL_MULTI /* needed to be able to define
- CONFIG_SERIAL_SOFTWARE_FIFO */
+#define CONFIG_SERIAL_MULTI 1
+/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD 691200
@@ -101,12 +101,23 @@
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
+ * Flash
+ *----------------------------------------------------------------------*/
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#undef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_IS_IN_FLASH
#undef CFG_ENV_IS_NOWHERE
#ifdef CFG_ENV_IS_IN_EEPROM
@@ -120,7 +131,7 @@
/* Put the environment in Flash */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
@@ -158,7 +169,7 @@
/* Setup some board specific values for the default environment variables */
#define CONFIG_HOSTNAME hcu4
-#define CONFIG_IPADDR 172.25.1.42
+#define CONFIG_IPADDR 172.25.1.99
#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_SERVERIP 172.25.1.3
@@ -180,21 +191,17 @@
"rootpath=/home/diagnose/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/hcu4/uImage\0" \
"load=tftp 100000 hcu4/u-boot.bin\0" \
- "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
- "cp.b 100000 FFFa0000 60000\0" \
+ "update=protect off FFFB0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \
+ "cp.b 100000 FFFB0000 50000\0" \
"upd=run load;run update\0" \
"vx=tftp ${loadaddr} hcu4_vx_rom;" \
- "setenv bootargs emac(0,0)hcu4_vx_rom e=${ipaddr} " \
- " h=${serverip} u=dpu pw=netstal8752 tn=hcu4 f=0x3008;" \
+ "vx=tftp ${loadaddr} hcu4/hcu4_vx_rom;" \
+ "setenv bootargs emac(0,0)c:hcu4/hcu4_vx_rom e=${ipaddr} " \
"bootvx ${loadaddr}\0" \
""
#define CONFIG_BOOTCOMMAND "run vx"
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
@@ -202,10 +209,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & desC */
/*
* BOOTP options
@@ -221,7 +228,6 @@
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BSP
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
@@ -241,15 +247,30 @@
#define CONFIG_SPD_EEPROM 1
#define SPD_EEPROM_ADDRESS 0x50
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_UART | \
+ CFG_POST_I2C | \
+ CFG_POST_CACHE | \
+ CFG_POST_ETHER | \
+ CFG_POST_SPR)
+
+#define CFG_POST_UART_TABLE {UART0_BASE}
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#undef CONFIG_LOGBUFFER
+#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
- #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
- #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
@@ -266,47 +287,40 @@
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CFG_EBC_PB0AP 0x02005400
-#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
+#define CFG_EBC_CFG 0x98400000
-#define CFG_EBC_PB1AP 0x03041200
-#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x02005400
+#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
-#define CFG_EBC_PB2AP 0x02054500
-#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+#define CFG_EBC_PB1AP 0x03041200
+#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
-#define CFG_EBC_PB3AP 0x01840300
-#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+#define CFG_EBC_PB2AP 0x02054500
+#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */
-#define CFG_EBC_PB4AP 0x01800300
-#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+#define CFG_EBC_PB3AP 0x01840300
+#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
-#define CFG_GPIO0_TCR 0x7ffe0000 /* GPIO value */
+#define CFG_EBC_PB4AP 0x01800300
+#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_GPIO0_OR 0xF27FFFFF /* GPIO value */
+#define CFG_GPIO0_TCR 0x7FFE0000 /* GPIO value */
+#define CFG_GPIO0_ODR 0x00E897FC /* GPIO value */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */
/* Init Memory Controller:
*
@@ -326,8 +340,8 @@
*
* Boot Flags
*/
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_HUSH_PARSER /* use "hush" command parser */
#ifdef CFG_HUSH_PARSER
@@ -338,4 +352,9 @@
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h
index 1214bc3..d66c47a 100644
--- a/include/configs/hcu5.h
+++ b/include/configs/hcu5.h
@@ -48,14 +48,16 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
-#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+#define CFG_TLB_FOR_BOOT_FLASH 3
#define CFG_BOOT_BASE_ADDR 0xfff00000
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
@@ -78,14 +80,15 @@
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#define CONFIG_BAUDRATE 9600
-#undef CONFIG_SERIAL_MULTI /* needed to be able to define
+#define CONFIG_SERIAL_MULTI 1
+/* needed to be able to define
CONFIG_SERIAL_SOFTWARE_FIFO, but
CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */
/* Size (bytes) of interrupt driven serial port buffer.
@@ -95,6 +98,7 @@
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CONFIG_UART1_CONSOLE
+#undef CONFIG_CMD_HWFLOW
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
@@ -103,8 +107,8 @@
*----------------------------------------------------------------------*/
#undef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_EEPROM
#undef CFG_ENV_IS_NOWHERE
#ifdef CFG_ENV_IS_IN_EEPROM
@@ -117,22 +121,28 @@
#ifdef CFG_ENV_IS_IN_FLASH
/* Put the environment in Flash */
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
#endif
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
-#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
-#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
-#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
-#define CONFIG_DDR_ECC 1 /* enable ECC */
+#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
+#define CFG_DDR_CACHED_ADDR 0x50000000 /* setup 2nd TLB cached here */
+#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
+#define CONFIG_DDR_ECC 1 /* enable ECC */
+
+/* Following two definitions must be kept in sync with config.h of vxWorks */
+#define USER_RESERVED_MEM ( 0) /* in kB */
+#define PM_RESERVED_MEM ( 64) /* in kB: pmLib reserved area size */
+#define CONFIG_PRAM ( USER_RESERVED_MEM + PM_RESERVED_MEM )
/*-----------------------------------------------------------------------
* I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
@@ -165,8 +175,8 @@
/* Setup some board specific values for the default environment variables */
#define CONFIG_HOSTNAME hcu5
-#define CONFIG_IPADDR 172.25.1.42
-#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
+#define CONFIG_IPADDR 172.25.1.99
+#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_SERVERIP 172.25.1.3
@@ -187,21 +197,27 @@
"bootfile=hcu5/uImage\0" \
"rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
"load=tftp 100000 hcu5/u-boot.bin\0" \
- "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
- "cp.b 100000 FFFa0000 60000\0" \
+ "update=protect off FFFb0000 FFFFFFFF;era FFFb0000 FFFFFFFF;" \
+ "cp.b 100000 FFFb0000 50000\0" \
"upd=run load;run update\0" \
- "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \
- "setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \
- " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \
- "bootvx ${loadaddr}\0" \
+ "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom; run vxboot\0" \
+ "vxusb=usb start; fatload usb 0 ${loadaddr} vxWorks.st; run vxboot\0" \
+ "vxargs=emac(0,0)c:hcu5/hcu5_vx_rom e=${ipaddr} h=${serverip}" \
+ " u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \
+ "vxboot=setenv bootargs $(vxargs); bootvx ${loadaddr}\0" \
+ "usbargs=setenv bootargs root=/dev/sda1 ro\0" \
+ "linux=usb start; ext2load usb 0 ${loadaddr} /boot/uImage;" \
+ "run usbargs addip addtty; bootm\0" \
+ "net_nfs_fdt=tftp 200000 ${bootfile};" \
+ "tftp ${fdt_addr} ${fdt_file};" \
+ "run nfsargs addip addtty;" \
+ "bootm 200000 - ${fdt_addr}\0" \
+ "fdt_file=hcu5/hcu5.dtb\0" \
+ "fdt_addr=400000\0" \
""
#define CONFIG_BOOTCOMMAND "run vx"
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
@@ -214,7 +230,7 @@
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & desc. */
#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
@@ -246,7 +262,6 @@
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BSP
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
@@ -264,6 +279,21 @@
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_USB
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_UART | \
+ CFG_POST_I2C | \
+ CFG_POST_CACHE | \
+ CFG_POST_FPU | \
+ CFG_POST_ETHER | \
+ CFG_POST_SPR)
+#define CFG_POST_UART_TABLE {UART0_BASE}
+
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
#define CONFIG_SUPPORT_VFAT
/*-----------------------------------------------------------------------
@@ -276,7 +306,7 @@
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
@@ -291,17 +321,16 @@
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* PCI stuff
*----------------------------------------------------------------------*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI 1 /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr map to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT
@@ -315,7 +344,17 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Flash
+ *----------------------------------------------------------------------*/
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
@@ -324,40 +363,30 @@
#define CFG_CS_1 0xC8000000 /* CAN */
#define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */
#define CFG_CPLD CFG_CS_2
-#define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */
+#define CFG_CS_3 0xCE000000 /* CPLD and IMC-Bus Fast */
-/*-----------------------------------------------------------------------
- * FLASH organization
- * Memory Bank 0 (BOOT-FLASH) initialization
- */
-#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */
+#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */
#define CFG_EBC_PB0AP 0x02005400
#define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH | 0xda000) */
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
-
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/* Memory Bank 1 CAN-Chips initialization */
+/* Memory Bank 1 CAN-Chips initialization */
#define CFG_EBC_PB1AP 0x02054500
#define CFG_EBC_PB1CR 0xC8018000
-/* Memory Bank 2 CPLD/IMC-Bus standard initialization */
+/* Memory Bank 2 CPLD/IMC-Bus standard initialization */
#define CFG_EBC_PB2AP 0x01840300
#define CFG_EBC_PB2CR 0xCC0BA000
-/* Memory Bank 3 IMC-Bus fast mode initialization */
+/* Memory Bank 3 IMC-Bus fast mode initialization */
#define CFG_EBC_PB3AP 0x01800300
#define CFG_EBC_PB3CR 0xCE0BA000
-/* Memory Bank 4 (not used) initialization */
+/* Memory Bank 4 (not used) initialization */
#undef CFG_EBC_PB4AP
#undef CFG_EBC_PB4CR
-/* Memory Bank 5 (not used) initialization */
+/* Memory Bank 5 (not used) initialization */
#undef CFG_EBC_PB5AP
#undef CFG_EBC_PB5CR
@@ -369,8 +398,8 @@
*
* Boot Flags
*/
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_HUSH_PARSER /* use "hush" command parser */
#ifdef CFG_HUSH_PARSER
@@ -381,4 +410,9 @@
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index f3e8601..a1d1533 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -476,7 +476,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index 8f8e867..2f0b0a8 100644
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -385,7 +385,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index c050a06..0a7a904 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -56,6 +56,7 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index b71ba78..f9ede5f 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -50,6 +50,7 @@
#undef CONFIG_PCI /* pci ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 3baa32c..047e1cf 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -51,6 +51,7 @@
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/* sysclk for MPC85xx
*/
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 9457bce..e09dd71 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -51,6 +51,7 @@
#undef CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/* sysclk for MPC85xx
*/
generated by cgit v1.1 at 2024-11-05 14:18:19 +0000