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-rw-r--r--include/configs/A3000.h1
-rw-r--r--include/configs/APC405.h1
-rw-r--r--include/configs/AR405.h1
-rw-r--r--include/configs/ASH405.h1
-rw-r--r--include/configs/B4860QDS.h36
-rw-r--r--include/configs/BSC9131RDB.h62
-rw-r--r--include/configs/BSC9132QDS.h64
-rw-r--r--include/configs/CATcenter.h1
-rw-r--r--include/configs/CPC45.h1
-rw-r--r--include/configs/CPCI2DP.h1
-rw-r--r--include/configs/CPCI405.h1
-rw-r--r--include/configs/CPCI4052.h1
-rw-r--r--include/configs/CPCI405AB.h1
-rw-r--r--include/configs/CPCI405DT.h1
-rw-r--r--include/configs/CPCIISER4.h1
-rw-r--r--include/configs/CPU87.h1
-rw-r--r--include/configs/CU824.h1
-rw-r--r--include/configs/DU440.h1
-rw-r--r--include/configs/ELPPC.h1
-rw-r--r--include/configs/G2000.h1
-rw-r--r--include/configs/HH405.h1
-rw-r--r--include/configs/HIDDEN_DRAGON.h1
-rw-r--r--include/configs/HWW1U1A.h1
-rw-r--r--include/configs/JSE.h1
-rw-r--r--include/configs/KAREF.h1
-rw-r--r--include/configs/MERGERBOX.h1
-rw-r--r--include/configs/METROBOX.h1
-rw-r--r--include/configs/MIP405.h1
-rw-r--r--include/configs/MOUSSE.h1
-rw-r--r--include/configs/MPC8260ADS.h1
-rw-r--r--include/configs/MPC8266ADS.h1
-rw-r--r--include/configs/MPC8308RDB.h1
-rw-r--r--include/configs/MPC8313ERDB.h1
-rw-r--r--include/configs/MPC8315ERDB.h1
-rw-r--r--include/configs/MPC8323ERDB.h1
-rw-r--r--include/configs/MPC832XEMDS.h1
-rw-r--r--include/configs/MPC8349EMDS.h1
-rw-r--r--include/configs/MPC8349ITX.h1
-rw-r--r--include/configs/MPC8360EMDS.h1
-rw-r--r--include/configs/MPC8360ERDK.h1
-rw-r--r--include/configs/MPC837XEMDS.h1
-rw-r--r--include/configs/MPC837XERDB.h1
-rw-r--r--include/configs/MPC8536DS.h1
-rw-r--r--include/configs/MPC8540ADS.h1
-rw-r--r--include/configs/MPC8541CDS.h1
-rw-r--r--include/configs/MPC8544DS.h1
-rw-r--r--include/configs/MPC8548CDS.h1
-rw-r--r--include/configs/MPC8555CDS.h1
-rw-r--r--include/configs/MPC8560ADS.h1
-rw-r--r--include/configs/MPC8568MDS.h1
-rw-r--r--include/configs/MPC8569MDS.h1
-rw-r--r--include/configs/MPC8572DS.h1
-rw-r--r--include/configs/MPC8610HPCD.h1
-rw-r--r--include/configs/MPC8641HPCN.h1
-rw-r--r--include/configs/MUSENKI.h1
-rw-r--r--include/configs/MVBLM7.h1
-rw-r--r--include/configs/MVBLUE.h1
-rw-r--r--include/configs/OCRTC.h1
-rw-r--r--include/configs/ORSG.h1
-rw-r--r--include/configs/P1010RDB.h78
-rw-r--r--include/configs/P1022DS.h3
-rw-r--r--include/configs/P1023RDB.h401
-rw-r--r--include/configs/P1023RDS.h1
-rw-r--r--include/configs/P1_P2_RDB.h1
-rw-r--r--include/configs/P2020COME.h1
-rw-r--r--include/configs/P2020DS.h1
-rw-r--r--include/configs/P2041RDB.h2
-rw-r--r--include/configs/P3041DS.h2
-rw-r--r--include/configs/P4080DS.h2
-rw-r--r--include/configs/P5020DS.h2
-rw-r--r--include/configs/PCI405.h1
-rw-r--r--include/configs/PIP405.h1
-rw-r--r--include/configs/PLU405.h1
-rw-r--r--include/configs/PM826.h1
-rw-r--r--include/configs/PM828.h1
-rw-r--r--include/configs/PMC405.h1
-rw-r--r--include/configs/PMC405DE.h1
-rw-r--r--include/configs/PMC440.h1
-rw-r--r--include/configs/PN62.h1
-rw-r--r--include/configs/PPChameleonEVB.h1
-rw-r--r--include/configs/SIMPC8313.h1
-rw-r--r--include/configs/Sandpoint8240.h1
-rw-r--r--include/configs/Sandpoint8245.h1
-rw-r--r--include/configs/TQM8272.h1
-rw-r--r--include/configs/TQM834x.h1
-rw-r--r--include/configs/VOH405.h1
-rw-r--r--include/configs/W7OLMC.h1
-rw-r--r--include/configs/W7OLMG.h1
-rw-r--r--include/configs/WUH405.h1
-rw-r--r--include/configs/a3m071.h1
-rw-r--r--include/configs/adp-ag102.h1
-rw-r--r--include/configs/alpr.h1
-rw-r--r--include/configs/am335x_evm.h36
-rw-r--r--include/configs/aria.h1
-rw-r--r--include/configs/atc.h1
-rw-r--r--include/configs/bamboo.h1
-rw-r--r--include/configs/beaver.h2
-rw-r--r--include/configs/bubinga.h1
-rw-r--r--include/configs/canyonlands.h1
-rw-r--r--include/configs/cardhu.h2
-rw-r--r--include/configs/coreboot.h3
-rw-r--r--include/configs/corenet_ds.h1
-rw-r--r--include/configs/csb272.h1
-rw-r--r--include/configs/csb472.h1
-rw-r--r--include/configs/dalmore.h2
-rw-r--r--include/configs/debris.h1
-rw-r--r--include/configs/devkit8000.h8
-rw-r--r--include/configs/eXalion.h1
-rw-r--r--include/configs/ebony.h1
-rw-r--r--include/configs/ep82xxm.h1
-rw-r--r--include/configs/exynos5250-dt.h6
-rw-r--r--include/configs/gdppc440etx.h1
-rw-r--r--include/configs/icon.h1
-rw-r--r--include/configs/igep0033.h5
-rw-r--r--include/configs/intip.h1
-rw-r--r--include/configs/katmai.h1
-rw-r--r--include/configs/kilauea.h1
-rw-r--r--include/configs/korat.h1
-rw-r--r--include/configs/kvme080.h1
-rw-r--r--include/configs/linkstation.h1
-rw-r--r--include/configs/luan.h1
-rw-r--r--include/configs/makalu.h1
-rw-r--r--include/configs/mpc5121ads.h1
-rw-r--r--include/configs/mpc8308_p1m.h1
-rw-r--r--include/configs/ocotea.h1
-rw-r--r--include/configs/p1_p2_rdb_pc.h1
-rw-r--r--include/configs/p3p440.h1
-rw-r--r--include/configs/paz00.h2
-rw-r--r--include/configs/pcm051.h6
-rw-r--r--include/configs/pcs440ep.h1
-rw-r--r--include/configs/pm9263.h2
-rw-r--r--include/configs/ppmc7xx.h3
-rw-r--r--include/configs/rpi_b.h2
-rw-r--r--include/configs/sbc405.h1
-rw-r--r--include/configs/sbc8349.h1
-rw-r--r--include/configs/sbc8548.h1
-rw-r--r--include/configs/sbc8641d.h1
-rw-r--r--include/configs/sc3.h1
-rw-r--r--include/configs/seaboard.h2
-rw-r--r--include/configs/sequoia.h1
-rw-r--r--include/configs/socrates.h1
-rw-r--r--include/configs/stxssa.h1
-rw-r--r--include/configs/t3corp.h1
-rw-r--r--include/configs/t4qds.h36
-rw-r--r--include/configs/taihu.h1
-rw-r--r--include/configs/taishan.h1
-rw-r--r--include/configs/utx8245.h1
-rw-r--r--include/configs/ve8313.h1
-rw-r--r--include/configs/ventana.h2
-rw-r--r--include/configs/vme8349.h1
-rw-r--r--include/configs/walnut.h1
-rw-r--r--include/configs/whistler.h4
-rw-r--r--include/configs/xpedite1000.h1
-rw-r--r--include/configs/xpedite517x.h1
-rw-r--r--include/configs/xpedite520x.h1
-rw-r--r--include/configs/xpedite537x.h1
-rw-r--r--include/configs/xpedite550x.h1
-rw-r--r--include/configs/yosemite.h1
-rw-r--r--include/configs/yucca.h1
159 files changed, 812 insertions, 95 deletions
diff --git a/include/configs/A3000.h b/include/configs/A3000.h
index b85244a..d506a55 100644
--- a/include/configs/A3000.h
+++ b/include/configs/A3000.h
@@ -96,6 +96,7 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#undef CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
diff --git a/include/configs/APC405.h b/include/configs/APC405.h
index 9a65cbc..1e39229 100644
--- a/include/configs/APC405.h
+++ b/include/configs/APC405.h
@@ -218,6 +218,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
index 9994476..7337f53 100644
--- a/include/configs/AR405.h
+++ b/include/configs/AR405.h
@@ -157,6 +157,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 09aa763..35c3773 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -172,6 +172,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
#undef CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 1c9d08e..a823f9f 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -34,6 +34,15 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_E500 /* BOOKE e500 family */
@@ -63,6 +72,7 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
#endif
#define CONFIG_FSL_LAW /* Use common FSL init code */
@@ -84,14 +94,15 @@
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_ENV_IS_NOWHERE
+#endif
#else
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#endif
-#ifndef CONFIG_SYS_NO_FLASH
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -113,16 +124,18 @@
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR 0xffe20000
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
-#else /* CONFIG_SYS_NO_FLASH */
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
-#endif
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
@@ -223,7 +236,7 @@ unsigned long get_board_ddr_clk(void);
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
- FTIM0_NOR_TEADC(0x01) | \
+ FTIM0_NOR_TEADC(0x04) | \
FTIM0_NOR_TEAHC(0x20))
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
FTIM1_NOR_TRAD_NOR(0x1A) |\
@@ -600,6 +613,16 @@ unsigned long get_board_ddr_clk(void);
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
@@ -620,6 +643,7 @@ unsigned long get_board_ddr_clk(void);
#endif
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_E1000
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index fd076e0..b5911c6 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -40,10 +40,34 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
+#define CONFIG_SPL_RELOC_STACK 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
@@ -55,7 +79,11 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
+#if defined(CONFIG_SYS_CLK_100)
+#define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
+#else
#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
+#endif
#define CONFIG_HWCONFIG
/*
@@ -125,16 +153,21 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
/* CONFIG_SYS_IMMR */
+/* DSP CCSRBAR */
+#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
/*
* Memory map
*
* 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
* 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
+ * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
* 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
* 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
* 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
* 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
+ * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
* 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
* 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
*
@@ -214,6 +247,9 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
@@ -295,7 +331,6 @@ extern unsigned long get_sdram_size(void);
/*
* Environment
*/
-#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
@@ -305,15 +340,16 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
-#else
-#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE 0x2000
-#endif
-#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE 0x400
+#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO /* echo on for serial download */
@@ -406,7 +442,9 @@ extern unsigned long get_sdram_size(void);
"fdtfile=bsc9131rdb.dtb\0" \
"bdev=sda1\0" \
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
- "othbootargs=ramdisk_size=600000 \0" \
+ "bootm_size=0x37000000\0" \
+ "othbootargs=ramdisk_size=600000 " \
+ "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
"usbext2boot=setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs; " \
"usb start;" \
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 431c686..3aa4443 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -49,6 +49,27 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
+#define CONFIG_SPL_RELOC_STACK 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x8ff80000
#endif
@@ -57,11 +78,12 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
@@ -73,6 +95,7 @@
#if defined(CONFIG_PCI)
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
@@ -221,6 +244,10 @@ combinations. this should be removed later
* IFC Definitions
*/
/* NOR Flash on IFC */
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
#define CONFIG_SYS_FLASH_BASE 0x88000000
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
@@ -301,7 +328,9 @@ combinations. this should be removed later
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_FSL_QIXIS
+#endif
#ifdef CONFIG_FSL_QIXIS
#define CONFIG_SYS_FPGA_BASE 0xffb00000
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
@@ -337,6 +366,22 @@ combinations. this should be removed later
#endif
/* Set up IFC registers for boot location NOR/NAND */
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
@@ -351,6 +396,7 @@ combinations. this should be removed later
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R
@@ -373,6 +419,9 @@ combinations. this should be removed later
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
@@ -502,7 +551,6 @@ combinations. this should be removed later
/*
* Environment
*/
-#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
@@ -516,11 +564,15 @@ combinations. this should be removed later
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
-#else
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
-#endif
#else
#define CONFIG_ENV_IS_IN_FLASH
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index 1e3a564..7017f8c 100644
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -327,6 +327,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#undef CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
index e102c36..c7904a1 100644
--- a/include/configs/CPC45.h
+++ b/include/configs/CPC45.h
@@ -450,6 +450,7 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_SYS_EARLY_PCI_INIT
#undef CONFIG_PCI_PNP
#undef CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index 11cf58b..bbd93ac 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -146,6 +146,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index e3e5ebc..36476e0 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -155,6 +155,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index c4fff48..4c12c85 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -176,6 +176,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 9122cbd..96b6c0a 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -173,6 +173,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index f778af7..c4cc5fd 100644
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -177,6 +177,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h
index 35daed0..78c66c7 100644
--- a/include/configs/CPCIISER4.h
+++ b/include/configs/CPCIISER4.h
@@ -140,6 +140,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index aa5ce29..3e9c21c 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -192,6 +192,7 @@
#define CONFIG_CMD_I2C
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_CMD_PCI
#endif
diff --git a/include/configs/CU824.h b/include/configs/CU824.h
index a3ceed1..6632196 100644
--- a/include/configs/CU824.h
+++ b/include/configs/CU824.h
@@ -288,6 +288,7 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#undef CONFIG_PCI_PNP
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
index bbe2713..4970ea6 100644
--- a/include/configs/DU440.h
+++ b/include/configs/DU440.h
@@ -357,6 +357,7 @@ int du440_phy_addr(int devnum);
* PCI stuff
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h
index 220372c..d10f4c1 100644
--- a/include/configs/ELPPC.h
+++ b/include/configs/ELPPC.h
@@ -242,6 +242,7 @@
* PCI stuff
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* pci plug-and-play */
#define CONFIG_PCI_HOST PCI_HOST_AUTO
#undef CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/G2000.h b/include/configs/G2000.h
index 08ba840..b6769ae 100644
--- a/include/configs/G2000.h
+++ b/include/configs/G2000.h
@@ -216,6 +216,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 444413d..d65377f 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -231,6 +231,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h
index a62ef63..dbad1fd 100644
--- a/include/configs/HIDDEN_DRAGON.h
+++ b/include/configs/HIDDEN_DRAGON.h
@@ -93,6 +93,7 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#undef CONFIG_PCI_PNP
diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h
index 791763a..2b72a33 100644
--- a/include/configs/HWW1U1A.h
+++ b/include/configs/HWW1U1A.h
@@ -188,6 +188,7 @@
#define CONFIG_PCI_PNP /* Scan PCI busses */
#define CONFIG_CMD_PCI /* Enable the "pci" command */
#define CONFIG_FSL_PCI_INIT /* Common FreeScale PCI initialization */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* We have PCI-E reset errata */
#define CONFIG_SYS_PCI_64BIT /* PCI resources are 64-bit */
#define CONFIG_PCI_SCAN_SHOW /* Display PCI scan during boot */
diff --git a/include/configs/JSE.h b/include/configs/JSE.h
index e0a0d8e..6ce789d 100644
--- a/include/configs/JSE.h
+++ b/include/configs/JSE.h
@@ -226,6 +226,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#undef CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h
index 546e28b..8d5e8ff 100644
--- a/include/configs/KAREF.h
+++ b/include/configs/KAREF.h
@@ -268,6 +268,7 @@
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE)
diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h
index 30fb6c2..2496639 100644
--- a/include/configs/MERGERBOX.h
+++ b/include/configs/MERGERBOX.h
@@ -36,6 +36,7 @@
#define CONFIG_SYS_TEXT_BASE 0xFC000000
#define CONFIG_PCI 1
+#define CONFIG_PCI_INDIRECT_BRIDGE 1
#define CONFIG_MASK_AER_AO
#define CONFIG_DISPLAY_AER_FULL
diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h
index 286f869..d1ef559 100644
--- a/include/configs/METROBOX.h
+++ b/include/configs/METROBOX.h
@@ -333,6 +333,7 @@
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE)
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 979495a..0d023ab 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -206,6 +206,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
#define CONFIG_PCI_PNP /* pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h
index 1391ce5..b3dbd6f 100644
--- a/include/configs/MOUSSE.h
+++ b/include/configs/MOUSSE.h
@@ -330,6 +330,7 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#undef CONFIG_PCI_PNP
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index c4c41c7..c312b77 100644
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -195,6 +195,7 @@
/*PCI*/
#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP
#define CONFIG_PCI_BOOTDELAY 0
#define CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index 0474140..c5aa586 100644
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -137,6 +137,7 @@
/* PCI */
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP
#define CONFIG_PCI_BOOTDELAY 0
#undef CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 95a1885..f10555c 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -402,6 +402,7 @@
#define CONFIG_SYS_SCCR_PCIEXP1CM 1
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE
#define CONFIG_PCI_PNP /* do pci plug-and-play */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index c28dfe0..1d753e7 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -76,6 +76,7 @@
#endif
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_ELBC 1
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 767b976..ee806c4 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -405,6 +405,7 @@
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE
#define CONFIG_PCI_PNP /* do pci plug-and-play */
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 8d5ed0f..ac4c253 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -264,6 +264,7 @@
#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SKIP_HOST_BRIDGE
#define CONFIG_PCI_PNP /* do pci plug-and-play */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index f592d3a..7c31f47 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -360,6 +360,7 @@
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_83XX_PCI_STREAMING
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index e5529c7..212089c 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -666,6 +666,7 @@
/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
| BATL_PP_RW \
| BATL_MEMCOHERENCE)
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 2c3f1f6..1130b59 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -393,6 +393,7 @@ boards, we say we have two, but don't display a message if we find only one. */
* PCI
*/
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_MPC83XX_PCI2
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index a1fbd5e..a71ac2b 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -458,6 +458,7 @@
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_83XX_PCI_STREAMING
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index fc00952..fcca542 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -314,6 +314,7 @@
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP /* do pci plug-and-play */
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 8243661..480468f 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -395,6 +395,7 @@
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#ifndef __ASSEMBLY__
extern int board_pci_host_broken(void);
#endif
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 9ad7e3a..d5c9d05 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -421,6 +421,7 @@
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index bcd77b6..cc2b7c3 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -84,6 +84,7 @@
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index a0fe15e..6cb00ee 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -52,6 +52,7 @@
#endif
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index a6bea15..d0e6ca6 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -40,6 +40,7 @@
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index d5f3c5f..09d0835 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -44,6 +44,7 @@
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 0e22cc7..d070f6a 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -52,6 +52,7 @@
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 266cb54..483556b 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -40,6 +40,7 @@
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 35d15f4..525e88f 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -49,6 +49,7 @@
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 5d69fb6..f1bfdcb 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -42,6 +42,7 @@
#define CONFIG_PCI1 1 /* PCI controller */
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index acd3276..c54755f 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -41,6 +41,7 @@
#define CONFIG_PCI 1 /* Disable PCI/PCIE */
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_QE /* Enable QE */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index d233365..25303c4 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -71,6 +71,7 @@
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index c619827..f791e76 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -51,6 +51,7 @@
#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 2643097..4a3ca01 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -510,6 +510,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* BAT2 Rapidio Memory
*/
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
| BATL_PP_RW | BATL_CACHEINHIBIT \
diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h
index 84a167d..8b04151 100644
--- a/include/configs/MUSENKI.h
+++ b/include/configs/MUSENKI.h
@@ -87,6 +87,7 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#undef CONFIG_PCI_PNP
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index a9c00ac..afd4c03 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -42,6 +42,7 @@
#define CONFIG_SYS_IMMR 0xE0000000
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SKIP_HOST_BRIDGE
#define CONFIG_HARD_I2C
#define CONFIG_TSEC_ENET
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
index 52d1729..21f286e 100644
--- a/include/configs/MVBLUE.h
+++ b/include/configs/MVBLUE.h
@@ -154,6 +154,7 @@
*/
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
index 47110af..4a93417 100644
--- a/include/configs/OCRTC.h
+++ b/include/configs/OCRTC.h
@@ -136,6 +136,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h
index 9f754c2..cd1f425 100644
--- a/include/configs/ORSG.h
+++ b/include/configs/ORSG.h
@@ -134,6 +134,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter */
#undef CONFIG_PCI_PNP /* no pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 437ee6e..7b28a27 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -31,10 +31,10 @@
#define CONFIG_PHYS_64BIT
#endif
-#ifdef CONFIG_P1010RDB
#define CONFIG_P1010
+#define CONFIG_E500 /* BOOKE e500 family */
+#include <asm/config_mpc85xx.h>
#define CONFIG_NAND_FSL_IFC
-#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD
@@ -48,15 +48,25 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
-#ifdef CONFIG_NAND /* NAND Boot */
-#define CONFIG_RAMBOOT_NAND
-#define CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
-#else
-#define CONFIG_SYS_TEXT_BASE 0x11001000
-#endif /* CONFIG_NAND_SPL */
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
+#define CONFIG_SPL_RELOC_STACK 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
@@ -74,8 +84,10 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
/* High Level Configuration Options */
@@ -90,6 +102,7 @@
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
@@ -241,7 +254,7 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* Don't relocate CCSRBAR while in NAND_SPL */
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
@@ -267,6 +280,10 @@ extern unsigned long get_sdram_size(void);
* IFC Definitions
*/
/* NOR Flash on IFC */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
#define CONFIG_SYS_FLASH_BASE 0xee000000
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
@@ -352,7 +369,7 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_NAND_DDR_LAW 11
/* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SECBOOT)
+#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
@@ -384,15 +401,6 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#endif
-/* NAND boot: 8K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE 0x2000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x10000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffb00000
@@ -420,14 +428,20 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_CS3_FTIM3 0x0
#endif /* CONFIG_SDCARD */
-#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
- defined(CONFIG_RAMBOOT_NAND)
+#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
#undef CONFIG_SYS_RAMBOOT
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\
+ && !defined(CONFIG_SECURE_BOOT)
+#define CONFIG_A003399_NOR_WORKAROUND
+#endif
+#endif
+
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R
@@ -449,7 +463,7 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
@@ -504,7 +518,7 @@ extern unsigned long get_sdram_size(void);
* SPI interface will not be available in case of NAND boot SPI CS0 will be
* used for SLIC
*/
-#if !defined(CONFIG_NAND_U_BOOT) || !defined(CONFIG_NAND_SECBOOT)
+#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
/* eSPI - Enhanced SPI */
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH
@@ -599,7 +613,6 @@ extern unsigned long get_sdram_size(void);
/*
* Environment
*/
-#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
@@ -614,16 +627,15 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
-#elif defined(CONFIG_NAND_U_BOOT)
+#elif defined(CONFIG_NAND)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_U_BOOT_SIZE
+#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
-#else
+#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
-#endif
#else
#define CONFIG_ENV_IS_IN_FLASH
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 8b13b10..9c27182 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -316,7 +316,6 @@
#define CONFIG_SYS_HUSH_PARSER
/* Video */
-#define CONFIG_FSL_DIU_FB
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
@@ -336,7 +335,6 @@
#endif
#ifndef CONFIG_FSL_DIU_FB
-#define CONFIG_ATI
#endif
#ifdef CONFIG_ATI
@@ -458,6 +456,7 @@
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
new file mode 100644
index 0000000..fee8040
--- /dev/null
+++ b/include/configs/P1023RDB.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Authors: Roy Zang <tie-fei.zang@freescale.com>
+ * Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE /* BOOKE */
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_MPC85xx
+#define CONFIG_P1023
+#define CONFIG_MP /* support multiple processors */
+
+#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
+#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 66666666
+#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_HWCONFIG
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x02000000
+
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/* Implement conversion of addresses in the LBC */
+#define CONFIG_SYS_LBC_LBCR 0x00000000
+#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
+
+/* DDR Setup */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+
+#define CONFIG_DDR_SPD
+#define CONFIG_FSL_DDR3
+#define CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x50
+#define CONFIG_SYS_DDR_RAW_TIMING
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x1fff_ffff DDR 512M cacheable
+ * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
+ * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
+ * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
+ * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable
+ * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
+ * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0
+ *
+ * Localbus non-cacheable
+ *
+ * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable
+ * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+ | BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
+
+#define CONFIG_SYS_NAND_BASE 0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
+ | OR_FCM_PGS \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+
+#define CONFIG_CMD_I2C
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 3, Slot 1, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_NAME "Slot 3"
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME "Slot 2"
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME "Slot 1"
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_E1000 /* Defind e1000 pci Ethernet card */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#endif /* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR 0xfff80000
+#else
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE 115200
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */
+#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
+#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
+#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
+#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
+
+/* For FM */
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHY_ATHEROS
+#endif
+
+/* Default address of microcode for the Linux Fman driver */
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xeff40000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1
+#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
+
+#define CONFIG_SYS_TBIPA_VALUE 8
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h
index 878bd5f..4943d7c 100644
--- a/include/configs/P1023RDS.h
+++ b/include/configs/P1023RDS.h
@@ -73,6 +73,7 @@
#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW /* Use common FSL init code */
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index a57d9dd..6ce4cbe 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -94,6 +94,7 @@
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#endif /* #if defined(CONFIG_PCI) */
diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h
index c75f86c..05a75d8 100644
--- a/include/configs/P2020COME.h
+++ b/include/configs/P2020COME.h
@@ -58,6 +58,7 @@
#define CONFIG_PCIE3 1 /* PCIE controller 3 (slot 3) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#endif /* #if defined(CONFIG_PCI) */
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index a975ee1..229117c 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -73,6 +73,7 @@
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index bbc53ce..4ea8717 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -77,6 +77,7 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CONFIG_FSL_LAW /* Use common FSL init code */
@@ -560,6 +561,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_E1000
diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
index ce8f9b0..dd2b9c3 100644
--- a/include/configs/P3041DS.h
+++ b/include/configs/P3041DS.h
@@ -40,7 +40,7 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
-
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#include "corenet_ds.h"
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 53979dd..48acee4 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -36,7 +36,7 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
-
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */
#include "corenet_ds.h"
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
index 778230d..d1e27c4 100644
--- a/include/configs/P5020DS.h
+++ b/include/configs/P5020DS.h
@@ -41,7 +41,7 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
-
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#include "corenet_ds.h"
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index 119819e..c3cacef 100644
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -141,6 +141,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */
#undef CONFIG_PCI_PNP /* no pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 713ea12..3757af0 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -199,6 +199,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
#define CONFIG_PCI_PNP /* pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 1ee0c48..1745eb3 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -192,6 +192,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index fbcf8e5..faadfe4 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -176,6 +176,7 @@
#define CONFIG_CMD_SNTP
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_CMD_PCI
#endif
diff --git a/include/configs/PM828.h b/include/configs/PM828.h
index c37aafd..f563fbe 100644
--- a/include/configs/PM828.h
+++ b/include/configs/PM828.h
@@ -176,6 +176,7 @@
#define CONFIG_CMD_SNTP
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_CMD_PCI
#endif
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index 8235b85..d97acec 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -163,6 +163,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h
index 992443a..a427551 100644
--- a/include/configs/PMC405DE.h
+++ b/include/configs/PMC405DE.h
@@ -142,6 +142,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 3837b8f..40c1827 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -419,6 +419,7 @@
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
diff --git a/include/configs/PN62.h b/include/configs/PN62.h
index 93876b1..e2f96aa 100644
--- a/include/configs/PN62.h
+++ b/include/configs/PN62.h
@@ -122,6 +122,7 @@
* PCI stuff
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* we need Plug 'n Play */
#if 0
#define CONFIG_PCI_SCAN_SHOW /* show PCI auto-scan at boot */
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 27a12b3..210bc30 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -324,6 +324,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#undef CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index c0ffb33..318c4c5 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -52,6 +52,7 @@
#endif
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_ELBC 1
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h
index f54fcb3..fa456ed 100644
--- a/include/configs/Sandpoint8240.h
+++ b/include/configs/Sandpoint8240.h
@@ -127,6 +127,7 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#undef CONFIG_PCI_PNP
diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h
index 84e4891..cdc51a5 100644
--- a/include/configs/Sandpoint8245.h
+++ b/include/configs/Sandpoint8245.h
@@ -95,6 +95,7 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#undef CONFIG_PCI_PNP
diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
index be977f1..3b3f9e6 100644
--- a/include/configs/TQM8272.h
+++ b/include/configs/TQM8272.h
@@ -443,6 +443,7 @@
#define CONFIG_PCI
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_PCI_PNP
#define CONFIG_EEPRO100
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 0738423..966a6e3 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -442,6 +442,7 @@
/* PCI */
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
| BATL_PP_RW \
| BATL_MEMCOHERENCE)
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index f1032f0..8f0c4b6 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -181,6 +181,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
index 462b155..710812f 100644
--- a/include/configs/W7OLMC.h
+++ b/include/configs/W7OLMC.h
@@ -154,6 +154,7 @@
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
#define CONFIG_PCI_PNP /* pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
index f28f3e4..f88dfe4 100644
--- a/include/configs/W7OLMG.h
+++ b/include/configs/W7OLMG.h
@@ -161,6 +161,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
#define CONFIG_PCI_PNP /* pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index 5def36a..0c78aca 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -169,6 +169,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
#undef CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index e9af825..8f29229 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -426,6 +426,7 @@
#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
#define CONFIG_SPL_OS_BOOT
+#define CONFIG_SPL_ENV_SUPPORT
/* Place patched DT blob (fdt) at this address */
#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
diff --git a/include/configs/adp-ag102.h b/include/configs/adp-ag102.h
index eea44db..a6e1849 100644
--- a/include/configs/adp-ag102.h
+++ b/include/configs/adp-ag102.h
@@ -143,6 +143,7 @@
*/
#define CONFIG_PCI
#define CONFIG_FTPCI100
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FTPCI100_MEM_BASE 0xa0000000
#define CONFIG_FTPCI100_IO_SIZE FTPCI100_BASE_IO_SIZE(256) /* 256M */
#define CONFIG_FTPCI100_MEM_SIZE FTPCI100_MEM_SIZE(128) /* 128M */
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index 0d53e51..d93d5e2 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -287,6 +287,7 @@
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 7cc3ef2..9c3c2cd 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -307,22 +307,44 @@
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
/*
- * Place the image at the start of the ROM defined image space and leave
- * space for SRAM scratch entries (see arch/arm/include/omap_common.h).
+ * Place the image at the start of the ROM defined image space.
* We limit our size to the ROM-defined downloaded image area, and use the
* rest of the space for stack.
*/
-#define CONFIG_SPL_TEXT_BASE 0x402F0500
+#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SPL_BSS_START_ADDR 0x80000000
+#define CONFIG_SPL_OS_BOOT
+
+#define CONFIG_SPL_BSS_START_ADDR 0x80a00000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+
+#ifdef CONFIG_SPL_OS_BOOT
+/* fat */
+#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args"
+#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_DRAM_1 + 0x100)
+
+/* raw mmc */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
+
+/* nand */
+#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* end of u-boot */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x1000
+
+/* spl export command */
+#define CONFIG_CMD_SPL
+#endif
+
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
@@ -334,6 +356,7 @@
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
#define CONFIG_SPL_ETH_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
@@ -380,7 +403,7 @@
* other needs.
*/
#define CONFIG_SYS_TEXT_BASE 0x80800000
-#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80a08000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
/* Since SPL did pll and ddr initialization for us,
@@ -476,7 +499,8 @@
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
"128k(SPL.backup1)," \
"128k(SPL.backup2)," \
- "128k(SPL.backup3),1920k(u-boot)," \
+ "128k(SPL.backup3),1792k(u-boot)," \
+ "128k(u-boot-spl-os)," \
"128k(u-boot-env),5m(kernel),-(rootfs)"
#define CONFIG_NAND_OMAP_GPMC
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
diff --git a/include/configs/aria.h b/include/configs/aria.h
index 5318aaf..bd81053 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -350,6 +350,7 @@
* PCI
*/
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
diff --git a/include/configs/atc.h b/include/configs/atc.h
index 538a167..57c4b33 100644
--- a/include/configs/atc.h
+++ b/include/configs/atc.h
@@ -263,6 +263,7 @@
#endif
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP
#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 506a558..d36984d 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -293,6 +293,7 @@
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
diff --git a/include/configs/beaver.h b/include/configs/beaver.h
index 058da4f..d51f5f8 100644
--- a/include/configs/beaver.h
+++ b/include/configs/beaver.h
@@ -56,7 +56,7 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index da67ae3..35a473a 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -153,6 +153,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index acb127c..92106d7 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -496,6 +496,7 @@
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index 6a99175..f3916de 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -55,7 +55,7 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index be04a75..2fefdc8 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -90,7 +90,8 @@
#endif
/* Generic TPM interfaced through LPC bus */
-#define CONFIG_GENERIC_LPC_TPM
+#define CONFIG_TPM
+#define CONFIG_TPM_TIS_LPC
#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000
/*-----------------------------------------------------------------------
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 2e2d439..66c7b4f 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -564,6 +564,7 @@
#endif
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_E1000
diff --git a/include/configs/csb272.h b/include/configs/csb272.h
index f21fa64..eec087c 100644
--- a/include/configs/csb272.h
+++ b/include/configs/csb272.h
@@ -204,6 +204,7 @@
*
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
diff --git a/include/configs/csb472.h b/include/configs/csb472.h
index aed5fa6..f6a456c 100644
--- a/include/configs/csb472.h
+++ b/include/configs/csb472.h
@@ -203,6 +203,7 @@
*
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
index 7b68f7c..6d7a187 100644
--- a/include/configs/dalmore.h
+++ b/include/configs/dalmore.h
@@ -60,7 +60,7 @@
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
-#define CONFIG_ENV_OFFSET ((4096 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */
diff --git a/include/configs/debris.h b/include/configs/debris.h
index 32aa4e5..c40fbd9 100644
--- a/include/configs/debris.h
+++ b/include/configs/debris.h
@@ -172,6 +172,7 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP
#define CONFIG_EEPRO100
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 788227d..3b74d7c 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -360,6 +360,14 @@
#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
0x400000)
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+
+#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args"
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
+
#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
#endif /* __CONFIG_H */
diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h
index 3238ac7..a6a0f8b 100644
--- a/include/configs/eXalion.h
+++ b/include/configs/eXalion.h
@@ -180,6 +180,7 @@
* PCI stuff
*/
#define CONFIG_PCI 1 /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#undef CONFIG_PCI_PNP
diff --git a/include/configs/ebony.h b/include/configs/ebony.h
index d6b6551..b05ba08 100644
--- a/include/configs/ebony.h
+++ b/include/configs/ebony.h
@@ -177,6 +177,7 @@
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
index 8d78921..7393f28 100644
--- a/include/configs/ep82xxm.h
+++ b/include/configs/ep82xxm.h
@@ -254,6 +254,7 @@
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_PCI_BOOTDELAY 0
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 9b97d4f..1632435 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -144,9 +144,9 @@
/* TPM */
#define CONFIG_TPM
#define CONFIG_CMD_TPM
-#define CONFIG_INFINEON_TPM_I2C
-#define CONFIG_INFINEON_TPM_I2C_BUS 3
-#define CONFIG_INFINEON_TPM_I2C_ADDR 0x20
+#define CONFIG_TPM_TIS_I2C
+#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
+#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
/* MMC SPL */
#define CONFIG_SPL
diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h
index 9efbb8e..7b8bac4 100644
--- a/include/configs/gdppc440etx.h
+++ b/include/configs/gdppc440etx.h
@@ -178,6 +178,7 @@
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \
diff --git a/include/configs/icon.h b/include/configs/icon.h
index 2fac0ef..c2da4ce 100644
--- a/include/configs/icon.h
+++ b/include/configs/icon.h
@@ -234,6 +234,7 @@
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h
index afbd549..12f28f8 100644
--- a/include/configs/igep0033.h
+++ b/include/configs/igep0033.h
@@ -215,12 +215,11 @@
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
/*
- * Place the image at the start of the ROM defined image space and leave
- * space for SRAM scratch entries (see arch/arm/include/omap_common.h).
+ * Place the image at the start of the ROM defined image space.
* We limit our size to the ROM-defined downloaded image area, and use the
* rest of the space for stack.
*/
-#define CONFIG_SPL_TEXT_BASE 0x402F0500
+#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
diff --git a/include/configs/intip.h b/include/configs/intip.h
index 33364a8..ed96b1b 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -316,6 +316,7 @@
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index 3ed8dc7..c6f712c 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -238,6 +238,7 @@
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index d505a41..aec4a58 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -483,6 +483,7 @@
* PCI stuff
*----------------------------------------------------------------------*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
diff --git a/include/configs/korat.h b/include/configs/korat.h
index b919aec..d7c1f85 100644
--- a/include/configs/korat.h
+++ b/include/configs/korat.h
@@ -355,6 +355,7 @@
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h
index e49dc28..87a5056 100644
--- a/include/configs/kvme080.h
+++ b/include/configs/kvme080.h
@@ -169,6 +169,7 @@
#define CONFIG_SYS_NS16550_CLK 14745600
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP
#define CONFIG_EEPRO100
diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h
index eec7961..20f0a18 100644
--- a/include/configs/linkstation.h
+++ b/include/configs/linkstation.h
@@ -185,6 +185,7 @@
* PCI stuff
*/
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
/* Verified: CONFIG_PCI_PNP doesn't work */
#undef CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/luan.h b/include/configs/luan.h
index 3b4761b..f0e568a 100644
--- a/include/configs/luan.h
+++ b/include/configs/luan.h
@@ -178,6 +178,7 @@
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index 6c1b136..f71f28b 100644
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -276,6 +276,7 @@
* PCI stuff
*----------------------------------------------------------------------*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index 64ce52d..6f003aa 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -336,6 +336,7 @@
* PCI
*/
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
/*
* General PCI
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index aa681f0..3c7a85e 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -353,6 +353,7 @@
#define CONFIG_SYS_SCCR_PCIEXP1CM 1
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE
#define CONFIG_PCI_PNP /* do pci plug-and-play */
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
index d0fe9da..3e64c74 100644
--- a/include/configs/ocotea.h
+++ b/include/configs/ocotea.h
@@ -197,6 +197,7 @@
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 7ed634b..2fa5372 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -217,6 +217,7 @@
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
index d7b1ca2..a19de07 100644
--- a/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@ -241,6 +241,7 @@
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index eac1ef9..9e2686a 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -46,7 +46,7 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 3480302..9b16c47 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -205,12 +205,11 @@
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
/*
- * Place the image at the start of the ROM defined image space and leave
- * space for SRAM scratch entries (see arch/arm/include/omap_common.h).
+ * Place the image at the start of the ROM defined image space.
* We limit our size to the ROM-defined downloaded image area, and use the
* rest of the space for stack.
*/
-#define CONFIG_SPL_TEXT_BASE 0x402F0500
+#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
@@ -232,6 +231,7 @@
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "pcm051 U-Boot SPL"
#define CONFIG_SPL_ETH_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index 351ff5a..1897619 100644
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -317,6 +317,7 @@
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index b60a9ad..6f6ddfa 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -355,7 +355,7 @@
#define CONFIG_BOOTCOMMAND "run flashboot"
#define CONFIG_ROOTPATH "/ronetix/rootfs"
-#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
#define CONFIG_CON_ROT "fbcon=rotate:3 "
#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\
diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h
index 5cd6609..3f9fdd4 100644
--- a/include/configs/ppmc7xx.h
+++ b/include/configs/ppmc7xx.h
@@ -118,6 +118,7 @@
*/
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP
#undef CONFIG_PCI_SCAN_SHOW
@@ -233,7 +234,7 @@
#define CONFIG_SYS_FLASH_ERASE_TOUT 250000
#define CONFIG_SYS_FLASH_WRITE_TOUT 5000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 19
+#define CONFIG_SYS_MAX_FLASH_SECT 128
/*
diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h
index c18b35b..216c6cb 100644
--- a/include/configs/rpi_b.h
+++ b/include/configs/rpi_b.h
@@ -61,6 +61,7 @@
#define CONFIG_BCM2835_GPIO
/* LCD */
#define CONFIG_LCD
+#define CONFIG_LCD_DT_SIMPLEFB
#define LCD_BPP LCD_COLOR16
/*
* Prevent allocation of RAM for FB; the real FB address is queried
@@ -175,6 +176,7 @@
/* Device tree support for bootm/bootz */
#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
/* ATAGs support for bootm/bootz */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h
index 5abcda3..6e53bc2 100644
--- a/include/configs/sbc405.h
+++ b/include/configs/sbc405.h
@@ -183,6 +183,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 478d0d8..fdc1b95 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -573,6 +573,7 @@
/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
| BATL_PP_RW \
| BATL_MEMCOHERENCE)
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 2209ddf..148ade3 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -33,6 +33,7 @@
* Top level Makefile configuration choices
*/
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI1
#endif
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 9040ec6..0e2d17d 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -64,6 +64,7 @@
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index fb74608..9dec21d 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -269,6 +269,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index f66173e..f0da1fc 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -72,7 +72,7 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index dd5d7cd..11fce53 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -363,6 +363,7 @@
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 25f15f2..7a0b481 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -48,6 +48,7 @@
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_TSEC_ENET /* tsec ethernet support */
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index c1a90a7..96d7128 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -46,6 +46,7 @@
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
#define CONFIG_PCI /* PCI ethernet support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_TSEC_ENET /* tsec ethernet support*/
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h
index 2a731a6..ff2189c 100644
--- a/include/configs/t3corp.h
+++ b/include/configs/t3corp.h
@@ -376,6 +376,7 @@
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index fa1dcc3..92b2179 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -33,6 +33,15 @@
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
#define CONFIG_CMD_REGINFO
/* High Level Configuration Options */
@@ -65,20 +74,22 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_ENV_IS_NOWHERE
+#endif
#else
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#endif
-#ifndef CONFIG_SYS_NO_FLASH
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -100,18 +111,18 @@
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR 0xffe20000
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
-#else /* CONFIG_SYS_NO_FLASH */
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
-#endif
-
-
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
@@ -633,6 +644,16 @@ unsigned long get_board_ddr_clk(void);
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
@@ -657,6 +678,7 @@ unsigned long get_board_ddr_clk(void);
#endif
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_E1000
diff --git a/include/configs/taihu.h b/include/configs/taihu.h
index a3738b7..a43c3da 100644
--- a/include/configs/taihu.h
+++ b/include/configs/taihu.h
@@ -171,6 +171,7 @@ unsigned char spi_read(void);
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/taishan.h b/include/configs/taishan.h
index 3046081..c9f1a9f 100644
--- a/include/configs/taishan.h
+++ b/include/configs/taishan.h
@@ -192,6 +192,7 @@
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_EEPRO100 1 /* include PCI EEPRO100 */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h
index 66568c8..60d1503 100644
--- a/include/configs/utx8245.h
+++ b/include/configs/utx8245.h
@@ -139,6 +139,7 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#undef CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_EEPRO100
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index d3b8379..7b1130a 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -43,6 +43,7 @@
#endif
#define CONFIG_PCI 1
+#define CONFIG_PCI_INDIRECT_BRIDGE 1
#define CONFIG_FSL_ELBC 1
#define CONFIG_BOARD_EARLY_INIT_F 1
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index 5755f11..41a7176 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -52,7 +52,7 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 61e02e6..f97de54 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -489,6 +489,7 @@
/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
diff --git a/include/configs/walnut.h b/include/configs/walnut.h
index d10f748..219f276 100644
--- a/include/configs/walnut.h
+++ b/include/configs/walnut.h
@@ -112,6 +112,7 @@
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index 9542c7e..994edec 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -61,12 +61,12 @@
/*
* Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes
- * the user plugged the standard 8MB MoviNAND card into J29/HSMMC/POP. If
+ * the user plugged the standard 8GB MoviNAND card into J29/HSMMC/POP. If
* they didn't, the boot sector layout may be different. However, use of that
* particular card is standard practice as far as I know.
*/
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h
index 506d646..1f48cc5 100644
--- a/include/configs/xpedite1000.h
+++ b/include/configs/xpedite1000.h
@@ -167,6 +167,7 @@ extern void out32(unsigned int, unsigned long);
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index 1851a00..f28f443 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -49,6 +49,7 @@
#define CONFIG_PCIE1 1 /* PCIE controler 1 */
#define CONFIG_PCIE2 1 /* PCIE controler 2 */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
index ff99481..3034a3c 100644
--- a/include/configs/xpedite520x.h
+++ b/include/configs/xpedite520x.h
@@ -48,6 +48,7 @@
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCI1 1 /* PCI controller 1 */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 46f1c90..43359a2 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -49,6 +49,7 @@
#define CONFIG_PCIE1 1 /* PCIE controler 1 */
#define CONFIG_PCIE2 1 /* PCIE controler 2 */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 2acf6c8..a171085 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -48,6 +48,7 @@
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (PEX8112 or XMC) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 0cbef6f..cde0df1 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -222,6 +222,7 @@
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index fb684b5..3282d37 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -199,6 +199,7 @@
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE