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-rw-r--r--include/configs/Adder.h6
-rw-r--r--include/configs/MPC8313ERDB.h88
-rw-r--r--include/configs/MPC8315ERDB.h2
-rw-r--r--include/configs/MPC8323ERDB.h64
-rw-r--r--include/configs/MPC832XEMDS.h2
-rw-r--r--include/configs/MPC8349ITX.h35
-rw-r--r--include/configs/MPC8360EMDS.h3
-rw-r--r--include/configs/MPC8360ERDK.h88
-rw-r--r--include/configs/MPC837XEMDS.h2
-rw-r--r--include/configs/MPC837XERDB.h113
-rw-r--r--include/configs/TQM5200.h21
-rw-r--r--include/configs/bf533-ezkit.h9
-rw-r--r--include/configs/bf533-stamp.h25
-rw-r--r--include/configs/bf537-stamp.h43
-rw-r--r--include/configs/bf561-ezkit.h6
-rw-r--r--include/configs/canyonlands.h567
-rw-r--r--include/configs/hcu4.h18
-rw-r--r--include/configs/hcu5.h14
-rw-r--r--include/configs/lwmon5.h96
-rw-r--r--include/configs/mcu25.h361
-rw-r--r--include/configs/mgcoge.h5
-rw-r--r--include/configs/stxxtc.h2
22 files changed, 1389 insertions, 181 deletions
diff --git a/include/configs/Adder.h b/include/configs/Adder.h
index 4304ecc..7919991 100644
--- a/include/configs/Adder.h
+++ b/include/configs/Adder.h
@@ -37,6 +37,8 @@
#define CONFIG_ETHER_ON_FEC1
#define CONFIG_ETHER_ON_FEC2
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
#define CFG_DISCOVER_PHY
@@ -212,4 +214,8 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index f12a3e6..9576fa5 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -38,6 +38,14 @@
#define CONFIG_PCI
#define CONFIG_83XX_GENERIC_PCI
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ */
+#define CONFIG_VSC7385_ENET
+
+
#ifdef CFG_66MHZ
#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
#elif defined(CFG_33MHZ)
@@ -65,6 +73,22 @@
#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
/*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE 0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE 8192
+
+#endif
+
+/*
* DDR Setup
*/
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
@@ -214,19 +238,24 @@
#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
#define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
+/* local bus read write buffer mapping */
+#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */
+#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */
+#define CFG_LBLAWBAR3_PRELIM 0xFA000000
+#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
+
+/* Vitesse 7385 */
+
#define CFG_VSC7385_BASE 0xF0000000
-#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
+#ifdef CONFIG_VSC7385_ENET
+
#define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
#define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */
#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */
-/* local bus read write buffer mapping */
-#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */
-#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */
-#define CFG_LBLAWBAR3_PRELIM 0xFA000000
-#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
+#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
@@ -263,13 +292,6 @@
#define CFG_I2C_OFFSET 0x3000
#define CFG_I2C2_OFFSET 0x3100
-/* TSEC */
-#define CFG_TSEC1_OFFSET 0x24000
-#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET 0x25000
-#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
-#define CONFIG_NET_MULTI
-
/*
* General PCI
* Addresses are mapped 1-1.
@@ -288,26 +310,31 @@
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
/*
- * TSEC configuration
+ * TSEC
*/
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
-#endif
-
-#define CONFIG_GMII 1 /* MII PHY management */
-#define CONFIG_TSEC1 1
+#define CONFIG_NET_MULTI
+#define CONFIG_GMII /* MII PHY management */
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
+#define CFG_TSEC1_OFFSET 0x24000
+#define TSEC1_PHY_ADDR 0x1c
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC1_PHYIDX 0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME "TSEC1"
-#define TSEC1_PHY_ADDR 0x1c
-#define TSEC2_PHY_ADDR 4
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
+#define CFG_TSEC2_OFFSET 0x25000
+#define TSEC2_PHY_ADDR 4
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC2_PHYIDX 0
+#endif
+
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC1"
@@ -496,10 +523,13 @@
*/
#define CONFIG_ENV_OVERWRITE
+#ifdef CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:95:01
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH0
+#endif
+
+#ifdef CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02
+#endif
#define CONFIG_IPADDR 10.0.0.2
#define CONFIG_SERVERIP 10.0.0.1
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index ff7101f..af78726 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -299,7 +299,7 @@
#define CFG_PCI_MMIO_BASE 0x90000000
#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE 0xE0300000
+#define CFG_PCI_IO_BASE 0x00000000
#define CFG_PCI_IO_PHYS 0xE0300000
#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index bf5ef4b..94c4c6b 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -66,6 +66,13 @@
#define CFG_IMMR 0xE0000000
/*
+ * System performance
+ */
+#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
+#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
+#define CFG_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
+
+/*
* DDR Setup
*/
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
@@ -82,17 +89,51 @@
/* Manually set up DDR parameters
*/
#define CFG_DDR_SIZE 64 /* MB */
-#define CFG_DDR_CS0_CONFIG 0x80840101
-#define CFG_DDR_TIMING_0 0x00220802
-#define CFG_DDR_TIMING_1 0x3935d322
-#define CFG_DDR_TIMING_2 0x0f9048ca
+#define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \
+ | CSCONFIG_ODT_WR_ACS \
+ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 )
+ /* 0x80010101 */
+#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+ | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
+ | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
+ | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
+ | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
+ | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
+ | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
+ | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+ /* 0x00220802 */
+#define CFG_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
+ | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+ | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
+ | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
+ | ( 3 << TIMING_CFG1_REFREC_SHIFT ) \
+ | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
+ | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
+ | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+ /* 0x26253222 */
+#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+ | (31 << TIMING_CFG2_CPO_SHIFT ) \
+ | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
+ | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
+ | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
+ | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
+ | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+ /* 0x1f9048c7 */
#define CFG_DDR_TIMING_3 0x00000000
-#define CFG_DDR_CLK_CNTL 0x02000000
-#define CFG_DDR_MODE 0x44400232
+#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+ /* 0x02000000 */
+#define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
+ | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
+ /* 0x44480232 */
#define CFG_DDR_MODE2 0x8000c000
-#define CFG_DDR_INTERVAL 0x03200064
+#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+ | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+ /* 0x03200064 */
#define CFG_DDR_CS0_BNDS 0x00000003
-#define CFG_DDR_SDRAM_CFG 0x43080000
+#define CFG_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_32_BE )
+ /* 0x43080000 */
#define CFG_DDR_SDRAM_CFG2 0x00401000
#endif
@@ -280,10 +321,10 @@
#define CFG_I2C_OFFSET 0x3000
/*
- * Config on-board RTC
+ * Config on-board EEPROM
*/
-#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
-#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 2
/*
* General PCI
@@ -376,6 +417,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ASKENV
#if defined(CONFIG_PCI)
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index f32c4f7..be2ab45 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -346,7 +346,7 @@
#define CFG_PCI_MMIO_BASE 0x90000000
#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE 0xE0300000
+#define CFG_PCI_IO_BASE 0x00000000
#define CFG_PCI_IO_PHYS 0xE0300000
#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 48c2736..6b8b74d 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -68,12 +68,16 @@
#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */
+#define CONFIG_MISC_INIT_F
+#define CONFIG_MISC_INIT_R
-/* On-board devices */
+/*
+ * On-board devices
+ */
#ifdef CONFIG_MPC8349ITX
#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */
-#define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */
+#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
#endif
#define CONFIG_PCI
@@ -88,9 +92,6 @@
/* I2C */
#ifdef CONFIG_HARD_I2C
-#define CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
-
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
@@ -155,7 +156,7 @@
#define CFG_MEMTEST_END 0x2000
#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#ifdef CONFIG_HARD_I2C
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
@@ -190,6 +191,18 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CFG_FLASH_SIZE 16 /* FLASH size in MB */
#define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE 0xFEFFE000
+#define CONFIG_VSC7385_IMAGE_SIZE 8192
+
+#endif
+
/*
* BRx, ORx, LBLAWBARx, and LBLAWARx
*/
@@ -205,10 +218,10 @@ boards, we say we have two, but don't display a message if we find only one. */
/* Vitesse 7385 */
-#ifdef CONFIG_VSC7385
-
#define CFG_VSC7385_BASE 0xF8000000
+#ifdef CONFIG_VSC7385_ENET
+
#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V)
#define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
@@ -384,7 +397,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME "TSEC1"
#define CFG_TSEC2_OFFSET 0x25000
-#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
+
#define TSEC2_PHY_ADDR 4
#define TSEC2_PHYIDX 0
#define TSEC2_FLAGS TSEC_GIGABIT
@@ -619,11 +632,11 @@ boards, we say we have two, but don't display a message if we find only one. */
*/
#define CONFIG_ENV_OVERWRITE
-#ifdef CONFIG_TSEC1
+#ifdef CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:8C:01
#endif
-#ifdef CONFIG_TSEC2
+#ifdef CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
#endif
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index c8dcbc6..46451c4 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -194,6 +194,7 @@
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
@@ -374,7 +375,7 @@
#define CFG_PCI_MMIO_BASE 0x90000000
#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE 0xE0300000
+#define CFG_PCI_IO_BASE 0x00000000
#define CFG_PCI_IO_PHYS 0xE0300000
#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 27b037a..a4f6af6 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -30,8 +30,8 @@
* System Clock Setup
*/
#ifdef CONFIG_CLKIN_33MHZ
-#define CONFIG_83XX_CLKIN 33000000
-#define CONFIG_SYS_CLK_FREQ 33000000
+#define CONFIG_83XX_CLKIN 33333333
+#define CONFIG_SYS_CLK_FREQ 33333333
#define PCI_33M 1
#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1
#else
@@ -89,8 +89,8 @@
#define CFG_83XX_DDR_USES_CS0
-#undef CONFIG_DDR_ECC /* support DDR ECC function */
-#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
+#define CONFIG_DDR_ECC /* support DDR ECC function */
+#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
/*
* DDRCDR - DDR Control Driver Register
@@ -104,20 +104,44 @@
*/
#define CONFIG_DDR_II
#define CFG_DDR_SIZE 256 /* MB */
-#define CFG_DDRCDR 0x80080001
#define CFG_DDR_CS0_BNDS 0x0000000f
#define CFG_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
- CSCONFIG_COL_BIT_10)
-#define CFG_DDR_TIMING_0 0x00330903
-#define CFG_DDR_TIMING_1 0x3835a322
-#define CFG_DDR_TIMING_2 0x00104909
-#define CFG_DDR_TIMING_3 0x00000000
-#define CFG_DDR_CLK_CNTL 0x02000000
+ CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
+#define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
+#define CFG_DDR_SDRAM_CFG2 0x00001000
+#define CFG_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CFG_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+ (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
#define CFG_DDR_MODE 0x47800432
#define CFG_DDR_MODE2 0x8000c000
-#define CFG_DDR_INTERVAL 0x045b0100
-#define CFG_DDR_SDRAM_CFG 0x03000000
-#define CFG_DDR_SDRAM_CFG2 0x00001000
+
+#define CFG_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+ (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+ (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+ (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+ (0 << TIMING_CFG0_WWT_SHIFT) | \
+ (0 << TIMING_CFG0_RRT_SHIFT) | \
+ (0 << TIMING_CFG0_WRT_SHIFT) | \
+ (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CFG_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_30) | \
+ ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
+ ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+ ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
+ (10 << TIMING_CFG1_REFREC_SHIFT) | \
+ ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+ ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+ ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CFG_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+ (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+ (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+ (0 << TIMING_CFG2_CPO_SHIFT))
+
+#define CFG_DDR_TIMING_3 0x00000000
/*
* Memory test
@@ -184,6 +208,11 @@
* NAND flash on the local bus
*/
#define CFG_NAND_BASE 0x60000000
+#define CONFIG_CMD_NAND 1
+#define CONFIG_NAND_FSL_UPM 1
+#define CFG_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
#define CFG_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */
@@ -230,6 +259,7 @@
/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
@@ -290,7 +320,7 @@
#define CFG_UEC1_TX_CLK QE_CLK9
#define CFG_UEC1_ETH_TYPE GIGA_ETH
#define CFG_UEC1_PHY_ADDR 2
-#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
#endif
#define CONFIG_UEC_ETH2 /* GETH2 */
@@ -301,7 +331,7 @@
#define CFG_UEC2_TX_CLK QE_CLK4
#define CFG_UEC2_ETH_TYPE GIGA_ETH
#define CFG_UEC2_PHY_ADDR 4
-#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
#endif
/*
@@ -340,6 +370,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -499,27 +530,44 @@
"consoledev=ttyS0\0"\
"loadaddr=a00000\0"\
"fdtaddr=900000\0"\
- "bootfile=uImage\0"\
"fdtfile=dtb\0"\
"fsfile=fs\0"\
"ubootfile=u-boot.bin\0"\
+ "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
"setbootargs=setenv bootargs console=$consoledev,$baudrate "\
"$mtdparts panic=1\0"\
"adddhcpargs=setenv bootargs $bootargs ip=on\0"\
"addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
"$gatewayip:$netmask:$hostname:$netdev:off "\
"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
+ "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
+ "rootfstype=jffs2 rw\0"\
"tftp_get_uboot=tftp 100000 $ubootfile\0"\
"tftp_get_kernel=tftp $loadaddr $bootfile\0"\
"tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
"tftp_get_fs=tftp c00000 $fsfile\0"\
+ "nand_erase_kernel=nand erase 0 400000\0"\
+ "nand_erase_dtb=nand erase 400000 20000\0"\
+ "nand_erase_fs=nand erase 420000 3be0000\0"\
+ "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\
+ "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\
+ "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\
+ "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
+ "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
"nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
"cp.b 100000 ff800000 $filesize\0"\
+ "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
+ "nand_write_kernel\0"\
+ "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
+ "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\
+ "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\
+ "nand_reflash_fs\0"\
"boot_m=bootm $loadaddr - $fdtaddr\0"\
- "dhcpboot=run setbootargs adddhcpargs tftp_get_kernel tftp_get_dtb "\
- "boot_m\0"\
+ "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
"nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
- "boot_m\0"\
+ "boot_m\0"\
+ "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
+ "boot_m\0"\
""
#define CONFIG_BOOTCOMMAND "run dhcpboot"
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 5586533..b307bf7 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -338,7 +338,7 @@
#define CFG_PCI_MMIO_BASE 0x90000000
#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE 0xE0300000
+#define CFG_PCI_IO_BASE 0x00000000
#define CFG_PCI_IO_PHYS 0xE0300000
#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 1964946..90812e9 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -32,6 +32,15 @@
#define CONFIG_PCI 1
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ */
+#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
+#define CONFIG_VSC7385_ENET
+
/*
* System Clock Setup
*/
@@ -118,6 +127,22 @@
#define CFG_IMMR 0xE0000000
/*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE 0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE 8192
+
+#endif
+
+/*
* DDR Setup
*/
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
@@ -251,15 +276,38 @@
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */
+#define CFG_BR1_PRELIM (CFG_NAND_BASE | \
+ (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \
+ BR_PS_8 | /* Port Size = 8 bit */ \
+ BR_MS_FCM | /* MSEL = FCM */ \
+ BR_V) /* valid */
+#define CFG_OR1_PRELIM (0xFFFF8000 | /* length 32K */ \
+ OR_FCM_CSCT | \
+ OR_FCM_CST | \
+ OR_FCM_CHT | \
+ OR_FCM_SCY_1 | \
+ OR_FCM_TRLX | \
+ OR_FCM_EHTR)
+#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
+#define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
+
+/* Vitesse 7385 */
+
#define CFG_VSC7385_BASE 0xF0000000
-/* VSC7385 Gigabit Switch support */
-#define CONFIG_VSC7385_ENET
+#ifdef CONFIG_VSC7385_ENET
+
#define CFG_BR2_PRELIM 0xf0000801 /* Base address */
#define CFG_OR2_PRELIM 0xfffe09ff /* 128K bytes*/
#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE /* Access Base */
#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */
+#endif
+
/*
* Serial Port
*/
@@ -276,6 +324,11 @@
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
+/* SERDES */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1 0xe3000
+#define CONFIG_FSL_SERDES2 0xe3100
+
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
@@ -285,6 +338,7 @@
/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
@@ -312,7 +366,7 @@
#define CFG_PCI_MMIO_BASE 0x90000000
#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE 0xE0300000
+#define CFG_PCI_IO_BASE 0x00000000
#define CFG_PCI_IO_PHYS 0xE0300000
#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
@@ -324,43 +378,43 @@
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif /* CONFIG_PCI */
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
-#endif
-
/*
* TSEC
*/
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
-#define CFG_TSEC1_OFFSET 0x24000
-#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET 0x25000
-#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
+#ifdef CONFIG_TSEC_ENET
-/*
- * TSEC ethernet configuration
- */
-#define CONFIG_GMII 1 /* MII PHY management */
-#define CONFIG_TSEC1 1
+#define CONFIG_NET_MULTI
+#define CONFIG_GMII /* MII PHY management */
+
+#define CONFIG_TSEC1
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "TSEC1"
+#define CFG_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 0x1c
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
+#endif
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define CFG_TSEC2_OFFSET 0x25000
+#define TSEC2_PHY_ADDR 0x1c
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHYIDX 0
+#endif
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
+#endif
+
/*
* Environment
*/
@@ -529,10 +583,15 @@
*/
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
-#define CONFIG_ETHADDR 00:04:9f:ef:04:01
-#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
-#define CONFIG_ETH1ADDR 00:04:9f:ef:04:02
+#ifdef CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR 00:04:9f:ef:04:01
+#endif
+
+#ifdef CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:04:9f:ef:04:02
+#endif
+
+#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_IPADDR 10.0.0.2
#define CONFIG_SERVERIP 10.0.0.1
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 9a0e9b8..b36c826 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -252,12 +252,22 @@
"setup=tftp 200000 cam5200/setup.img; autoscr 200000\0"
#endif
+#if defined(CONFIG_TQM5200_B)
+#define ENV_FLASH_LAYOUT \
+ "fdt_addr=FC100000\0" \
+ "kernel_addr=FC140000\0" \
+ "ramdisk_addr=FC600000\0"
+#else /* !CONFIG_TQM5200_B */
+#define ENV_FLASH_LAYOUT \
+ "fdt_addr=FC0A0000\0" \
+ "kernel_addr=FC0C0000\0" \
+ "ramdisk_addr=FC300000\0"
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"console=ttyPSC0\0" \
- "fdt_addr=FC0A0000\0" \
- "kernel_addr=FC0C0000\0" \
- "ramdisk_addr=FC300000\0" \
+ ENV_FLASH_LAYOUT \
"kernel_addr_r=400000\0" \
"fdt_addr_r=600000\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
@@ -400,8 +410,9 @@
# if defined(CONFIG_TQM5200_B)
# if defined(CFG_LOWBOOT)
# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:1m(firmware)," \
- "1536k(kernel)," \
- "3584k(small-fs)," \
+ "256k(dtb)," \
+ "2304k(kernel)," \
+ "2560k(small-fs)," \
"2m(initrd)," \
"8m(misc)," \
"16m(big-fs)"
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index 6cb6bc4..f2c8703 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -5,6 +5,8 @@
#ifndef __CONFIG_EZKIT533_H__
#define __CONFIG_EZKIT533_H__
+#include <asm/blackfin-config-pre.h>
+
#define CONFIG_BAUDRATE 57600
#define CONFIG_STAMP 1
@@ -41,10 +43,7 @@
#define CONFIG_PANIC_HANG 1
-#define ADSP_BF531 0x31
-#define ADSP_BF532 0x32
-#define ADSP_BF533 0x33
-#define BFIN_CPU ADSP_BF533
+#define CONFIG_BFIN_CPU bf533-0.3
/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
@@ -120,7 +119,7 @@
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"
-#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */
+#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index cce6ef7..76dd2fa 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -5,6 +5,8 @@
#ifndef __CONFIG_STAMP_H__
#define __CONFIG_STAMP_H__
+#include <asm/blackfin-config-pre.h>
+
#define CONFIG_STAMP 1
#define CONFIG_RTC_BFIN 1
#define CONFIG_BF533 1
@@ -21,10 +23,7 @@
#define CONFIG_PANIC_HANG 1
-#define ADSP_BF531 0x31
-#define ADSP_BF532 0x32
-#define ADSP_BF533 0x33
-#define BFIN_CPU ADSP_BF533
+#define CONFIG_BFIN_CPU bf533-0.3
/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
@@ -329,23 +328,7 @@
#define CONFIG_BAUDRATE 57600
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#if (BFIN_CPU == ADSP_BF531)
-#define CFG_PROMPT "serial_bf531> " /* Monitor Command Prompt */
-#elif (BFIN_CPU == ADSP_BF532)
-#define CFG_PROMPT "serial_bf532> " /* Monitor Command Prompt */
-#else
-#define CFG_PROMPT "serial_bf533> " /* Monitor Command Prompt */
-#endif
-#else
-#if (BFIN_CPU == ADSP_BF531)
-#define CFG_PROMPT "bf531> " /* Monitor Command Prompt */
-#elif (BFIN_CPU == ADSP_BF532)
-#define CFG_PROMPT "bf532> " /* Monitor Command Prompt */
-#else
-#define CFG_PROMPT "bf533> " /* Monitor Command Prompt */
-#endif
-#endif
+#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index b9a9e3c..0e189d4 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -5,6 +5,8 @@
#ifndef __CONFIG_BF537_H__
#define __CONFIG_BF537_H__
+#include <asm/blackfin-config-pre.h>
+
#define CFG_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_BAUDRATE 57600
@@ -31,10 +33,8 @@
#define CONFIG_PANIC_HANG 1
-#define ADSP_BF534 0x34
-#define ADSP_BF536 0x36
-#define ADSP_BF537 0x37
-#define BFIN_CPU ADSP_BF537
+#define CONFIG_BFIN_CPU bf537-0.2
+#define CONFIG_BFIN_MAC
/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
@@ -113,7 +113,7 @@
* Network Settings
*/
/* network support */
-#if (BFIN_CPU != ADSP_BF534)
+#ifdef CONFIG_BFIN_MAC
#define CONFIG_IPADDR 192.168.0.15
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_GATEWAYIP 192.168.0.1
@@ -186,7 +186,7 @@
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_DATE
-#if (BFIN_CPU == ADSP_BF534)
+#ifndef CONFIG_BFIN_MAC
#undef CONFIG_CMD_NET
#else
#define CONFIG_CMD_PING
@@ -219,7 +219,7 @@
#define CONFIG_LOADADDR 0x1000000
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
-#if (BFIN_CPU != ADSP_BF534)
+#ifdef CONFIG_BFIN_MAC
#define CONFIG_EXTRA_ENV_SETTINGS \
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
@@ -243,7 +243,7 @@
""
#endif
#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
-#if (BFIN_CPU != ADSP_BF534)
+#ifdef CONFIG_BFIN_MAC
#define CONFIG_EXTRA_ENV_SETTINGS \
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
@@ -267,23 +267,7 @@
#endif
#endif
-#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
-#if (BFIN_CPU == ADSP_BF534)
-#define CFG_PROMPT "serial_bf534> " /* Monitor Command Prompt */
-#elif (BFIN_CPU == ADSP_BF536)
-#define CFG_PROMPT "serial_bf536> " /* Monitor Command Prompt */
-#else
-#define CFG_PROMPT "serial_bf537> " /* Monitor Command Prompt */
-#endif
-#else
-#if (BFIN_CPU == ADSP_BF534)
-#define CFG_PROMPT "bf534> " /* Monitor Command Prompt */
-#elif (BFIN_CPU == ADSP_BF536)
-#define CFG_PROMPT "bf536> " /* Monitor Command Prompt */
-#else
-#define CFG_PROMPT "bf537> " /* Monitor Command Prompt */
-#endif
-#endif
+#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
@@ -302,6 +286,11 @@
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x20000000
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_FLASH_PROTECTION
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
@@ -311,10 +300,6 @@
#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_UART_BOOT)
/* for bf537-stamp, usrt boot mode still store env in flash */
#define CFG_ENV_IS_IN_FLASH 1
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 2966260..c29555a 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -5,6 +5,8 @@
#ifndef __CONFIG_EZKIT561_H__
#define __CONFIG_EZKIT561_H__
+#include <asm/blackfin-config-pre.h>
+
#define CONFIG_VDSP 1
#define CONFIG_BF561 1
@@ -18,6 +20,8 @@
#define CONFIG_PANIC_HANG 1
+#define CONFIG_BFIN_CPU bf561-0.3
+
/*
* Boot Mode Set
* Blackfin can support several boot modes
@@ -216,7 +220,7 @@
*/
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */
+#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
new file mode 100644
index 0000000..a4bcc65
--- /dev/null
+++ b/include/configs/canyonlands.h
@@ -0,0 +1,567 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * canyonlands.h - configuration for Canyonlands (460EX)
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_CANYONLANDS 1 /* Board is Canyonlands */
+#define CONFIG_440 1
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_460EX 1 /* Specific PPC460EX support */
+
+#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
+
+#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
+#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
+#define CFG_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
+
+#define CFG_PCIE0_CFGBASE 0xc0000000
+#define CFG_PCIE1_CFGBASE 0xc1000000
+#define CFG_PCIE0_XCFGBASE 0xc3000000
+#define CFG_PCIE1_XCFGBASE 0xc3001000
+
+#define CFG_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
+
+/* base address of inbound PCIe window */
+#define CFG_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
+
+/* EBC stuff */
+#define CFG_NAND_ADDR 0xE0000000
+#define CFG_BCSR_BASE 0xE1000000
+#define CFG_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
+#define CFG_FLASH_BASE 0xFC000000 /* later mapped to this addr */
+#define CFG_FLASH_BASE_PHYS_H 0x4
+#define CFG_FLASH_BASE_PHYS_L 0xCC000000
+#define CFG_FLASH_BASE_PHYS (((u64)CFG_FLASH_BASE_PHYS_H << 32) | \
+ (u64)CFG_FLASH_BASE_PHYS_L)
+#define CFG_FLASH_SIZE (64 << 20)
+
+#define CFG_OCM_BASE 0xE3000000 /* OCM: 16k */
+#define CFG_SRAM_BASE 0xE8000000 /* SRAM: 256k */
+#define CFG_LOCAL_CONF_REGS 0xEF000000
+
+#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */
+
+#define CFG_AHB_BASE 0xE2000000 /* internal AHB peripherals */
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc()*/
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in OCM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH).
+ */
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
+#else
+#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
+#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
+#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
+#endif
+
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 4k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ * On 440EPx the SPL is copied to SDRAM before the NAND controller is
+ * set up. While still running from cache, I experienced problems accessing
+ * the NAND controller. sr - 2006-08-25
+ */
+#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
+#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
+#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
+#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
+#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from */
+ /* this addr */
+#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
+#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
+
+/*
+ * Now the NAND chip has to be defined (no autodetection used!)
+ */
+#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
+#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
+#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
+#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
+#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
+
+#define CFG_NAND_ECCSIZE 256
+#define CFG_NAND_ECCBYTES 3
+#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+#define CFG_NAND_OOBSIZE 16
+#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
+
+#ifdef CFG_ENV_IS_IN_NAND
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
+ */
+#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
+#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
+
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
+#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+
+/*------------------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------------*/
+#if !defined(CONFIG_NAND_U_BOOT)
+/*
+ * NAND booting U-Boot version uses a fixed initialization, since the whole
+ * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
+ * code.
+ */
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
+#define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/
+#define CONFIG_DDR_ECC 1 /* with ECC support */
+#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
+#endif
+#define CFG_MBYTES_SDRAM 256 /* 256MB */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible) */
+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
+#define CONFIG_DTT_AD7414 1 /* use AD7414 */
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CFG_DTT_MAX_TEMP 70
+#define CFG_DTT_LOW_TEMP -30
+#define CFG_DTT_HYSTERESIS 3
+
+/* RTC configuration */
+#define CONFIG_RTC_M41T62 1
+#define CFG_I2C_RTC_ADDR 0x68
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
+#define CONFIG_PHY1_ADDR 1
+#define CONFIG_HAS_ETH0 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_NET_MULTI 1
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CONFIG_PHY_DYNAMIC_ANEG 1
+
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+/*-----------------------------------------------------------------------
+ * USB-OHCI
+ *----------------------------------------------------------------------*/
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#undef CFG_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */
+#define CFG_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
+#define CFG_OHCI_USE_NPS /* force NoPowerSwitching mode */
+#define CFG_USB_OHCI_REGS_BASE (CFG_AHB_BASE | 0xd0000)
+#define CFG_USB_OHCI_SLOT_NAME "ppc440"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
+/*-----------------------------------------------------------------------
+ * Default environment
+ *----------------------------------------------------------------------*/
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=canyonlands\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "net_nfs=tftp 200000 ${bootfile};" \
+ "run nfsargs addip addtty;" \
+ "bootm 200000\0" \
+ "net_nfs_fdt=tftp 200000 ${bootfile};" \
+ "tftp ${fdt_addr} ${fdt_file};" \
+ "run nfsargs addip addtty;" \
+ "bootm 200000 - ${fdt_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "rootpath=/opt/eldk/ppc_4xxFP\0" \
+ "bootfile=canyonlands/uImage\0" \
+ "fdt_file=canyonlands/canyonlands.dtb\0" \
+ "fdt_addr=400000\0" \
+ "kernel_addr=fc000000\0" \
+ "ramdisk_addr=fc200000\0" \
+ "initrd_high=30000000\0" \
+ "load=tftp 200000 canyonlands/u-boot.bin\0" \
+ "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
+ "cp.b ${fileaddr} fffa0000 ${filesize};" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load update\0" \
+ "nload=tftp 200000 canyonlands/u-boot-nand.bin\0" \
+ "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
+ "setenv filesize;saveenv\0" \
+ "nupd=run nload nupdate\0" \
+ "pciconfighost=1\0" \
+ "pcie_mode=RP:RP\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_USB
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
+
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/* Board-specific PCI */
+#define CFG_PCI_TARGET_INIT /* let board init pci target */
+#undef CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Internal Definitions
+ */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+
+/*
+ * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
+ * boot EBC mapping only supports a maximum of 16MBytes
+ * (4.ff00.0000 - 4.ffff.ffff).
+ * To solve this problem, the FLASH has to get remapped to another
+ * EBC address which accepts bigger regions:
+ *
+ * 0xfc00.0000 -> 4.cc00.0000
+ */
+
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+/* Memory Bank 3 (NOR-FLASH) initialization */
+#define CFG_EBC_PB3AP 0x10055e00
+#define CFG_EBC_PB3CR (CFG_BOOT_BASE_ADDR | 0x9a000)
+
+/* Memory Bank 0 (NAND-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x018003c0
+#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
+#else
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x10055e00
+#define CFG_EBC_PB0CR (CFG_BOOT_BASE_ADDR | 0x9a000)
+
+/* Memory Bank 3 (NAND-FLASH) initialization */
+#define CFG_EBC_PB3AP 0x018003c0
+#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
+#endif
+
+/* Memory Bank 2 (CPLD) initialization */
+#define CFG_EBC_PB2AP 0x00804240
+#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
+
+#define CFG_EBC_CFG 0xB8400000 /* EBC0_CFG */
+
+/*
+ * PPC4xx GPIO Configuration
+ */
+#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+{ \
+/* GPIO Core 0 */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
+{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
+}, \
+{ \
+/* GPIO Core 1 */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
+{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
+} \
+}
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h
index 5a85feb..4ecaf90 100644
--- a/include/configs/hcu4.h
+++ b/include/configs/hcu4.h
@@ -1,5 +1,5 @@
/*
- *(C) Copyright 2005-2007 Netstal Maschinen AG
+ *(C) Copyright 2005-2008 Netstal Maschinen AG
* Niklaus Giger (Niklaus.Giger@netstal.com)
*
* See file CREDITS for list of people who contributed to this
@@ -103,13 +103,19 @@
* Flash
*----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
+/* Use common CFI driver */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+/* board provides its own flash_init code */
+#define CONFIG_FLASH_CFI_LEGACY 1
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+#define CFG_FLASH_LEGACY_512Kx8 1
-#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
/*-----------------------------------------------------------------------
* Environment
diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h
index 2ed8530..f5f1197 100644
--- a/include/configs/hcu5.h
+++ b/include/configs/hcu5.h
@@ -349,12 +349,20 @@
* Flash
*----------------------------------------------------------------------*/
+/* Use common CFI driver */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+/* board provides its own flash_init code */
+#define CONFIG_FLASH_CFI_LEGACY 1
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+#define CFG_FLASH_LEGACY_512Kx8 1
+
+/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO
+
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index c3f10c7..ced7ba6 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -36,6 +36,7 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_BOARD_RESET 1 /* Call board_reset */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
@@ -86,6 +87,15 @@
#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
/* unused GPT0 COMP reg */
+/* Additional registers for watchdog timer post test */
+
+#define CFG_DSPIC_TEST_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP5)
+#define CFG_WATCHDOG_TIME_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP4)
+#define CFG_WATCHDOG_FLAGS_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP5)
+#define CFG_WATCHDOG_MAGIC 0x12480000
+#define CFG_WATCHDOG_MAGIC_MASK 0xFFFF0000
+#define CFG_DSPIC_TEST_MASK 0x00000001
+
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
@@ -156,10 +166,86 @@
CFG_POST_MEMORY | \
CFG_POST_RTC | \
CFG_POST_SPR | \
- CFG_POST_UART)
+ CFG_POST_UART | \
+ CFG_POST_SYSMON | \
+ CFG_POST_WATCHDOG | \
+ CFG_POST_DSP | \
+ CFG_POST_BSPEC1 | \
+ CFG_POST_BSPEC2 | \
+ CFG_POST_BSPEC3 | \
+ CFG_POST_BSPEC4 | \
+ CFG_POST_BSPEC5)
+
+#define CONFIG_POST_WATCHDOG {\
+ "Watchdog timer test", \
+ "watchdog", \
+ "This test checks the watchdog timer.", \
+ POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
+ &lwmon5_watchdog_post_test, \
+ NULL, \
+ NULL, \
+ CFG_POST_WATCHDOG \
+ }
+
+#define CONFIG_POST_BSPEC1 {\
+ "dsPIC init test", \
+ "dspic_init", \
+ "This test returns result of dsPIC READY test run earlier.", \
+ POST_RAM | POST_ALWAYS, \
+ &dspic_init_post_test, \
+ NULL, \
+ NULL, \
+ CFG_POST_BSPEC1 \
+ }
+
+#define CONFIG_POST_BSPEC2 {\
+ "dsPIC test", \
+ "dspic", \
+ "This test gets result of dsPIC POST and dsPIC version.", \
+ POST_RAM | POST_ALWAYS, \
+ &dspic_post_test, \
+ NULL, \
+ NULL, \
+ CFG_POST_BSPEC2 \
+ }
+
+#define CONFIG_POST_BSPEC3 {\
+ "FPGA test", \
+ "fpga", \
+ "This test checks FPGA registers and memory.", \
+ POST_RAM | POST_ALWAYS, \
+ &fpga_post_test, \
+ NULL, \
+ NULL, \
+ CFG_POST_BSPEC3 \
+ }
+
+#define CONFIG_POST_BSPEC4 {\
+ "GDC test", \
+ "gdc", \
+ "This test checks GDC registers and memory.", \
+ POST_RAM | POST_ALWAYS, \
+ &gdc_post_test, \
+ NULL, \
+ NULL, \
+ CFG_POST_BSPEC4 \
+ }
+
+#define CONFIG_POST_BSPEC5 {\
+ "SYSMON1 test", \
+ "sysmon1", \
+ "This test checks GPIO_62_EPX pin indicating power failure.", \
+ POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
+ &sysmon1_post_test, \
+ NULL, \
+ NULL, \
+ CFG_POST_BSPEC5 \
+ }
#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
#define CONFIG_LOGBUFFER
+#define CONFIG_ALT_LH_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP1)
+#define CONFIG_ALT_LB_ADDR (CFG_OCM_BASE)
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
/*-----------------------------------------------------------------------
@@ -181,6 +267,7 @@
#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
+#define CFG_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
#if 0
@@ -366,9 +453,6 @@
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
-/*
- * ToDo: Watchdog is not test fully, so exclude it for now
- */
#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
#define CONFIG_WD_PERIOD 40000 /* in usec */
@@ -431,10 +515,14 @@
#define CFG_GPIO_PHY1_RST 12
#define CFG_GPIO_FLASH_WP 14
#define CFG_GPIO_PHY0_RST 22
+#define CFG_GPIO_DSPIC_READY 51
#define CFG_GPIO_EEPROM_EXT_WP 55
+#define CFG_GPIO_HIGHSIDE 56
#define CFG_GPIO_EEPROM_INT_WP 57
+#define CFG_GPIO_BOARD_RESET 58
#define CFG_GPIO_LIME_S 59
#define CFG_GPIO_LIME_RST 60
+#define CFG_GPIO_SYSMON_STATUS 62
#define CFG_GPIO_WATCHDOG 63
/*-----------------------------------------------------------------------
diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h
new file mode 100644
index 0000000..c5b6e8f
--- /dev/null
+++ b/include/configs/mcu25.h
@@ -0,0 +1,361 @@
+/*
+ *(C) Copyright 2005-2007 Netstal Maschinen AG
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * mcu25.h - configuration for MCU25 board (similar to hcu4.h)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_MCU25 1 /* Board is MCU25 */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_405GP 1
+#define CONFIG_4xx 1
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+*----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+
+
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+
+/* ... with on-chip memory here (4KBytes) */
+#define CFG_OCM_DATA_ADDR 0xF4000000
+#define CFG_OCM_DATA_SIZE 0x00001000
+/* Do not set up locked dcache as init ram. */
+#undef CFG_INIT_DCACHE_CS
+
+/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
+#define CFG_TEMP_STACK_OCM 1
+
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#define CONFIG_SERIAL_MULTI 1
+/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */
+#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD 691200
+
+/* Size (bytes) of interrupt driven serial port buffer.
+ * Set to 0 to use polling instead of interrupts.
+ * Setting to 0 will also disable RTS/CTS handshaking.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+/* Set console baudrate to 9600 */
+#define CONFIG_BAUDRATE 9600
+
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Flash
+ *----------------------------------------------------------------------*/
+
+/* Use common CFI driver */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+/* board provides its own flash_init code */
+#define CONFIG_FLASH_CFI_LEGACY 1
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+#define CFG_FLASH_LEGACY_512Kx8 1
+
+/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+
+#undef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_NOWHERE
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+/* Put the environment after the SDRAM configuration */
+#define PROM_SIZE 2048
+#define CFG_ENV_OFFSET 512
+#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+/* Put the environment in Flash */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
+ * the first internal I2C controller of the PPC440EPx
+ *----------------------------------------------------------------------*/
+#define CFG_SPD_BUS_NUM 0
+
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/* This is the 7bit address of the device, not including P. */
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+
+/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#undef CFG_I2C_MULTI_EEPROMS
+
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+/* Setup some board specific values for the default environment variables */
+#define CONFIG_HOSTNAME mcu25
+#define CONFIG_IPADDR 172.25.1.99
+#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_SERVERIP 172.25.1.3
+
+#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=0x01000000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/home/diagnose/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/mcu25/uImage\0" \
+ "load=tftp 100000 mcu25/u-boot.bin\0" \
+ "update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \
+ "cp.b 100000 FFFB0000 50000\0" \
+ "upd=run load;run update\0" \
+ "vx_rom=mcu25/mcu25_vx_rom\0" \
+ "vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \
+ "vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \
+ " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run vx"
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1 /* PHY address */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descr */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+/* SPD EEPROM (sdram speed config) disabled */
+#define CONFIG_SPD_EEPROM 1
+#define SPD_EEPROM_ADDRESS 0x50
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_UART | \
+ CFG_POST_I2C | \
+ CFG_POST_CACHE | \
+ CFG_POST_ETHER | \
+ CFG_POST_SPR)
+
+#define CFG_POST_UART_TABLE {UART0_BASE}
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#undef CONFIG_LOGBUFFER
+#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+#define CFG_EBC_CFG 0x98400000
+
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x02005400
+#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit*/
+
+#define CFG_EBC_PB1AP 0x03041200
+#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
+
+#define CFG_EBC_PB2AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
+#define CFG_EBC_PB2CR 0x7A09A000u
+
+#define CFG_EBC_PB3AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
+#define CFG_EBC_PB3CR 0x7B09A000u
+
+#define CFG_EBC_PB4AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
+#define CFG_EBC_PB4CR 0x7C09A000u
+
+#define CFG_EBC_PB5AP 0x00800200u
+#define CFG_EBC_PB5CR 0x7D81A000u
+
+#define CFG_EBC_PB6AP 0x01040200u
+#define CFG_EBC_PB6CR 0x7D91A000u
+
+#define CFG_GPIO0_OR 0x087FFFFF /* GPIO value */
+#define CFG_GPIO0_TCR 0x7FFF8000 /* GPIO value */
+#define CFG_GPIO0_ODR 0xFFFF0000 /* GPIO value */
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/* Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
+
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR 0xF0000500
+
+#define CFG_HUSH_PARSER /* use "hush" command parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h
index 98facf2..b1e3d53 100644
--- a/include/configs/mgcoge.h
+++ b/include/configs/mgcoge.h
@@ -105,12 +105,11 @@
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
- "addcon=setenv bootargs ${bootargs} console=ttyCPM0,,${baudrate}\0" \
+ "addcon=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}:${netdev}:off panic=1 " \
- "console=${console}\0" \
+ "${netmask}:${hostname}:${netdev}:off panic=1\0" \
"net_nfs=tftp ${kernel_addr} ${bootfile}; " \
"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcon;"\
"bootm ${kernel_addr} - ${fdt_addr}\0" \
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index b035857..f12765d 100644
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -594,7 +594,5 @@ typedef unsigned int led_id_t;
#define OF_CPU "PowerPC,MPC870@0"
#define OF_TBCLK (MPC8XX_HZ / 16)
-#define CONFIG_OF_HAS_BD_T 1
-#define CONFIG_OF_HAS_UBOOT_ENV 1
#endif /* __CONFIG_H */
generated by cgit v1.1 at 2024-11-09 12:26:37 +0000