diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/IceCube.h | 2 | ||||
| -rw-r--r-- | include/configs/MPC8360EMDS.h | 6 | ||||
| -rw-r--r-- | include/configs/NC650.h | 12 | ||||
| -rw-r--r-- | include/configs/acadia.h | 300 | ||||
| -rw-r--r-- | include/configs/atstk1002.h | 69 | ||||
| -rw-r--r-- | include/configs/katmai.h | 2 | ||||
| -rw-r--r-- | include/configs/ml401.h | 230 | ||||
| -rw-r--r-- | include/configs/mpc7448hpc2.h | 411 | ||||
| -rw-r--r-- | include/configs/sc3.h | 10 | ||||
| -rw-r--r-- | include/configs/sequoia.h | 16 | ||||
| -rw-r--r-- | include/configs/suzaku.h | 7 | ||||
| -rw-r--r-- | include/configs/xupv2p.h | 174 | ||||
| -rw-r--r-- | include/configs/yosemite.h | 1 | ||||
| -rw-r--r-- | include/configs/yucca.h | 2 |
14 files changed, 1037 insertions, 205 deletions
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index c380c54..6c6480d 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -189,7 +189,7 @@ #define OF_CPU "PowerPC,5200@0" #define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" /* diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index d2af0e1..79937dc 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -342,8 +342,12 @@ #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 +#undef CONFIG_OF_FLAT_TREE #define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_HAS_BD_T 1 +#define CONFIG_OF_HAS_UBOOT_ENV 1 + /* maximum size of the flat tree (8K) */ #define OF_FLAT_TREE_MAX_SIZE 8192 diff --git a/include/configs/NC650.h b/include/configs/NC650.h index 8da29c4..a12c8da 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 Detlev Zundel, dzu@denx.de + * (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de * (C) Copyright 2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -237,18 +237,8 @@ /* * NAND flash support */ -#define CFG_NAND_LEGACY - #define CFG_MAX_NAND_DEVICE 1 -#define NAND_ChipID_UNKNOWN 0x00 -#define SECTORSIZE 512 -#define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define ADDR_COLUMN 1 -#define NAND_NO_RB - /*----------------------------------------------------------------------- * SYPCR - System Protection Control 11-9 diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 9e02ca3..35b6a51 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -31,20 +31,18 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_ACADIA 1 /* Board is Acadia */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_405EZ 1 /* Specifc 405EZ support*/ -#undef CFG_DRAM_TEST /* Disable-takes long time */ +#define CONFIG_ACADIA 1 /* Board is Acadia */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EZ 1 /* Specifc 405EZ support*/ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */ #define CONFIG_NO_SERIAL_EEPROM /*#undef CONFIG_NO_SERIAL_EEPROM*/ #ifdef CONFIG_NO_SERIAL_EEPROM - /*---------------------------------------------------------------------------- * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, * assuming a 66MHz input clock to the 405EZ. @@ -59,24 +57,125 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFE000000 #define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (384 * 1024)/* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */ + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xfe000000 #define CFG_MONITOR_BASE TEXT_BASE +#define CFG_CPLD_BASE 0x80000000 +#define CFG_NAND_ADDR 0xd0000000 #define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */ -/* - * Define here the location of the environment variables (FLASH). - * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only - * supported for backward compatibility. - */ +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */ + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #else - #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ #endif +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * RAM (CRAM) + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_RAM 64 /* 64MB */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_AD7414 1 /* use AD7414 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +#if 0 /* test-only... */ +/*----------------------------------------------------------------------- + * SPI stuff - Define to include SPI control + *----------------------------------------------------------------------- + */ +#define CONFIG_SPI +#endif + +/*----------------------------------------------------------------------- + * Ethernet + *----------------------------------------------------------------------*/ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" @@ -122,13 +221,6 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - #define CONFIG_USB_OHCI #define CONFIG_USB_STORAGE @@ -166,7 +258,6 @@ CFG_CMD_PCI | \ CFG_CMD_PING | \ CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ CFG_CMD_USB) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -174,76 +265,34 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -/* +/*----------------------------------------------------------------------- * Miscellaneous configurable options - */ + *----------------------------------------------------------------------*/ #define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#define CFG_BASE_BAUD 691200 -#define CONFIG_BAUDRATE 115200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_AD7414 1 /* use AD7414 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CFG_DTT_MAX_TEMP 70 -#define CFG_DTT_LOW_TEMP -30 -#define CFG_DTT_HYSTERESIS 3 - -#if 0 /* test-only... */ -/*----------------------------------------------------------------------- - * SPI stuff - Define to include SPI control - *----------------------------------------------------------------------- - */ -#define CONFIG_SPI -#endif - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -251,39 +300,13 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif - #ifdef TEST_ONLY_NAND /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ #define CFG_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 -#define CFG_NAND_BASE (CFG_NAND + CFG_NAND_CS) +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #endif @@ -297,50 +320,42 @@ #endif /*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup - */ -#define CFG_NAND 0xd0000000 + *----------------------------------------------------------------------*/ #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ -/* Memory Bank 0 (Flash) initialization */ +/* Memory Bank 0 (Flash) initialization */ #define CFG_EBC_PB0AP 0x03337200 -#define CFG_EBC_PB0CR 0xfe0bc000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=32bit */ +#define CFG_EBC_PB0CR 0xfe0bc000 -/* Memory Bank 1 (CRAM) initialization */ +/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/ +/* Memory Bank 1 (CRAM) initialization */ #define CFG_EBC_PB1AP 0x030400c0 #define CFG_EBC_PB1CR 0x000bc000 -/* Memory Bank 2 (CRAM) initialization */ +/* Memory Bank 2 (CRAM) initialization */ #define CFG_EBC_PB2AP 0x030400c0 #define CFG_EBC_PB2CR 0x020bc000 /* Memory Bank 3 (NAND-FLASH) initialization */ #define CFG_EBC_PB3AP 0x018003c0 -#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) +#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000) -/* Memory Bank 4 (CPLD) initialization */ +/* Memory Bank 4 (CPLD) initialization */ #define CFG_EBC_PB4AP 0x04006000 -#define CFG_EBC_PB4CR 0x80018000 /* BAS=0x000,BS=16MB,BU=R/W,BW=32bit */ +#define CFG_EBC_PB4CR (CFG_CPLD_BASE | 0x18000) #define CFG_EBC_CFG 0xf8400000 /*----------------------------------------------------------------------- + * GPIO Setup + *----------------------------------------------------------------------*/ +#define CFG_GPIO_CRAM_CLK 8 +#define CFG_GPIO_CRAM_WAIT 9 +#define CFG_GPIO_CRAM_ADV 10 +#define CFG_GPIO_CRAM_CRE (32 + 21) + +/*----------------------------------------------------------------------- * Definitions for GPIO_0 setup (PPC405EZ specific) * * GPIO0[0-3] - External Bus Controller CS_4 - CS_7 Outputs @@ -389,25 +404,6 @@ #define CFG_GPIO1_TSRL 0x00000000 #define CFG_GPIO1_TCR 0xFFFF8014 -/*----------------------------------------------------------------------- - * EPLD Regs. - */ -#define EPLD_BASE 0x80000000 -#define EPLD_ETHRSTBOOT 0x10 -#define EPLD_CTRL 0x14 -#define EPLD_MUXOE 0x16 - -/* - * State definations - */ -#define LOAK_INIT 0x494e4954 /* ASCII "INIT" */ -#define LOAK_NONE 0x4e4f4e45 /* ASCII "NONE" */ -#define LOAK_CRAM 0x4352414d /* ASCII "CRAM" */ -#define LOAK_PSRAM 0x50535241 /* ASCII "PSRA" - PSRAM */ -#define LOAK_OCM 0x4f434d20 /* ASCII "OCM " */ -#define LOAK_ZERO 0x5a45524f /* ASCII "ZERO" */ -#define LOAK_SPL 0x53504c20 /* ASCII "SPL" */ - /* * Internal Definitions * diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 458ebab..beaf385 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -62,11 +62,14 @@ */ #define CFG_PLL0_OPT 0x04 -#define CFG_USART1 1 - -#define CFG_CONSOLE_UART_DEV DEVICE_USART1 +#undef CONFIG_USART0 +#define CONFIG_USART1 1 +#undef CONFIG_USART2 +#undef CONFIG_USART3 /* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMDLINE_TAG 1 #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 @@ -75,16 +78,47 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS \ - "console=ttyUS0 root=/dev/mtdblock1 fbmem=600k" + "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2 fbmem=600k" + +#define CONFIG_BOOTCOMMAND \ + "fsload; bootm $(fileaddr)" + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 2 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * These are "locally administered ethernet addresses" generated by + * ./tools/gen_eth_addr + * + * After booting the board for the first time, new addresses should be + * generated and assigned to the environment variables "ethaddr" and + * "eth1addr". + */ +#define CONFIG_ETHADDR "6a:87:71:14:cd:cb" +#define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6" +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_SUBNETMASK \ + | CONFIG_BOOTP_GATEWAY) #define CONFIG_COMMANDS (CFG_CMD_BDI \ | CFG_CMD_LOADS \ | CFG_CMD_LOADB \ - /* | CFG_CMD_IMI */ \ + | CFG_CMD_IMI \ /* | CFG_CMD_CACHE */ \ | CFG_CMD_FLASH \ | CFG_CMD_MEMORY \ - /* | CFG_CMD_NET */ \ + | CFG_CMD_NET \ | CFG_CMD_ENV \ /* | CFG_CMD_IRQ */ \ | CFG_CMD_BOOTD \ @@ -96,7 +130,7 @@ /* | CFG_CMD_I2C */ \ | CFG_CMD_REGINFO \ /* | CFG_CMD_DATE */ \ - /* | CFG_CMD_DHCP */ \ + | CFG_CMD_DHCP \ /* | CFG_CMD_AUTOSCRIPT */ \ /* | CFG_CMD_MII */ \ | CFG_CMD_MISC \ @@ -106,19 +140,22 @@ /* | CFG_CMD_SAVES */ \ /* | CFG_CMD_SPI */ \ /* | CFG_CMD_PING */ \ - /* | CFG_CMD_MMC */ \ - /* | CFG_CMD_FAT */ \ - /* | CFG_CMD_IMLS */ \ + | CFG_CMD_MMC \ + | CFG_CMD_FAT \ + | CFG_CMD_IMLS \ /* | CFG_CMD_ITEST */ \ - /* | CFG_CMD_EXT2 */ \ + | CFG_CMD_EXT2 \ + | CFG_CMD_JFFS2 \ ) #include <cmd_confdefs.h> #define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 #define CONFIG_PIO2 1 #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 @@ -150,16 +187,8 @@ #define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) #define CFG_MALLOC_LEN (256*1024) -#define CFG_MALLOC_END \ - ({ \ - DECLARE_GLOBAL_DATA_PTR; \ - CFG_SDRAM_BASE + gd->sdram_size; \ - }) -#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN) - #define CFG_DMA_ALLOC_LEN (16384) -#define CFG_DMA_ALLOC_END (CFG_MALLOC_START) -#define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN) + /* Allow 2MB for the kernel run-time image */ #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) #define CFG_BOOTPARAMS_LEN (16 * 1024) diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 1606d0d..7f55366 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -78,7 +78,7 @@ #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) -#define CFG_ACE_BASE 0xe0000000 /* Xilinx ACE controller - Compact Flash */ +#define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */ /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in internal SRAM) diff --git a/include/configs/ml401.h b/include/configs/ml401.h new file mode 100644 index 0000000..cb159e7 --- /dev/null +++ b/include/configs/ml401.h @@ -0,0 +1,230 @@ +/* + * (C) Copyright 2007 Czech Technical University. + * + * Michal SIMEK <monstr@seznam.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "../board/xilinx/ml401/xparameters.h" + +#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */ +#define CONFIG_ML401 1 /* ML401 Board */ + +/* uart */ +#define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR +#define CONFIG_BAUDRATE XILINX_UART_BAUDRATE +#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE } + +/* setting reset address */ +#define CFG_RESET_ADDRESS TEXT_BASE + +/* ethernet */ +#define CONFIG_EMACLITE 1 +#define XPAR_EMAC_0_DEVICE_ID XPAR_XEMAC_NUM_INSTANCES + +/* gpio */ +#define CFG_GPIO_0 1 +#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR + +/* interrupt controller */ +#define CFG_INTC_0 1 +#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR +#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS + +/* timer */ +#define CFG_TIMER_0 1 +#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR +#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ +#define FREQUENCE XILINX_CLOCK_FREQ +#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 ) + +/* + * memory layout - Example + * TEXT_BASE = 0x1200_0000; + * CFG_SRAM_BASE = 0x1000_0000; + * CFG_SRAM_SIZE = 0x0400_0000; + * + * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000 + * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000 + * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 + * + * 0x1000_0000 CFG_SDRAM_BASE + * FREE + * 0x1200_0000 TEXT_BASE + * U-BOOT code + * 0x1202_0000 + * FREE + * + * STACK + * 0x13F7_F000 CFG_MALLOC_BASE + * MALLOC_AREA 256kB Alloc + * 0x11FB_F000 CFG_MONITOR_BASE + * MONITOR_CODE 256kB Env + * 0x13FF_F000 CFG_GBL_DATA_OFFSET + * GLOBAL_DATA 4kB bd, gd + * 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE + */ + +/* ddr sdram - main memory */ +#define CFG_SDRAM_BASE XILINX_RAM_START +#define CFG_SDRAM_SIZE XILINX_RAM_SIZE +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000) + +/* global pointer */ +#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */ +#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */ + +/* monitor code */ +#define SIZE 0x40000 +#define CFG_MONITOR_LEN SIZE +#define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN) +#define CFG_MONITOR_END (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_MALLOC_LEN SIZE +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) + +/* stack */ +#define CFG_INIT_SP_OFFSET CFG_MONITOR_BASE + +/*#define RAMENV */ +#define FLASH + +#ifdef FLASH + #define CFG_FLASH_BASE XILINX_FLASH_START + #define CFG_FLASH_SIZE XILINX_FLASH_SIZE + #define CFG_FLASH_CFI 1 + #define CFG_FLASH_CFI_DRIVER 1 + #define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */ + #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ + #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + + #ifdef RAMENV + #define CFG_ENV_IS_NOWHERE 1 + #define CFG_ENV_SIZE 0x1000 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE) + + #else /* !RAMENV */ + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR 0x40000 + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 + #endif /* !RAMBOOT */ +#else /* !FLASH */ + /* ENV in RAM */ + #define CFG_NO_FLASH 1 + #define CFG_ENV_IS_NOWHERE 1 + #define CFG_ENV_SIZE 0x1000 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE) +#endif /* !FLASH */ + +#ifdef FLASH + #ifdef RAMENV + #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\ + CFG_CMD_MEMORY |\ + CFG_CMD_MISC |\ + CFG_CMD_AUTOSCRIPT |\ + CFG_CMD_IRQ |\ + CFG_CMD_ASKENV |\ + CFG_CMD_BDI |\ + CFG_CMD_RUN |\ + CFG_CMD_LOADS |\ + CFG_CMD_LOADB |\ + CFG_CMD_IMI |\ + CFG_CMD_NET |\ + CFG_CMD_CACHE |\ + CFG_CMD_IMLS |\ + CFG_CMD_FLASH |\ + CFG_CMD_PING \ + ) + #else /* !RAMENV */ + #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\ + CFG_CMD_MEMORY |\ + CFG_CMD_MISC |\ + CFG_CMD_AUTOSCRIPT |\ + CFG_CMD_IRQ |\ + CFG_CMD_ASKENV |\ + CFG_CMD_BDI |\ + CFG_CMD_RUN |\ + CFG_CMD_LOADS |\ + CFG_CMD_LOADB |\ + CFG_CMD_IMI |\ + CFG_CMD_NET |\ + CFG_CMD_CACHE |\ + CFG_CMD_IMLS |\ + CFG_CMD_FLASH |\ + CFG_CMD_PING |\ + CFG_CMD_ENV |\ + CFG_CMD_SAVES \ + ) + + #endif + +#else /* !FLASH */ + #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\ + CFG_CMD_MEMORY |\ + CFG_CMD_MISC |\ + CFG_CMD_AUTOSCRIPT |\ + CFG_CMD_IRQ |\ + CFG_CMD_ASKENV |\ + CFG_CMD_BDI |\ + CFG_CMD_RUN |\ + CFG_CMD_LOADS |\ + CFG_CMD_LOADB |\ + CFG_CMD_IMI |\ + CFG_CMD_NET |\ + CFG_CMD_CACHE |\ + CFG_CMD_PING \ + ) +#endif /* !FLASH */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* Miscellaneous configurable options */ +#define CFG_PROMPT "U-Boot-mONStR> " +#define CFG_CBSIZE 512 /* size of console buffer */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */ +#define CFG_MAXARGS 15 /* max number of command args */ +#define CFG_LONGHELP +#define CFG_LOAD_ADDR 0x12000000 /* default load address */ + +#define CONFIG_BOOTDELAY 30 +#define CONFIG_BOOTARGS "root=romfs" +#define CONFIG_HOSTNAME "ml401" +#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" +#define CONFIG_IPADDR 192.168.0.3 +#define CONFIG_SERVERIP 192.168.0.5 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD + +/* architecture dependent code */ +#define CFG_USR_EXCEP /* user exception */ +#define CFG_HZ 1000 + +/* system ace */ +/*#define CONFIG_SYSTEMACE +#define DEBUG_SYSTEMACE +#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR +#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH +#define CONFIG_DOS_PARTITION +*/ +#endif /* __CONFIG_H */ diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h new file mode 100644 index 0000000..243a3f6 --- /dev/null +++ b/include/configs/mpc7448hpc2.h @@ -0,0 +1,411 @@ +/* + * Copyright (c) 2005 Freescale Semiconductor, Inc. + * + * (C) Copyright 2006 + * Alex Bounine , Tundra Semiconductor Corp. + * Roy Zang , <tie-fei.zang@freescale.com> Freescale Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board specific configuration options for Freescale + * MPC7448HPC2 (High-Performance Computing II) (Taiga) board + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* Board Configuration Definitions */ +/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */ + +#define CONFIG_MPC7448HPC2 + +#define CONFIG_74xx +#define CONFIG_750FX /* this option to enable init of extended BATs */ +#define CONFIG_ALTIVEC /* undef to disable */ + +#define CFG_BOARD_NAME "MPC7448 HPC II" +#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" + +#define CFG_OCN_CLK 133000000 /* 133 MHz */ +#define CFG_CONFIG_BUS_CLK 133000000 + +#define CFG_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */ + +#undef CONFIG_ECC /* disable ECC support */ + +/* Board-specific Initialization Functions to be called */ +#define CFG_BOARD_ASM_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_HAS_ETH1 + +#define CONFIG_ENV_OVERWRITE + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ + +/*#define CFG_HUSH_PARSER */ +#undef CFG_HUSH_PARSER + +#define CFG_PROMPT_HUSH_PS2 "> " + +/* Pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,7448@0" +#define OF_TSI "tsi108@c0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808" + +/* + * The following defines let you select what serial you want to use + * for your console driver. + * + * what to do: + * If you have hacked a serial cable onto the second DUART channel, + * change the CFG_DUART port from 1 to 0 below. + * + */ + +#define CONFIG_CONS_INDEX 1 +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK CFG_OCN_CLK * 8 + +#define CFG_NS16550_COM1 (CFG_TSI108_CSR_RST_BASE+0x7808) +#define CFG_NS16550_COM2 (CFG_TSI108_CSR_RST_BASE+0x7C08) +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#undef CONFIG_BOOTARGS +/* #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" + * to mount root filesystem over NFS;echo" */ + +#if (CONFIG_BOOTDELAY >= 0) +#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\ + setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ + ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; " + +#define CONFIG_BOOTARGS "console=ttyS0,115200" +#endif + +#undef CONFIG_EXTRA_ENV_SETTINGS + +#define CONFIG_SERIAL "No. 1" + +/* Networking Configuration */ + +#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */ + +#define CONFIG_TSI108_ETH +#define CONFIG_TSI108_ETH_NUM_PORTS 2 + +#define CONFIG_NET_MULTI + +#define CONFIG_BOOTFILE zImage.initrd.elf +#define CONFIG_LOADADDR 0x400000 + +/*-------------------------------------------------------------------------- */ + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_CACHE \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C \ + | CFG_CMD_SDRAM \ + | CFG_CMD_EEPROM \ + | CFG_CMD_FLASH \ + | CFG_CMD_ENV \ + | CFG_CMD_BSP \ + | CFG_CMD_DHCP \ + | CFG_CMD_PING \ + | CFG_CMD_DATE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/*set date in u-boot*/ +#define CONFIG_RTC_M48T35A +#define CFG_NVRAM_BASE_ADDR 0xfc000000 +#define CFG_NVRAM_SIZE 0x8000 +/* + * Miscellaneous configurable options + */ +#define CONFIG_VERSION_VARIABLE 1 +#define CONFIG_TSI108_I2C + +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)/* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00400000 /* default load address */ + +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + +/* + * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS + * To an unused memory region. The stack will remain in cache until RAM + * is initialized + */ +#undef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */ +#define CFG_INIT_RAM_END 0x4000/* larger space - we have SDRAM initialized */ + +#define CFG_GBL_DATA_SIZE 128/* size in bytes reserved for init data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ + +#define CFG_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */ +#define CFG_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */ + +#define CFG_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */ +#define CFG_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */ + +#define CFG_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */ + +#define CFG_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */ + +#define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */ + +#define CFG_FLASH_BASE 0xff000000 /* Base Address of Flash device */ +#define CFG_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */ + +#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */ + +#define PCI0_IO_BASE_BOOTM 0xfd000000 + +#define CFG_RESET_ADDRESS 0x3fffff00 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* u-boot code base */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ + +/* Peripheral Device section */ + +/* + * Resources on the Tsi108 + */ + +#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */ +#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */ + +#define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */ + +#undef DISABLE_PBM + +/* + * PCI stuff + * + */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_TSI108_PCI /* include tsi108 pci support */ + +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +/* PCI MEMORY MAP section */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +/* PCI Memory Space */ +#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS) +#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) /* 0xE0000000 */ +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */ + +/* PCI I/O Space */ +#define CFG_PCI_IO_BUS 0x00000000 +#define CFG_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */ + +#define CFG_PCI_IO_SIZE 0x01000000 /* 16MB */ + +#define _IO_BASE 0x00000000 /* points to PCI I/O space */ + +/* PCI Config Space mapping */ +#define CFG_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */ +#define CFG_PCI_CFG_SIZE 0x01000000 /* 16MB */ + +#define CFG_IBAT0U 0xFE0003FF +#define CFG_IBAT0L 0xFE000002 + +#define CFG_IBAT1U 0x00007FFF +#define CFG_IBAT1L 0x00000012 + +#define CFG_IBAT2U 0x80007FFF +#define CFG_IBAT2L 0x80000022 + +#define CFG_IBAT3U 0x00000000 +#define CFG_IBAT3L 0x00000000 + +#define CFG_IBAT4U 0x00000000 +#define CFG_IBAT4L 0x00000000 + +#define CFG_IBAT5U 0x00000000 +#define CFG_IBAT5L 0x00000000 + +#define CFG_IBAT6U 0x00000000 +#define CFG_IBAT6L 0x00000000 + +#define CFG_IBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 + +#define CFG_DBAT0U 0xE0003FFF +#define CFG_DBAT0L 0xE000002A + +#define CFG_DBAT1U 0x00007FFF +#define CFG_DBAT1L 0x00000012 + +#define CFG_DBAT2U 0x00000000 +#define CFG_DBAT2L 0x00000000 + +#define CFG_DBAT3U 0xC0000003 +#define CFG_DBAT3L 0xC000002A + +#define CFG_DBAT4U 0x00000000 +#define CFG_DBAT4L 0x00000000 + +#define CFG_DBAT5U 0x00000000 +#define CFG_DBAT5L 0x00000000 + +#define CFG_DBAT6U 0x00000000 +#define CFG_DBAT6L 0x00000000 + +#define CFG_DBAT7U 0x00000000 +#define CFG_DBAT7L 0x00000000 + +/* I2C addresses for the two DIMM SPD chips */ +#define DIMM0_I2C_ADDR 0x51 +#define DIMM1_I2C_ADDR 0x52 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1/* Flash can be at one of two addresses */ +#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_WRITE_SWAPPED_DATA + +#define PHYS_FLASH_SIZE 0x01000000 +#define CFG_MAX_FLASH_SECT (128) + +#define CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_ADDR 0xFC000000 + +#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * L2CR setup -- make sure this is right for your board! + * look in include/mpc74xx.h for the defines used here + */ +#undef CFG_L2 + +#define L2_INIT 0 +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CFG_SERIAL_HANG_IN_EXCEPTION +#endif /* __CONFIG_H */ diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 8298084..6b6acfa 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -133,8 +133,8 @@ #if 1 /* feel free to disable for development */ #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with S\n" -#define CONFIG_AUTOBOOT_DELAY_STR "S" /* 1st "password" */ +#define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with ENTER\n" +#define CONFIG_AUTOBOOT_DELAY_STR "\n" /* 1st "password" */ #endif /* @@ -416,11 +416,11 @@ extern unsigned long offsetOfEnvironment; #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -/* No command line, one static partition Partition 3 contains jffs2 rootfs */ +/* No command line, one static partition */ #undef CONFIG_JFFS2_CMDLINE #define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_SIZE 0x00400000 -#define CONFIG_JFFS2_PART_OFFSET 0x00c00000 +#define CONFIG_JFFS2_PART_SIZE 0x01000000 +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 29f3b40..1f19621 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -33,7 +33,6 @@ *----------------------------------------------------------------------*/ /* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ #ifndef CONFIG_RAINIER -#define CONFIG_SEQUOIA 1 /* Board is Sequoia */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ #else #define CONFIG_440GRX 1 /* Specific PPC440GRx */ @@ -75,9 +74,7 @@ * Initial RAM & stack pointer *----------------------------------------------------------------------*/ /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ - #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) @@ -381,9 +378,6 @@ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ -#define CFG_FLASH CFG_FLASH_BASE -#define CFG_NAND 0xD0000000 -#define CFG_CPLD 0xC0000000 /* * On Sequoia CS0 and CS3 are switched when configuring for NAND booting @@ -392,25 +386,25 @@ #define CFG_NAND_CS 3 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x03017200 -#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) +#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000) /* Memory Bank 3 (NAND-FLASH) initialization */ #define CFG_EBC_PB3AP 0x018003c0 -#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) +#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000) #else #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ /* Memory Bank 3 (NOR-FLASH) initialization */ #define CFG_EBC_PB3AP 0x03017200 -#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000) +#define CFG_EBC_PB3CR (CFG_FLASH_BASE | 0xda000) /* Memory Bank 0 (NAND-FLASH) initialization */ #define CFG_EBC_PB0AP 0x018003c0 -#define CFG_EBC_PB0CR (CFG_NAND | 0x1c000) +#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000) #endif /* Memory Bank 2 (CPLD) initialization */ #define CFG_EBC_PB2AP 0x24814580 -#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000) +#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000) /*----------------------------------------------------------------------- * NAND FLASH diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h index 1ee6be1..8224555 100644 --- a/include/configs/suzaku.h +++ b/include/configs/suzaku.h @@ -44,12 +44,17 @@ #define CFG_FLASH_SIZE 0x00400000 #define CFG_RESET_ADDRESS 0xfff00100 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - (1024 * 1024)) +#define CFG_MONITOR_BASE (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - (1024 * 1024)) #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - (1024 * 1024)) #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 115200 } +/* System Register (GPIO) */ +#define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000 +#define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0) + #define CONFIG_COMMANDS (CONFIG__CMD_DFL) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h new file mode 100644 index 0000000..a2f4810 --- /dev/null +++ b/include/configs/xupv2p.h @@ -0,0 +1,174 @@ +/* + * (C) Copyright 2007 Czech Technical University. + * + * Michal SIMEK <monstr@monstr.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "../board/xilinx/xupv2p/xparameters.h" + +#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */ +#define CONFIG_XUPV2P 1 + +/* uart */ +#define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR +#define CONFIG_BAUDRATE XILINX_UART_BAUDRATE +#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE } + +/* ethernet */ +#define CONFIG_EMAC 1 +#define XPAR_EMAC_0_DEVICE_ID XPAR_XEMAC_NUM_INSTANCES + +/* + * setting reset address + * + * TEXT_BASE is set to place, where the U-BOOT run in RAM, but + * if you want to store U-BOOT in flash, set CFG_RESET_ADDRESS + * to FLASH memory and after loading bitstream jump to FLASH. + * U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze + * jump to CFG_RESET_ADDRESS where is the original U-BOOT code. + */ +#define CFG_RESET_ADDRESS 0x36000000 + +/* gpio */ +#define CFG_GPIO_0 1 +#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR + +/* interrupt controller */ +#define CFG_INTC_0 1 +#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR +#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS + +/* timer */ +#define CFG_TIMER_0 1 +#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR +#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ +#define FREQUENCE XILINX_CLOCK_FREQ +#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 ) + +/* + * memory layout - Example + * TEXT_BASE = 0x3600_0000; + * CFG_SRAM_BASE = 0x3000_0000; + * CFG_SRAM_SIZE = 0x1000_0000; + * + * CFG_GBL_DATA_OFFSET = 0x3000_0000 + 0x1000_0000 - 0x1000 = 0x3FFF_F000 + * CFG_MONITOR_BASE = 0x3FFF_F000 - 0x40000 = 0x3FFB_F000 + * CFG_MALLOC_BASE = 0x3FFB_F000 - 0x40000 = 0x3FF7_F000 + * + * 0x3000_0000 CFG_SDRAM_BASE + * FREE + * 0x3600_0000 TEXT_BASE + * U-BOOT code + * 0x3602_0000 + * FREE + * + * STACK + * 0x3FF7_F000 CFG_MALLOC_BASE + * MALLOC_AREA 256kB Alloc + * 0x3FFB_F000 CFG_MONITOR_BASE + * MONITOR_CODE 256kB Env + * 0x3FFF_F000 CFG_GBL_DATA_OFFSET + * GLOBAL_DATA 4kB bd, gd + * 0x4000_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE + */ + +/* ddr sdram - main memory */ +#define CFG_SDRAM_BASE XILINX_RAM_START +#define CFG_SDRAM_SIZE XILINX_RAM_SIZE +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000) + +/* global pointer */ +#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */ +#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */ + +/* monitor code */ +#define SIZE 0x40000 +#define CFG_MONITOR_LEN SIZE +#define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN) +#define CFG_MONITOR_END (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_MALLOC_LEN SIZE +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) + +/* stack */ +#define CFG_INIT_SP_OFFSET CFG_MALLOC_BASE + +#define CFG_NO_FLASH 1 +#define CFG_ENV_IS_NOWHERE 1 +#define CFG_ENV_SIZE 0x1000 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE) +#define CONFIG_COMMANDS (CONFIG__CMD_DFL |\ + CFG_CMD_MEMORY |\ + CFG_CMD_IRQ |\ + CFG_CMD_BDI |\ + CFG_CMD_NET |\ + CFG_CMD_IMI |\ + CFG_CMD_ECHO |\ + CFG_CMD_CACHE |\ + CFG_CMD_RUN |\ + CFG_CMD_AUTOSCRIPT |\ + CFG_CMD_ASKENV |\ + CFG_CMD_LOADS |\ + CFG_CMD_LOADB |\ + CFG_CMD_MISC |\ + CFG_CMD_PING \ + ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* Miscellaneous configurable options */ +#define CFG_PROMPT "U-Boot-mONStR> " +#define CFG_CBSIZE 512 /* size of console buffer */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */ +#define CFG_MAXARGS 15 /* max number of command args */ +#define CFG_LONGHELP +#define CFG_LOAD_ADDR 0x12000000 /* default load address */ + +#define CONFIG_BOOTDELAY 30 +#define CONFIG_BOOTARGS "root=romfs" +#define CONFIG_HOSTNAME "ml401" +#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" +#define CONFIG_IPADDR 192.168.0.3 +#define CONFIG_SERVERIP 192.168.0.5 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD + +/* architecture dependent code */ +#define CFG_USR_EXCEP /* user exception */ +#define CFG_HZ 1000 + +#define CONFIG_PREBOOT "echo U-BOOT by mONStR;" \ + "base 0;" \ + "echo" + + +/* system ace */ +/*#define CONFIG_SYSTEMACE +#define DEBUG_SYSTEMACE +#define CFG_SYSTEMACE_BASE 0xCF000000 +#define CFG_SYSTEMACE_WIDTH 16 +#define CONFIG_DOS_PARTITION*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index b59f75b..0a41dff 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -32,7 +32,6 @@ *----------------------------------------------------------------------*/ /* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/ #ifndef CONFIG_YELLOWSTONE -#define CONFIG_YOSEMITE 1 /* Board is Yosemite */ #define CONFIG_440EP 1 /* Specific PPC440EP support */ #define CONFIG_HOSTNAME yosemite #else diff --git a/include/configs/yucca.h b/include/configs/yucca.h index eb4859c..7f8b022 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -120,7 +120,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ #define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ -#undef CONFIG_DDR_ECC /* no ECC support for now */ +#define CONFIG_DDR_ECC 1 /* with ECC support */ /*----------------------------------------------------------------------- * I2C |