diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/bamboo.h | 154 | ||||
| -rw-r--r-- | include/configs/walnut.h | 112 | ||||
| -rw-r--r-- | include/configs/yellowstone.h | 62 | ||||
| -rw-r--r-- | include/configs/yosemite.h | 68 |
4 files changed, 198 insertions, 198 deletions
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index da3c29f..6ccd8b9 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -30,13 +30,13 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_BAMBOO 1 /* Board is BAMBOO */ -#define CONFIG_440_EP 1 /* Specific PPC440EP support */ +#define CONFIG_BAMBOO 1 /* Board is BAMBOO */ +#define CONFIG_440_EP 1 /* Specific PPC440EP support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#undef CFG_DRAM_TEST /* disable - takes long time! */ -//#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#undef CFG_DRAM_TEST /* disable - takes long time! */ +/*#define CONFIG_SYS_CLK_FREQ 66666666 /X* external freq to pll */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ /*----------------------------------------------------------------------- @@ -64,24 +64,24 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */ +#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */ #define CFG_INIT_RAM_END 0x2000 -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ -#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */ -//#define CFG_SDRAM_BANKS (2) -#define CFG_SDRAM_BANKS (1) +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ +#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */ +/*#define CFG_SDRAM_BANKS (2) */ +#define CFG_SDRAM_BANKS (1) /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 /*define this if you want console on UART1*/ #undef CONFIG_UART1_CONSOLE @@ -95,8 +95,8 @@ * The DS1558 code assumes this condition * *----------------------------------------------------------------------*/ -#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ -#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ +#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ +#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ /*----------------------------------------------------------------------- * FLASH related @@ -109,9 +109,9 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */ #else -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ @@ -125,7 +125,7 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ /*----------------------------------------------------------------------- * I2C @@ -139,9 +139,9 @@ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/ +#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/ #undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ -#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_IS_IN_EEPROM 1 /* Define to allow the user to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -158,12 +158,12 @@ #define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */ #define CONFIG_BOOTDELAY 3 /* disable autoboot */ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 /* required for netconsole */ -#define CONFIG_PHY1_ADDR 3 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 /* required for netconsole */ +#define CONFIG_PHY1_ADDR 3 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_NETMASK 255.255.255.0 @@ -196,49 +196,49 @@ #ifdef CONFIG_440_EP /* Need to define POST */ -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - /* CFG_CMD_EXT2 |*/ \ - /* CFG_CMD_FAT |*/ \ - CFG_CMD_I2C | \ - /* CFG_CMD_IDE |*/ \ - CFG_CMD_IRQ | \ - /* CFG_CMD_KGDB |*/ \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_FLASH | \ - /* CFG_CMD_SPI |*/ \ - CFG_CMD_USB | \ +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + /* CFG_CMD_EXT2 |*/ \ + /* CFG_CMD_FAT |*/ \ + CFG_CMD_I2C | \ + /* CFG_CMD_IDE |*/ \ + CFG_CMD_IRQ | \ + /* CFG_CMD_KGDB |*/ \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_FLASH | \ + /* CFG_CMD_SPI |*/ \ + CFG_CMD_USB | \ 0 ) & ~CFG_CMD_IMLS) #else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - /* CFG_CMD_EXT2 |*/ \ - /* CFG_CMD_FAT |*/ \ - CFG_CMD_I2C | \ - /* CFG_CMD_IDE |*/ \ - CFG_CMD_IRQ | \ - /* CFG_CMD_KGDB |*/ \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_FLASH | \ - /* CFG_CMD_SPI |*/ \ +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + /* CFG_CMD_EXT2 |*/ \ + /* CFG_CMD_FAT |*/ \ + CFG_CMD_I2C | \ + /* CFG_CMD_IDE |*/ \ + CFG_CMD_IRQ | \ + /* CFG_CMD_KGDB |*/ \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_FLASH | \ + /* CFG_CMD_SPI |*/ \ 0 ) & ~CFG_CMD_IMLS) #endif @@ -263,8 +263,8 @@ #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_LYNXKDI 1 /* support kdi files */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CONFIG_LYNXKDI 1 /* support kdi files */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ @@ -273,18 +273,18 @@ *----------------------------------------------------------------------- */ /* General PCI */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT -#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ -#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ /* * For booting Linux, the board info and command line data diff --git a/include/configs/walnut.h b/include/configs/walnut.h index ac5b530..3a8e61c 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -34,21 +34,21 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_WALNUT 1 /* ...on a WALNUT board */ - /* ...and on a SYCAMORE board */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_WALNUT 1 /* ...on a WALNUT board */ + /* ...and on a SYCAMORE board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CONFIG_PREBOOT "echo;" \ +#define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "hostname=walnut\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ @@ -62,15 +62,15 @@ "bootm $(kernel_addr)\0" \ "flash_self=run ramargs addip addtty;" \ "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ - "bootm\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=/tftpboot/walnut/uImage\0" \ "kernel_addr=fff80000\0" \ "ramdisk_addr=fff80000\0" \ "load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ + "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ "" @@ -88,7 +88,7 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ @@ -105,7 +105,7 @@ CFG_CMD_NFS | \ CFG_CMD_PCI | \ CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ + CFG_CMD_REGINFO | \ CFG_CMD_SDRAM | \ CFG_CMD_SNTP ) @@ -122,9 +122,9 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ @@ -143,9 +143,9 @@ * set Linux BASE_BAUD to 403200. */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CFG_BASE_BAUD 691200 +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CFG_BASE_BAUD 691200 /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ @@ -154,10 +154,10 @@ #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ @@ -168,7 +168,7 @@ *----------------------------------------------------------------------- */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F @@ -176,24 +176,24 @@ * PCI stuff *----------------------------------------------------------------------- */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -209,10 +209,10 @@ /* * Define here the location of the environment variables (FLASH or NVRAM). * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only - * supported for backward compatibility. + * supported for backward compatibility. */ #if 1 -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #else #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ #endif @@ -227,8 +227,8 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ @@ -238,14 +238,14 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_FLASH_ADDR0 0x5555 -#define CFG_FLASH_ADDR1 0x2aaa -#define CFG_FLASH_WORD_SIZE unsigned char +#define CFG_FLASH_ADDR0 0x5555 +#define CFG_FLASH_ADDR1 0x2aaa +#define CFG_FLASH_WORD_SIZE unsigned char #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) @@ -280,44 +280,44 @@ /* Memory Bank 0 (Flash Bank 0) initialization */ #define CFG_EBC_PB0AP 0x9B015480 -#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ #define CFG_EBC_PB1AP 0x02815480 -#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ #define CFG_EBC_PB2AP 0x04815A80 -#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ #define CFG_EBC_PB3AP 0x01815280 -#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ #define CFG_EBC_PB7AP 0x01815280 -#define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ /*----------------------------------------------------------------------- * External peripheral base address *----------------------------------------------------------------------- */ -#define CFG_KEY_REG_BASE_ADDR 0xF0100000 -#define CFG_IR_REG_BASE_ADDR 0xF0200000 -#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 +#define CFG_KEY_REG_BASE_ADDR 0xF0100000 +#define CFG_IR_REG_BASE_ADDR 0xF0200000 +#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area */ -#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ +#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ -#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Definitions for Serial Presence Detect EEPROM address * (to get SDRAM settings) */ -#define SPD_EEPROM_ADDRESS 0x50 +#define SPD_EEPROM_ADDRESS 0x50 /* * Internal Definitions diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h index 90418e0..d83d8e7 100644 --- a/include/configs/yellowstone.h +++ b/include/configs/yellowstone.h @@ -28,11 +28,11 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_YELLOWSTONE 1 /* Board is BAMBOO */ +#define CONFIG_YELLOWSTONE 1 /* Board is BAMBOO */ #define CONFIG_440_GR 1 /* Specific PPC440GR support */ #define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #undef CFG_DRAM_TEST /* disable - takes long time! */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ @@ -63,14 +63,14 @@ *----------------------------------------------------------------------*/ #define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */ #define CFG_INIT_RAM_END 0x2000 -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ -#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */ -#define CFG_SDRAM_BANKS (2) +#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */ +#define CFG_SDRAM_BANKS (2) /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ @@ -92,7 +92,7 @@ * *----------------------------------------------------------------------*/ #define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ -#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ +#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ /*----------------------------------------------------------------------- * FLASH related @@ -107,7 +107,7 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ /*----------------------------------------------------------------------- * I2C @@ -121,7 +121,7 @@ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/ +#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/ #undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ #define CFG_ENV_IS_IN_EEPROM 1 @@ -144,7 +144,7 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 /* required for netconsole */ +#define CONFIG_NET_MULTI 1 /* required for netconsole */ #define CONFIG_PHY1_ADDR 3 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ @@ -178,48 +178,48 @@ #ifdef CONFIG_440_EP /* Need to define POST */ -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ - /* CFG_CMD_EXT2 |*/ \ + /* CFG_CMD_EXT2 |*/ \ /* CFG_CMD_FAT |*/ \ CFG_CMD_I2C | \ /* CFG_CMD_IDE |*/ \ CFG_CMD_IRQ | \ - /* CFG_CMD_KGDB |*/ \ - CFG_CMD_MII | \ + /* CFG_CMD_KGDB |*/ \ + CFG_CMD_MII | \ CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ CFG_CMD_SDRAM | \ - CFG_CMD_FLASH | \ + CFG_CMD_FLASH | \ /* CFG_CMD_SPI |*/ \ CFG_CMD_USB | \ 0 ) & ~CFG_CMD_IMLS) #else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ - /* CFG_CMD_EXT2 |*/ \ + /* CFG_CMD_EXT2 |*/ \ /* CFG_CMD_FAT |*/ \ CFG_CMD_I2C | \ /* CFG_CMD_IDE |*/ \ CFG_CMD_IRQ | \ - /* CFG_CMD_KGDB |*/ \ - CFG_CMD_MII | \ + /* CFG_CMD_KGDB |*/ \ + CFG_CMD_MII | \ CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ CFG_CMD_SDRAM | \ - CFG_CMD_FLASH | \ + CFG_CMD_FLASH | \ /* CFG_CMD_SPI |*/ \ 0 ) & ~CFG_CMD_IMLS) #endif @@ -246,7 +246,7 @@ #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_LYNXKDI 1 /* support kdi files */ +#define CONFIG_LYNXKDI 1 /* support kdi files */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ @@ -255,18 +255,18 @@ *----------------------------------------------------------------------- */ /* General PCI */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT -#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ -#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ /* * For booting Linux, the board info and command line data diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 5f88306..18d6623 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -28,11 +28,11 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_YOSEMITE 1 /* Board is BAMBOO */ +#define CONFIG_YOSEMITE 1 /* Board is BAMBOO */ #define CONFIG_440_EP 1 /* Specific PPC440EP support */ #define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #undef CFG_DRAM_TEST /* disable - takes long time! */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ @@ -63,14 +63,14 @@ *----------------------------------------------------------------------*/ #define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */ #define CFG_INIT_RAM_END 0x2000 -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ -#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */ -#define CFG_SDRAM_BANKS (2) +#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */ +#define CFG_SDRAM_BANKS (2) /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ @@ -92,7 +92,7 @@ * *----------------------------------------------------------------------*/ #define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ -#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ +#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ /*----------------------------------------------------------------------- * FLASH related @@ -105,9 +105,9 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */ #else -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ @@ -121,7 +121,7 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ /*----------------------------------------------------------------------- * I2C @@ -135,7 +135,7 @@ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/ +#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/ #undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ #define CFG_ENV_IS_IN_EEPROM 1 @@ -158,7 +158,7 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 /* required for netconsole */ +#define CONFIG_NET_MULTI 1 /* required for netconsole */ #define CONFIG_PHY1_ADDR 3 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ @@ -192,48 +192,48 @@ #ifdef CONFIG_440_EP /* Need to define POST */ -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ - /* CFG_CMD_EXT2 |*/ \ + /* CFG_CMD_EXT2 |*/ \ /* CFG_CMD_FAT |*/ \ CFG_CMD_I2C | \ /* CFG_CMD_IDE |*/ \ CFG_CMD_IRQ | \ - /* CFG_CMD_KGDB |*/ \ - CFG_CMD_MII | \ + /* CFG_CMD_KGDB |*/ \ + CFG_CMD_MII | \ CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ CFG_CMD_SDRAM | \ - CFG_CMD_FLASH | \ + CFG_CMD_FLASH | \ /* CFG_CMD_SPI |*/ \ CFG_CMD_USB | \ 0 ) & ~CFG_CMD_IMLS) #else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ - /* CFG_CMD_EXT2 |*/ \ + /* CFG_CMD_EXT2 |*/ \ /* CFG_CMD_FAT |*/ \ CFG_CMD_I2C | \ /* CFG_CMD_IDE |*/ \ CFG_CMD_IRQ | \ - /* CFG_CMD_KGDB |*/ \ - CFG_CMD_MII | \ + /* CFG_CMD_KGDB |*/ \ + CFG_CMD_MII | \ CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ CFG_CMD_SDRAM | \ - CFG_CMD_FLASH | \ + CFG_CMD_FLASH | \ /* CFG_CMD_SPI |*/ \ 0 ) & ~CFG_CMD_IMLS) #endif @@ -260,7 +260,7 @@ #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_LYNXKDI 1 /* support kdi files */ +#define CONFIG_LYNXKDI 1 /* support kdi files */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ @@ -269,18 +269,18 @@ *----------------------------------------------------------------------- */ /* General PCI */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT -#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ -#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ /* * For booting Linux, the board info and command line data |