diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/M5235EVB.h | 7 | ||||
| -rw-r--r-- | include/configs/M5249EVB.h | 4 | ||||
| -rw-r--r-- | include/configs/M5253DEMO.h | 11 | ||||
| -rw-r--r-- | include/configs/M5271EVB.h | 2 | ||||
| -rw-r--r-- | include/configs/M5272C3.h | 5 | ||||
| -rw-r--r-- | include/configs/M5275EVB.h | 5 | ||||
| -rw-r--r-- | include/configs/M5282EVB.h | 4 | ||||
| -rw-r--r-- | include/configs/M54451EVB.h | 5 | ||||
| -rw-r--r-- | include/configs/M54455EVB.h | 5 | ||||
| -rw-r--r-- | include/configs/M5475EVB.h | 2 | ||||
| -rw-r--r-- | include/configs/M5485EVB.h | 2 | ||||
| -rw-r--r-- | include/configs/ads5121.h | 1 | ||||
| -rw-r--r-- | include/configs/ap325rxa.h | 177 | ||||
| -rw-r--r-- | include/configs/rsk7203.h | 107 | ||||
| -rw-r--r-- | include/configs/sequoia.h | 2 | ||||
| -rw-r--r-- | include/configs/sh7785lcr.h | 167 | ||||
| -rw-r--r-- | include/configs/smdk6400.h | 307 |
17 files changed, 793 insertions, 20 deletions
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index e836132..b32eabe 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -102,12 +102,15 @@ /* I2C */ #define CONFIG_FSL_I2C -#define CONFIG_HARD_I2C /* I2C with hw support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 80000 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_OFFSET 0x00000300 #define CFG_IMMR CFG_MBAR +#define CFG_I2C_PINMUX_REG (gpio->par_qspi) +#define CFG_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) +#define CFG_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index c2f5dd9..6bf2d99 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -41,8 +41,8 @@ #define CONFIG_MCFUART #define CFG_UART_PORT (0) -#define CONFIG_BAUDRATE 19200 -#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #undef CONFIG_WATCHDOG diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index f2c2317..9f78f6e 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -118,6 +118,17 @@ #define CONFIG_HOSTNAME M5253DEMO +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#define CFG_I2C_SPEED 80000 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x00000280 +#define CFG_IMMR CFG_MBAR +#define CFG_I2C_PINMUX_REG (*(u32 *) (CFG_MBAR+0x19C)) +#define CFG_I2C_PINMUX_CLR (0xFFFFE7FF) +#define CFG_I2C_PINMUX_SET (0) + #define CFG_PROMPT "=> " #define CFG_LONGHELP /* undef to save memory */ diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index 12f9783..78a1b93 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -42,7 +42,7 @@ #define CONFIG_MCFUART #define CFG_UART_PORT (0) -#define CONFIG_BAUDRATE 19200 +#define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #undef CONFIG_WATCHDOG /* disable watchdog */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 7edd322..fc457e3 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -40,8 +40,8 @@ #define CONFIG_MCFUART #define CFG_UART_PORT (0) -#define CONFIG_BAUDRATE 19200 -#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ @@ -91,6 +91,7 @@ #ifdef CONFIG_MCFFEC # define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 # define CFG_DISCOVER_PHY # define CFG_RX_ETH_BUFFER 8 # define CFG_FAULT_ECHO_LINK_DOWN diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 30c70e5..430af6b 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -45,7 +45,7 @@ #define CONFIG_MCFUART #define CFG_UART_PORT (0) -#define CONFIG_BAUDRATE 19200 +#define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } /* Configuration for environment @@ -118,6 +118,9 @@ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_OFFSET 0x00000300 #define CFG_IMMR CFG_MBAR +#define CFG_I2C_PINMUX_REG (gpio_reg->par_feci2c) +#define CFG_I2C_PINMUX_CLR (0xFFF0) +#define CFG_I2C_PINMUX_SET (0x000F) #ifdef CONFIG_MCFFEC #define CONFIG_ETHADDR 00:06:3b:01:41:55 diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 279a12b..eb59c25 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -40,8 +40,8 @@ #define CONFIG_MCFUART #define CFG_UART_PORT (0) -#define CONFIG_BAUDRATE 19200 -#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 588c00c..cf58239 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -140,9 +140,8 @@ "u-boot=u-boot.bin\0" \ "load=tftp ${loadaddr) ${u-boot}\0" \ "upd=run load; run prog\0" \ - "prog=prot off 0 " MK_STR(CFG_UBOOT_END)\ - "; era 0 " MK_STR(CFG_UBOOT_END) \ - "2ffff;" \ + "prog=prot off 0 " MK_STR(CFG_UBOOT_END) \ + "; era 0 " MK_STR(CFG_UBOOT_END) " ;" \ "cp.b ${loadaddr} 0 ${filesize};" \ "save\0" \ "" diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 476aba3..ad9c15e 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -157,7 +157,7 @@ " " MK_STR(CFG_UBOOT_END) ";" \ "era " MK_STR(CFG_FLASH_BASE) " " \ MK_STR(CFG_UBOOT_END) ";" \ - "cp.b ${loadaddr} " MK_STR(CFG_FLASH_BASE)\ + "cp.b ${loadaddr} " MK_STR(CFG_FLASH_BASE) \ " ${filesize}; save\0" \ "" #endif @@ -388,9 +388,6 @@ #endif #endif -#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ -#define CFG_FLASH_CHECKSUM - /* * This is setting for JFFS2 support in u-boot. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index 4037efb..af6723c 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -226,7 +226,7 @@ */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_SDRAM_CFG1 0x73711630 -#define CFG_SDRAM_CFG2 0x46370000 +#define CFG_SDRAM_CFG2 0x46770000 #define CFG_SDRAM_CTRL 0xE10B0000 #define CFG_SDRAM_EMOD 0x40010000 #define CFG_SDRAM_MODE 0x018D0000 diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index a14c55b..248db53 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -212,7 +212,7 @@ */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_SDRAM_CFG1 0x73711630 -#define CFG_SDRAM_CFG2 0x46370000 +#define CFG_SDRAM_CFG2 0x46770000 #define CFG_SDRAM_CTRL 0xE10B0000 #define CFG_SDRAM_EMOD 0x40010000 #define CFG_SDRAM_MODE 0x018D0000 diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 5f74afb..f516c46 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -210,6 +210,7 @@ #define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ #define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ +#define CFG_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */ /* Use SRAM for initial stack */ #define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */ diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h new file mode 100644 index 0000000..81a118d --- /dev/null +++ b/include/configs/ap325rxa.h @@ -0,0 +1,177 @@ +/* + * Configuation settings for the Renesas Solutions AP-325RXA board + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __AP325RXA_H +#define __AP325RXA_H + +#undef DEBUG +#define CONFIG_SH 1 +#define CONFIG_SH4 1 +#define CONFIG_CPU_SH7723 1 +#define CONFIG_AP325RXA 1 + +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_ENV +#define CONFIG_CMD_IDE +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION + +#define CONFIG_BAUDRATE 38400 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttySC2,38400" + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +/* SMC9118 */ +#define CONFIG_DRIVER_SMC911X 1 +#define CONFIG_DRIVER_SMC911X_32_BIT 1 +#define CONFIG_DRIVER_SMC911X_BASE 0xB6080000 + +/* MEMORY */ +#define AP325RXA_SDRAM_BASE (0x88000000) +#define AP325RXA_FLASH_BASE_1 (0xA0000000) +#define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024) + +/* undef to save memory */ +#define CFG_LONGHELP +/* Monitor Command Prompt */ +#define CFG_PROMPT "=> " +/* Buffer size for input from the Console */ +#define CFG_CBSIZE 256 +/* Buffer size for Console output */ +#define CFG_PBSIZE 256 +/* max args accepted for monitor commands */ +#define CFG_MAXARGS 16 +/* Buffer size for Boot Arguments passed to kernel */ +#define CFG_BARGSIZE 512 +/* List of legal baudrate settings for this board */ +#define CFG_BAUDRATE_TABLE { 38400 } + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE 1 +#define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */ +#define CONFIG_CONS_SCIF5 1 + +/* Suppress display of console information at boot */ +#undef CFG_CONSOLE_INFO_QUIET +#undef CFG_CONSOLE_OVERWRITE_ROUTINE +#undef CFG_CONSOLE_ENV_OVERWRITE + +#define CFG_MEMTEST_START (AP325RXA_SDRAM_BASE) +#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024)) + +/* Enable alternate, more extensive, memory test */ +#undef CFG_ALT_MEMTEST +/* Scratch address used by the alternate memory test */ +#undef CFG_MEMTEST_SCRATCH + +/* Enable temporary baudrate change while serial download */ +#undef CFG_LOADS_BAUD_CHANGE + +#define CFG_SDRAM_BASE (AP325RXA_SDRAM_BASE) +/* maybe more, but if so u-boot doesn't know about it... */ +#define CFG_SDRAM_SIZE (128 * 1024 * 1024) +/* default load address for scripts ?!? */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 16 * 1024 * 1024) + +/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ +#define CFG_MONITOR_BASE (AP325RXA_FLASH_BASE_1) +/* Monitor size */ +#define CFG_MONITOR_LEN (128 * 1024) +/* Size of DRAM reserved for malloc() use */ +#define CFG_MALLOC_LEN (256 * 1024) +/* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE (256) +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) + +/* FLASH */ +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#undef CFG_FLASH_QUIET_TEST +/* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_EMPTY_INFO +/* Physical start address of Flash memory */ +#define CFG_FLASH_BASE (AP325RXA_FLASH_BASE_1) +/* Max number of sectors on each Flash chip */ +#define CFG_MAX_FLASH_SECT 512 + +/* + * IDE support + */ +#define CONFIG_IDE_RESET 1 +#define CFG_PIO_MODE 1 +#define CFG_IDE_MAXBUS 1 /* IDE bus */ +#define CFG_IDE_MAXDEVICE 1 +#define CFG_ATA_BASE_ADDR 0xB4180000 +#define CFG_ATA_STRIDE 2 /* 1bit shift */ +#define CFG_ATA_DATA_OFFSET 0x200 /* data reg offset */ +#define CFG_ATA_REG_OFFSET 0x200 /* reg offset */ +#define CFG_ATA_ALT_OFFSET 0x210 /* alternate register offset */ + +/* if you use all NOR Flash , you change dip-switch. Please see Manual. */ +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)} + +/* Timeout for Flash erase operations (in ms) */ +#define CFG_FLASH_ERASE_TOUT (3 * 1000) +/* Timeout for Flash write operations (in ms) */ +#define CFG_FLASH_WRITE_TOUT (3 * 1000) +/* Timeout for Flash set sector lock bit operations (in ms) */ +#define CFG_FLASH_LOCK_TOUT (3 * 1000) +/* Timeout for Flash clear lock bit operations (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT (3 * 1000) + +/* + * Use hardware flash sectors protection instead + * of U-Boot software protection + */ +#undef CFG_FLASH_PROTECTION +#undef CFG_DIRECT_FLASH_TFTP + +/* ENV setting */ +#define CFG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE 1 +#define CFG_ENV_SECT_SIZE (128 * 1024) +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) +/* Offset of env Flash sector relative to CFG_FLASH_BASE */ +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE) + +/* Board Clock */ +#define CONFIG_SYS_CLK_FREQ 33333333 +#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ +#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) + +#endif /* __AP325RXA_H */ diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h new file mode 100644 index 0000000..23598f3 --- /dev/null +++ b/include/configs/rsk7203.h @@ -0,0 +1,107 @@ +/* + * Configuation settings for the Renesas Technology RSK 7203 + * + * Copyright (C) 2008 Nobuhiro Iwamatsu + * Copyright (C) 2008 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __RSK7203_H +#define __RSK7203_H + +#undef DEBUG +#define CONFIG_SH 1 +#define CONFIG_SH2 1 +#define CONFIG_SH2A 1 +#define CONFIG_CPU_SH7203 1 +#define CONFIG_RSK7203 1 + +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_ENV +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_CACHE + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS "console=ttySC0,115200" +#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */ + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +/* MEMORY */ +#define RSK7203_SDRAM_BASE 0x0C000000 +#define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */ +#define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024) + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Buffer size for input from the Console */ +#define CFG_PBSIZE 256 /* Buffer size for Console output */ +#define CFG_MAXARGS 16 /* max args accepted for monitor commands */ +/* Buffer size for Boot Arguments passed to kernel */ +#define CFG_BARGSIZE 512 +/* List of legal baudrate settings for this board */ +#define CFG_BAUDRATE_TABLE { 115200 } + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE 1 +#define CONFIG_CONS_SCIF0 1 + +#define CFG_MEMTEST_START RSK7203_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + (3 * 1024 * 1024)) + +#define CFG_SDRAM_BASE RSK7203_SDRAM_BASE +#define CFG_SDRAM_SIZE (32 * 1024 * 1024) + +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 1024 * 1024) +#define CFG_MONITOR_BASE RSK7203_FLASH_BASE_1 +#define CFG_MONITOR_LEN (128 * 1024) +#define CFG_MALLOC_LEN (256 * 1024) +#define CFG_GBL_DATA_SIZE 256 +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) + +/* FLASH */ +#define CONFIG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#undef CFG_FLASH_QUIET_TEST +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_BASE RSK7203_FLASH_BASE_1 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_MAX_FLASH_SECT 64 +#define CFG_MAX_FLASH_BANKS 1 + +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE (64 * 1024) +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_FLASH_ERASE_TOUT 12000 +#define CFG_FLASH_WRITE_TOUT 500 + +/* Board Clock */ +#define CONFIG_SYS_CLK_FREQ 33333333 +#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ +#define CFG_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) + +#endif /* __RSK7203_H */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 18675c2..74f6e3a 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -179,7 +179,7 @@ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) */ #define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ -#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */ /* * Now the NAND chip has to be defined (no autodetection used!) diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h new file mode 100644 index 0000000..efdb163 --- /dev/null +++ b/include/configs/sh7785lcr.h @@ -0,0 +1,167 @@ +/* + * Configuation settings for the Renesas Technology R0P7785LC0011RL board + * + * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SH7785LCR_H +#define __SH7785LCR_H + +#undef DEBUG +#define CONFIG_SH 1 +#define CONFIG_SH4A 1 +#define CONFIG_CPU_SH7785 1 +#define CONFIG_SH7785LCR 1 + +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_NFS +#define CONFIG_CMD_DFL +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_RUN +#define CONFIG_CMD_ENV + +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootdevice=0:1\0" \ + "usbload=usb reset;usbboot;usb stop;bootm\0" + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +/* MEMORY */ +#define SH7785LCR_SDRAM_BASE (0x08000000) +#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) +#define SH7785LCR_FLASH_BASE_1 (0xa0000000) +#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) +#define SH7785LCR_USB_BASE (0xb4000000) + +#define CFG_LONGHELP +#define CFG_PROMPT "=> " +#define CFG_CBSIZE 256 +#define CFG_PBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_BARGSIZE 512 +#define CFG_BAUDRATE_TABLE { 115200 } + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE 1 +#define CONFIG_CONS_SCIF1 1 +#define CONFIG_SCIF_EXT_CLOCK 1 +#undef CFG_CONSOLE_INFO_QUIET +#undef CFG_CONSOLE_OVERWRITE_ROUTINE +#undef CFG_CONSOLE_ENV_OVERWRITE + + +#define CFG_MEMTEST_START (SH7785LCR_SDRAM_BASE) +#define CFG_MEMTEST_END (CFG_MEMTEST_START + \ + (SH7785LCR_SDRAM_SIZE) - \ + 4 * 1024 * 1024) +#undef CFG_ALT_MEMTEST +#undef CFG_MEMTEST_SCRATCH +#undef CFG_LOADS_BAUD_CHANGE + +#define CFG_SDRAM_BASE (SH7785LCR_SDRAM_BASE) +#define CFG_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 16 * 1024 * 1024) + +#define CFG_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) +#define CFG_MONITOR_LEN (512 * 1024) +#define CFG_MALLOC_LEN (512 * 1024) +#define CFG_GBL_DATA_SIZE (256) +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) + +/* FLASH */ +#define CONFIG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#undef CFG_FLASH_QUIET_TEST +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_BASE (SH7785LCR_FLASH_BASE_1) +#define CFG_MAX_FLASH_SECT 512 + +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + \ + (0 * SH7785LCR_FLASH_BANK_SIZE) } + +#define CFG_FLASH_ERASE_TOUT (3 * 1000) +#define CFG_FLASH_WRITE_TOUT (3 * 1000) +#define CFG_FLASH_LOCK_TOUT (3 * 1000) +#define CFG_FLASH_UNLOCK_TOUT (3 * 1000) + +#undef CFG_FLASH_PROTECTION +#undef CFG_DIRECT_FLASH_TFTP + +/* R8A66597 */ +#define LITTLEENDIAN /* for include/usb.h */ +#define CONFIG_USB_R8A66597_HCD +#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE +#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ +#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ +#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ + +/* PCI Controller */ +#define CONFIG_PCI +#define CONFIG_SH4_PCI +#define CONFIG_SH7780_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW 1 + +#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ + +#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ + +/* Network device (RTL8169) support */ +#define CONFIG_NET_MULTI +#define CONFIG_RTL8169 + +/* ENV setting */ +#define CFG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE 1 +#define CFG_ENV_SECT_SIZE (256 * 1024) +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE) + +/* Board Clock */ +/* The SCIF used external clock. system clock only used timer. */ +#define CONFIG_SYS_CLK_FREQ 50000000 +#define TMU_CLK_DIVIDER 4 +#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) + +#endif /* __SH7785LCR_H */ diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h new file mode 100644 index 0000000..f0c146e --- /dev/null +++ b/include/configs/smdk6400.h @@ -0,0 +1,307 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * Gary Jennejohn <gj@denx.de> + * David Mueller <d.mueller@elsoft.ch> + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> + * + * Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_S3C6400 1 /* in a SAMSUNG S3C6400 SoC */ +#define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */ +#define CONFIG_SMDK6400 1 /* on a SAMSUNG SMDK6400 Board */ + +#define CFG_SDRAM_BASE 0x50000000 + +/* input clock of PLL: SMDK6400 has 12MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 12000000 + +#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000) +#define CONFIG_ENABLE_MMU +#endif + +#define CONFIG_MEMORY_UPPER_CODE + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG + +/* + * Architecture magic and machine type + */ +#define MACH_TYPE 1270 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#undef CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 1024 * 1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x18800300 +#define CS8900_BUS16 1 /* follow the Linux driver */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK6400 */ + +#define CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#define CONFIG_CMDLINE_EDITING + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +/*********************************************************** + * Command definition + ***********************************************************/ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_ENV +#define CONFIG_CMD_NAND +#if defined(CONFIG_BOOT_ONENAND) +#define CONFIG_CMD_ONENAND +#endif +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "SMDK6400 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE 384 /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START CFG_SDRAM_BASE /* memtest works on */ +#define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */ + +#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* default load address */ + +#define CFG_HZ 1000 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE 0x40000 /* regular stack 256KB */ + +/********************************** + Support Clock Settings + ********************************** + Setting SYNC ASYNC + ---------------------------------- + 667_133_66 X O + 533_133_66 O O + 400_133_66 X O + 400_100_50 O O + **********************************/ + +/*#define CONFIG_CLK_667_133_66*/ +#define CONFIG_CLK_533_133_66 +/* +#define CONFIG_CLK_400_100_50 +#define CONFIG_CLK_400_133_66 +#define CONFIG_SYNC_MODE +*/ + +/* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CFG_SDRAM_BASE /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB in Bank #1 */ + +#define CFG_FLASH_BASE 0x10000000 +#define CFG_MONITOR_BASE 0x00000000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +/* AM29LV160B has 35 sectors, AM29LV800B - 19 */ +#define CFG_MAX_FLASH_SECT 40 + +#define CONFIG_AMD_LV800 +#define CFG_FLASH_CFI 1 /* Use CFI parameters (needed?) */ +/* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant */ +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_FLASH_CFI_LEGACY +#define CFG_FLASH_LEGACY_512Kx16 + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (5 * CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (5 * CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* + * SMDK6400 board specific data + */ + +#define CONFIG_IDENT_STRING " for SMDK6400" + +/* base address for uboot */ +#define CFG_PHY_UBOOT_BASE (CFG_SDRAM_BASE + 0x07e00000) +/* total memory available to uboot */ +#define CFG_UBOOT_SIZE (1024 * 1024) + +#ifdef CONFIG_ENABLE_MMU +#define CFG_MAPPED_RAM_BASE 0xc0000000 +#define CONFIG_BOOTCOMMAND "nand read 0xc0018000 0x60000 0x1c0000;" \ + "bootm 0xc0018000" +#else +#define CFG_MAPPED_RAM_BASE CFG_SDRAM_BASE +#define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \ + "bootm 0x50018000" +#endif + +/* NAND U-Boot load and start address */ +#define CFG_UBOOT_BASE (CFG_MAPPED_RAM_BASE + 0x07e00000) + +#define CFG_ENV_OFFSET 0x0040000 + +/* NAND configuration */ +#define CFG_MAX_NAND_DEVICE 1 +#define CFG_NAND_BASE 0x70200010 +#define NAND_MAX_CHIPS 1 +#define CFG_S3C_NAND_HWECC + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_WP 1 +#define CFG_NAND_YAFFS_WRITE 1 /* support yaffs write */ +#define CFG_NAND_BBT_2NDPAGE 1 /* bad-block markers in 1st and 2nd pages */ + +#define CFG_NAND_U_BOOT_DST CFG_PHY_UBOOT_BASE /* NUB load-addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* NUB start-addr */ + +#define CFG_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */ + +/* NAND chip page size */ +#define CFG_NAND_PAGE_SIZE 2048 +/* NAND chip block size */ +#define CFG_NAND_BLOCK_SIZE (128 * 1024) +/* NAND chip page per block count */ +#define CFG_NAND_PAGE_COUNT 64 +/* Location of the bad-block label */ +#define CFG_NAND_BAD_BLOCK_POS 0 +/* Extra address cycle for > 128MiB */ +#define CFG_NAND_5_ADDR_CYCLE + +/* Size of the block protected by one OOB (Spare Area in Samsung terminology) */ +#define CFG_NAND_ECCSIZE CFG_NAND_PAGE_SIZE +/* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */ +#define CFG_NAND_ECCBYTES 4 +/* Number of ECC-blocks per NAND page */ +#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE) +/* Size of a single OOB region */ +#define CFG_NAND_OOBSIZE 64 +/* Number of ECC bytes per page */ +#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) +/* ECC byte positions */ +#define CFG_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63} + +/* Boot configuration (define only one of next 3) */ +#define CONFIG_BOOT_NAND +/* None of these are currently implemented. Left from the original Samsung + * version for reference +#define CONFIG_BOOT_NOR +#define CONFIG_BOOT_MOVINAND +#define CONFIG_BOOT_ONENAND +*/ + +#define CONFIG_NAND +#define CONFIG_NAND_S3C64XX +/* Unimplemented or unsupported. See comment above. +#define CONFIG_ONENAND +#define CONFIG_MOVINAND +*/ + +/* Settings as above boot configuration */ +#define CFG_ENV_IS_IN_NAND +#define CONFIG_BOOTARGS "console=ttySAC,115200" + +#if !defined(CONFIG_ENABLE_MMU) +#define CONFIG_CMD_USB 1 +#define CONFIG_USB_OHCI_NEW 1 +#define CFG_USB_OHCI_REGS_BASE 0x74300000 +#define CFG_USB_OHCI_SLOT_NAME "s3c6400" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 3 +#define CFG_USB_OHCI_CPU_INIT 1 +#define LITTLEENDIAN 1 /* used by usb_ohci.c */ + +#define CONFIG_USB_STORAGE 1 +#endif +#define CONFIG_DOS_PARTITION 1 + +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_ENABLE_MMU) +# error "usb_ohci.c is currently broken with MMU enabled." +#endif + +#endif /* __CONFIG_H */ |