diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/PPChameleonEVB.h | 9 | ||||
| -rw-r--r-- | include/configs/Total5200.h | 1 | ||||
| -rw-r--r-- | include/configs/lwmon.h | 18 | ||||
| -rw-r--r-- | include/configs/mx1ads.h | 89 | ||||
| -rw-r--r-- | include/configs/mx1fs2.h | 291 | ||||
| -rw-r--r-- | include/configs/scb9328.h | 357 |
6 files changed, 706 insertions, 59 deletions
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index bb8ce43..b1f41a1 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -43,6 +43,9 @@ * CONFIG_PPCHAMELEON_CLK_25 * CONFIG_PPCHAMELEON_CLK_33 */ +#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33)) +#define CONFIG_PPCHAMELEON_CLK_33 +#endif #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) #error "* Two external frequencies (SysClk) are defined! *" @@ -74,11 +77,11 @@ #ifdef CONFIG_PPCHAMELEON_CLK_25 - #define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ +# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ #elif (defined (CONFIG_PPCHAMELEON_CLK_33)) -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ +# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ #else -#error "* External frequency (SysClk) not defined! *" +# error "* External frequency (SysClk) not defined! *" #endif #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 830bf81..47f24be 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -64,6 +64,7 @@ * Video console */ #if 1 +#define CONFIG_VIDEO #define CONFIG_VIDEO_SED13806 #define CONFIG_VIDEO_SED13806_16BPP diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h index d944ed8..a76ec23 100644 --- a/include/configs/lwmon.h +++ b/include/configs/lwmon.h @@ -47,11 +47,9 @@ #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#if 1 +#define CONFIG_SERIAL_MULTI 1 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#else -#define CONFIG_8xx_CONS_SCC2 -#endif +#define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */ #define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */ @@ -151,17 +149,6 @@ #define CFG_CMD_POST_DIAG 0 #endif -#ifdef CONFIG_8xx_CONS_SCC2 /* Can't use ethernet, then */ -#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_IDE | \ - CFG_CMD_BSP | \ - CFG_CMD_BMP | \ - CFG_CMD_POST_DIAG ) -#else #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ CFG_CMD_DHCP | \ @@ -172,7 +159,6 @@ CFG_CMD_BSP | \ CFG_CMD_BMP | \ CFG_CMD_POST_DIAG ) -#endif #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h index 5cf092a..df951e2 100644 --- a/include/configs/mx1ads.h +++ b/include/configs/mx1ads.h @@ -16,7 +16,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -25,7 +25,6 @@ * MA 02111-1307 USA */ - #ifndef __CONFIG_H #define __CONFIG_H @@ -40,14 +39,19 @@ * (easy to change) */ #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_MC9328 1 /* It's a Motorola MC9328 SoC */ -#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */ - -#define BOARD_LATE_INIT 1 +#define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */ +#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* + * Select serial console configuration + */ +#define CONFIG_IMX_SERIAL1 /* internal uart 1 */ +/* #define _CONFIG_UART2 */ /* internal uart 2 */ +/* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */ +#define BOARD_LATE_INIT 1 #define USE_920T_MMU 1 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #if 0 #define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ @@ -60,6 +64,8 @@ */ #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) + + #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ /* @@ -67,13 +73,13 @@ */ #define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ #define CS8900_BASE 0x15000300 -#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ +#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ /* * select serial console configuration */ -#define CONFIG_UART1 1 +/* #define CONFIG_UART1 */ /* #define CONFIG_UART2 1 */ #define CONFIG_BAUDRATE 115200 @@ -85,24 +91,20 @@ #define CONFIG_COMMANDS \ (CONFIG_CMD_DFL | \ CFG_CMD_CACHE | \ - /*CFG_CMD_NAND |*/ \ - /*CFG_CMD_EEPROM |*/ \ - /*CFG_CMD_I2C |*/ \ - /*CFG_CMD_USB |*/ \ - CFG_CMD_REGINFO | \ + CFG_CMD_REGINFO | \ CFG_CMD_ELF) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=/dev/docbp mem=48M" +#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M" #define CONFIG_ETHADDR 08:00:3e:26:0a:5c -#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 192.168.0.22 #define CONFIG_SERVERIP 192.168.0.11 #define CONFIG_BOOTFILE "mx1ads" -/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ +#define CONFIG_BOOTCOMMAND "tftp; bootm" #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ @@ -114,10 +116,10 @@ * Miscellaneous configurable options */ -#define CFG_HUSH_PARSER 1 +#define CFG_HUSH_PARSER 1 #define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT "MX1ADS$ " /* Monitor Command Prompt */ @@ -125,21 +127,20 @@ #define CFG_PROMPT "MX1ADS=> " /* Monitor Command Prompt */ #endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_MEMTEST_START 0x09000000 /* memtest works on */ #define CFG_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */ -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x08800000 /* default load address */ - - -#define CFG_HZ 1000 +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CFG_LOAD_ADDR 0x08800000 /* default load address */ +/*#define CFG_HZ 1000 */ +#define CFG_HZ 3686400 +#define CFG_CPUSPEED 0x141 /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } @@ -159,27 +160,35 @@ * Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ +#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ -#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define CFG_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */ -#define CFG_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */ -#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ - +#define CFG_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */ +#define CFG_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */ +#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ /*----------------------------------------------------------------------- * FLASH and environment organization */ - #define CONFIG_SYNCFLASH 1 #define PHYS_FLASH_SIZE 0x01000000 #define CFG_MAX_FLASH_SECT (16) -#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x00ff0000) +#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x00ff8000) -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x0f000 /* Total Size of Environment Sector */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x100000 + +/*----------------------------------------------------------------------- + * Enable passing ATAGS + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 + +#define CONFIG_SYS_CLK_FREQ 16780000 +#define CONFIG_SYSPLL_CLK_FREQ 16000000 + #endif /* __CONFIG_H */ diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h new file mode 100644 index 0000000..61a3b29 --- /dev/null +++ b/include/configs/mx1fs2.h @@ -0,0 +1,291 @@ +/* + * Copyright (C) 2004 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */ +#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */ +#define CONFIG_MX1FS2 1 /* on a mx1fs2 board */ +#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ + +/* + * Select serial console configuration + */ +#undef _CONFIG_UART1 /* internal uart 1 */ +#define _CONFIG_UART2 /* internal uart 2 */ +#undef _CONFIG_UART3 /* internal uart 3 */ +#undef _CONFIG_UART4 /* internal uart 4 */ +#undef CONFIG_SILENT_CONSOLE /* use this to disable output */ + +/* + * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if + * neccessary in include/cmd_confdefs.h file. (Un)comment for getting + * functionality or size of u-boot code. + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + & ~CFG_CMD_LOADS \ + & ~CFG_CMD_CONSOLE \ + & ~CFG_CMD_AUTOSCRIPT \ + & ~CFG_CMD_NET \ + & ~CFG_CMD_PING \ + & ~CFG_CMD_DHCP \ + | CFG_CMD_JFFS2 \ + ) + +#include <cmd_confdefs.h> + +/* + * Boot options. Setting delay to -1 stops autostart count down. + */ +#define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTARGS "root=/dev/mtdblock4 console=ttySMX0,115200n8 rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND "bootm 10080000" +#define CONFIG_SHOW_BOOT_PROGRESS + +/* + * General options for u-boot. Modify to save memory foot print + */ +#define CFG_LONGHELP /* undef saves memory */ +#define CFG_PROMPT "mx1fs2> " /* prompt string */ +#define CFG_CBSIZE 256 /* console I/O buffer */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ +#define CFG_MAXARGS 16 /* max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ + +#define CFG_MEMTEST_START 0x08100000 /* memtest test area */ +#define CFG_MEMTEST_END 0x08F00000 + +#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x141 /* core clock - register value */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_BAUDRATE 115200 +/* + * Definitions related to passing arguments to kernel. + */ +#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ +#define CONFIG_INITRD_TAG 1 /* send initrd params */ +#undef CONFIG_VFD /* do not send framebuffer setup */ + +#define CFG_JFFS_CUSTOM_PART +/* + * Malloc pool need to host env + 128 Kb reserve for other allocations. + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) ) + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_STACKSIZE (120<<10) /* stack size */ + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ +#endif + +/* SDRAM Setup Values + * 0x910a8300 Precharge Command CAS 3 + * 0x910a8200 Precharge Command CAS 2 + * + * 0xa10a8300 AutoRefresh Command CAS 3 + * 0xa10a8200 Set AutoRefresh Command CAS 2 + */ +#define PRECHARGE_CMD 0x910a8300 +#define AUTOREFRESH_CMD 0xa10a8300 + +#define CONFIG_INIT_CRITICAL + +#define BUS32BIT_VERSION +/* + * SDRAM Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ +#define MX1FS2_SDRAM_1 0x08000000 /* SDRAM bank #1 */ +#ifdef BUS32BIT_VERSION +#define MX1FS2_SDRAM_1_SIZE (0x04000000 - 0x100000) /* 64 MB - 1M Framebuffer */ +#else +#define MX1FS2_SDRAM_1_SIZE (0x01FC0000 - 0x100000) /* 32 MB - 1M Framebuffer */ +#endif +/* + * Flash Controller settings + */ + +#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ +#define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ + +#ifdef BUS32BIT_VERSION +#define MX1FS2_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ +#define MX1FS2_FLASH_INTERLEAVE 2 /* ... made of 2 chips */ +#define MX1FS2_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank*/ +#define MX1FS2_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ +#define MX1FS2_JFFS2_PART0_START 0x10200000 +#define MX1FS2_JFFS2_PART0_SIZE 0x00500000 +#define MX1FS2_JFFS2_PART1_START 0x10700000 +#define MX1FS2_JFFS2_PART1_SIZE 0x00900000 +#else +#define MX1FS2_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ +#define MX1FS2_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ +#define MX1FS2_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank*/ +#define MX1FS2_FLASH_SECT_SIZE 0x00010000 /* size of erase sector */ +#endif +#define MX1FS2_FLASH_BASE 0x10000000 /* location of flash memory */ +#define MX1FS2_FLASH_UNLOCK 1 /* perform hw unlock first */ + +/* This should be defined if CFI FLASH device is present. Actually benefit + is not so clear to me. In other words we can provide more informations + to user, but this expects more complex flash handling we do not provide + now.*/ +#undef CFG_FLASH_CFI + +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ + +#define CFG_FLASH_BASE MX1FS2_FLASH_BASE + +/* + * This is setting for JFFS2 support in u-boot. + * Right now there is no gain for user, but later on booting kernel might be + * possible. Consider using XIP kernel running from flash to save RAM + * footprint. + * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. + */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_FIRST_SECTOR 5 +#define CFG_JFFS2_NUM_BANKS 1 + +/* + * Environment setup. Definitions of monitor location and size with + * definition of environment setup ends up in 2 possibilities. + * 1. Embeded environment - in u-boot code is space for environment + * 2. Environment is read from predefined sector of flash + * Right now we support 2. possiblity, but expecting no env placed + * on mentioned address right now. This also needs to provide whole + * sector for it - for us 256Kb is really waste of memory. U-boot uses + * default env. and until kernel parameters could be sent to kernel + * env. has no sense to us. + */ + +#define CFG_MONITOR_BASE 0x10000000 +#define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x10020000 /* absolute address for now */ +#define CFG_ENV_SIZE 0x20000 + +#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ + +/* Setup CS4 and CS5 */ +#define CFG_GIUS_A_VAL 0x0003fffe + +/* + * CSxU_VAL: + * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 + * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | + * + * CSxL_VAL: + * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 + * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| + */ + +#define CFG_CS0U_VAL 0x00008C00 +#define CFG_CS0L_VAL 0x22222601 +#define CFG_CS1U_VAL 0x00008C00 +#define CFG_CS1L_VAL 0x22222301 +#define CFG_CS4U_VAL 0x00008C00 +#define CFG_CS4L_VAL 0x22222301 +#define CFG_CS5U_VAL 0x00008C00 +#define CFG_CS5L_VAL 0x22222301 + +/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) + f_ref=16,777MHz + + 0x002a141f: 191,9944MHz + 0x040b2007: 144MHz + 0x042a141f: 96MHz + 0x0811140d: 64MHz + 0x040e200e: 150MHz + 0x00321431: 200MHz + + 0x08001800: 64MHz mit 16er Quarz + 0x04001800: 96MHz mit 16er Quarz + 0x04002400: 144MHz mit 16er Quarz + + 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 + |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ + +#define CFG_MPCTL0_VAL 0x07E723AD +#define CFG_MPCTL1_VAL 0x00000040 +#define CFG_PCDR_VAL 0x00010005 +#define CFG_GPCR_VAL 0x00000FFB + +#define USE_16M_OSZI /* If you have one, you want to use it + The internal 32kHz oszillator jitters */ +#ifdef USE_16M_OSZI + +#define CFG_SPCTL0_VAL 0x04001401 +#define CFG_SPCTL1_VAL 0x0C000040 +#define CFG_CSCR_VAL 0x07030003 +#define CONFIG_SYS_CLK_FREQ 16780000 +#define CONFIG_SYSPLL_CLK_FREQ 16000000 + +#else + +#define CFG_SPCTL0_VAL 0x07E716D1 +#define CFG_CSCR_VAL 0x06000003 +#define CONFIG_SYS_CLK_FREQ 16780000 +#define CONFIG_SYSPLL_CLK_FREQ 16780000 + +#endif + +/* + * Well this has to be defined, but on the other hand it is used differently + * one may expect. For instance loadb command do not cares :-) + * So advice is - do not relay on this... + */ +#define CFG_LOAD_ADDR 0x08400000 + +#define CFG_FMCR_VAL 0x00000003 /* Reset Default */ + +/* Bit[0:3] contain PERCLK1DIV for UART 1 + 0x000b00b ->b<- -> 192MHz/12=16MHz + 0x000b00b ->8<- -> 144MHz/09=16MHz + 0x000b00b ->3<- -> 64MHz/4=16MHz */ + +#ifdef _CONFIG_UART1 +#define CONFIG_IMX_SERIAL1 +#elif defined _CONFIG_UART2 +#define CONFIG_IMX_SERIAL2 +#elif defined _CONFIG_UART3 | defined _CONFIG_UART4 +#define CONFIG_IMX_SERIAL_NONE +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_CLK 3686400 +#define CFG_NS16550_REG_SIZE 1 +#define CONFIG_CONS_INDEX 1 +#ifdef _CONFIG_UART3 +#define CFG_NS16550_COM1 0x15000000 +#elif defined _CONFIG_UART4 +#define CFG_NS16550_COM1 0x16000000 +#endif +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h new file mode 100644 index 0000000..6cd9126 --- /dev/null +++ b/include/configs/scb9328.h @@ -0,0 +1,357 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli <peposh@etc.sk>, 2003. + * + * 2003/13/06 Initial MP10 Support copied from wepep250 + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */ +#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */ +#define CONFIG_SCB9328 1 /* on a scb9328tronix board */ +#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ + +#define CONFIG_IMX_SERIAL1 +/* + * Select serial console configuration + */ + + +/* + * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if + * neccessary in include/cmd_confdefs.h file. (Un)comment for getting + * functionality or size of u-boot code. + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + & ~CFG_CMD_LOADS \ + & ~CFG_CMD_CONSOLE \ + & ~CFG_CMD_AUTOSCRIPT \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + | CFG_CMD_DHCP \ + ) + +#include <cmd_confdefs.h> + +/* + * Boot options. Setting delay to -1 stops autostart count down. + * NOTE: Sending parameters to kernel depends on kernel version and + * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept + * parameters at all! Do not get confused by them so. + */ +#define CONFIG_BOOTDELAY -1 +#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328" +#define CONFIG_BOOTCOMMAND "bootm 10040000" +#define CONFIG_SHOW_BOOT_PROGRESS +#define CONFIG_ETHADDR 80:81:82:83:84:85 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.10.10.9 +#define CONFIG_SERVERIP 10.10.10.10 + +/* + * General options for u-boot. Modify to save memory foot print + */ +#define CFG_LONGHELP /* undef saves memory */ +#define CFG_PROMPT "scb9328> " /* prompt string */ +#define CFG_CBSIZE 256 /* console I/O buffer */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ +#define CFG_MAXARGS 16 /* max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ + +#define CFG_MEMTEST_START 0x08100000 /* memtest test area */ +#define CFG_MEMTEST_END 0x08F00000 + +#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x141 /* core clock - register value */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_BAUDRATE 115200 +/* + * Definitions related to passing arguments to kernel. + */ +#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ +#define CONFIG_INITRD_TAG 1 /* send initrd params */ +#undef CONFIG_VFD /* do not send framebuffer setup */ + + +/* + * Malloc pool need to host env + 128 Kb reserve for other allocations. + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) ) + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_STACKSIZE (120<<10) /* stack size */ + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ +#endif + +/* SDRAM Setup Values +0x910a8300 Precharge Command CAS 3 +0x910a8200 Precharge Command CAS 2 + +0xa10a8300 AutoRefresh Command CAS 3 +0xa10a8200 Set AutoRefresh Command CAS 2 */ + +#define PRECHARGE_CMD 0x910a8200 +#define AUTOREFRESH_CMD 0xa10a8200 +#define CONFIG_INIT_CRITICAL + +/* + * SDRAM Memory Map + */ +/* SH FIXME */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ +#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */ +#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */ + +/* + * Flash Controller settings + */ + +/* + * Hardware drivers + */ + + +/* + * Configuration for FLASH memory for the Synertronixx board + */ + +/* #define SCB9328_FLASH_32M */ + +/* 32MB */ +#ifdef SCB9328_FLASH_32M +#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ +#define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ +#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ +#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ +#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */ +#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ +#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ +#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ +#else + +/* 16MB */ +#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ +#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ +#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ +#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ +#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */ +#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ +#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ +#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ +#endif /* SCB9328_FLASH_32M */ + +/* This should be defined if CFI FLASH device is present. Actually benefit + is not so clear to me. In other words we can provide more informations + to user, but this expects more complex flash handling we do not provide + now.*/ +#undef CFG_FLASH_CFI + +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ + +#define CFG_FLASH_BASE SCB9328_FLASH_BASE + +/* + * This is setting for JFFS2 support in u-boot. + * Right now there is no gain for user, but later on booting kernel might be + * possible. Consider using XIP kernel running from flash to save RAM + * footprint. + * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. + */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_FIRST_SECTOR 5 +#define CFG_JFFS2_NUM_BANKS 1 + +/* + * Environment setup. Definitions of monitor location and size with + * definition of environment setup ends up in 2 possibilities. + * 1. Embeded environment - in u-boot code is space for environment + * 2. Environment is read from predefined sector of flash + * Right now we support 2. possiblity, but expecting no env placed + * on mentioned address right now. This also needs to provide whole + * sector for it - for us 256Kb is really waste of memory. U-boot uses + * default env. and until kernel parameters could be sent to kernel + * env. has no sense to us. + */ + +/* Setup for PA23 which is Reset Default PA23 but has to become + CS5 */ + +#define CFG_GPR_A_VAL 0x00800000 +#define CFG_GIUS_A_VAL 0x0043fffe + +#define CFG_MONITOR_BASE 0x10000000 +#define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x10020000 /* absolute address for now */ +#define CFG_ENV_SIZE 0x20000 + +#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ + +/* + * CSxU_VAL: + * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 + * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | + * + * CSxL_VAL: + * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 + * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| + */ + +#define CFG_CS0U_VAL 0x000F2000 +#define CFG_CS0L_VAL 0x11110d01 +#define CFG_CS1U_VAL 0x000F0a00 +#define CFG_CS1L_VAL 0x11110601 +#define CFG_CS2U_VAL 0x0 +#define CFG_CS2L_VAL 0x0 + +#define CFG_CS3U_VAL 0x000FFFFF +#define CFG_CS3L_VAL 0x00000303 + +#define CFG_CS4U_VAL 0x000F0a00 +#define CFG_CS4L_VAL 0x11110301 + +/* CNC == 3 too long + #define CFG_CS5U_VAL 0x0000C210 */ + +/* #define CFG_CS5U_VAL 0x00008400 + mal laenger mahcen, ob der bei 150MHz laenger haelt dann und + kaum langsamer ist */ +/* #define CFG_CS5U_VAL 0x00009400 + #define CFG_CS5L_VAL 0x11010D03 */ + +#define CFG_CS5U_VAL 0x00008400 +#define CFG_CS5L_VAL 0x00000D03 + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x16000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+4) +/* #define CONFIG_DM9000_USE_8BIT */ +#define CONFIG_DM9000_USE_16BIT +/* #define CONFIG_DM9000_USE_32BIT */ + +/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) + f_ref=16,777MHz + + 0x002a141f: 191,9944MHz + 0x040b2007: 144MHz + 0x042a141f: 96MHz + 0x0811140d: 64MHz + 0x040e200e: 150MHz + 0x00321431: 200MHz + + 0x08001800: 64MHz mit 16er Quarz + 0x04001800: 96MHz mit 16er Quarz + 0x04002400: 144MHz mit 16er Quarz + + 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 + |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ + +#define CPU200 + +#ifdef CPU200 +#define CFG_MPCTL0_VAL 0x00321431 +#else +#define CFG_MPCTL0_VAL 0x040e200e +#endif + +/* #define BUS64 */ +#define BUS72 + +#ifdef BUS72 +#define CFG_SPCTL0_VAL 0x04002400 +#endif + +#ifdef BUS96 +#define CFG_SPCTL0_VAL 0x04001800 +#endif + +#ifdef BUS64 +#define CFG_SPCTL0_VAL 0x08001800 +#endif + +/* Das ist der BCLK Divider, der aus der System PLL + BCLK und HCLK erzeugt: + 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0 + 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2 + 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2 + 0x2f001003 : 192MHz/5=38,4MHz + 0x2f000003 : 64MHz/1 + Bit 22: SPLL Restart + Bit 21: MPLL Restart */ + +#ifdef BUS64 +#define CFG_CSCR_VAL 0x2f030003 +#endif + +#ifdef BUS72 +#define CFG_CSCR_VAL 0x2f030403 +#endif + +/* + * Well this has to be defined, but on the other hand it is used differently + * one may expect. For instance loadb command do not cares :-) + * So advice is - do not relay on this... + */ +#define CFG_LOAD_ADDR 0x08400000 + +#define MHZ16QUARZINUSE + +#ifdef MHZ16QUARZINUSE +#define CONFIG_SYSPLL_CLK_FREQ 16000000 +#else +#define CONFIG_SYSPLL_CLK_FREQ 16780000 +#endif + +#define CONFIG_SYS_CLK_FREQ 16780000 + +/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */ +#define CFG_FMCR_VAL 0x00000001 + +/* Bit[0:3] contain PERCLK1DIV for UART 1 + 0x000b00b ->b<- -> 192MHz/12=16MHz + 0x000b00b ->8<- -> 144MHz/09=16MHz + 0x000b00b ->3<- -> 64MHz/4=16MHz */ + +#ifdef BUS96 +#define CFG_PCDR_VAL 0x000b00b5 +#endif + +#ifdef BUS64 +#define CFG_PCDR_VAL 0x000b00b3 +#endif + +#ifdef BUS72 +#define CFG_PCDR_VAL 0x000b00b8 +#endif + +#endif /* __CONFIG_H */ |