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-rw-r--r--include/configs/katmai.h415
-rw-r--r--include/configs/mcc200.h1
-rw-r--r--include/configs/mecp5200.h58
-rw-r--r--include/configs/motionpro.h305
-rw-r--r--include/configs/sc3.h2
-rw-r--r--include/configs/sequoia.h4
6 files changed, 753 insertions, 32 deletions
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
new file mode 100644
index 0000000..c750e14
--- /dev/null
+++ b/include/configs/katmai.h
@@ -0,0 +1,415 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * katmai.h - configuration for AMCC Katmai (440SPe)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_KATMAI 1 /* Board is Katmai */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_440 1 /* ... PPC440 family */
+#define CONFIG_440SPE 1 /* Specifc SPe support */
+#undef CFG_DRAM_TEST /* Disable-takes long time */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
+#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
+
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xff000000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
+#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
+
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
+
+#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
+#define CFG_PCIE_MEMSIZE 0x01000000
+#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
+
+#define CFG_PCIE0_CFGBASE 0xc0000000
+#define CFG_PCIE0_XCFGBASE 0xc0000400
+#define CFG_PCIE1_CFGBASE 0xc0001000
+#define CFG_PCIE1_XCFGBASE 0xc0001400
+#define CFG_PCIE2_CFGBASE 0xc0002000
+#define CFG_PCIE2_XCFGBASE 0xc0002400
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
+
+#define CFG_ACE_BASE 0xe0000000 /* Xilinx ACE controller - Compact Flash */
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM 1
+#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_SERIAL_MULTI 1
+#undef CONFIG_UART1_CONSOLE
+#undef CFG_EXT_SERIAL_CLOCK
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
+#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses */
+#define IIC0_DIMM0_ADDR 0x51
+#define IIC0_DIMM1_ADDR 0x52
+#undef CONFIG_STRESS
+#undef ENABLE_ECC
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_SPD_BUS_NUM 0 /* The I2C bus for SPD */
+
+#define IIC0_BOOTPROM_ADDR 0x50
+#define IIC0_ALT_BOOTPROM_ADDR 0x54
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR (0x50)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11 1
+#define CFG_RTC_BUS_NUM 1 /* The I2C bus for RTC */
+#define CFG_I2C_RTC_ADDR 0x68
+#define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */
+
+/* I2C DTT */
+#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
+#define CFG_DTT_BUS_NUM 1 /* The I2C bus for DTT */
+/*
+ * standard dtt sensor configuration - bottom bit will determine local or
+ * remote sensor of the ADM1021, the rest determines index into
+ * CFG_DTT_ADM1021 array below.
+ */
+#define CONFIG_DTT_SENSORS { 0, 1 }
+
+/*
+ * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
+ * there will be one entry in this array for each two (dummy) sensors in
+ * CONFIG_DTT_SENSORS.
+ *
+ * For Katmai board:
+ * - only one ADM1021
+ * - i2c addr 0x18
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT ouput disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
+ * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
+ */
+#define CFG_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=katmai\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=katmai/uImage\0" \
+ "kernel_addr=fff10000\0" \
+ "ramdisk_addr=fff20000\0" \
+ "initrd_high=30000000\0" \
+ "load=tftp 200000 katmai/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b ${fileaddr} fffc0000 ${filesize};" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ "kozio=bootm ffc60000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_DTT | \
+ CFG_CMD_ELF | \
+ CFG_CMD_EXT2 | \
+ CFG_CMD_FAT | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
+#define CONFIG_HAS_ETH0
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_RESET_DELAY 1000
+#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* needed for NetConsole */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */
+#define CFG_PCI_TARGET_INIT /* let board init pci target */
+#undef CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+/* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */
+
+/*
+ * NETWORK Support (PCI):
+ */
+/* Support for Intel 82557/82559/82559ER chips. */
+#define CONFIG_EEPRO100
+
+/*-----------------------------------------------------------------------
+ * Xilinx System ACE support
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */
+#define CFG_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
+#define CFG_SYSTEMACE_BASE CFG_ACE_BASE
+#define CONFIG_DOS_PARTITION 1
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+
+/* Memory Bank 0 (Flash) initialization */
+#define CFG_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(7) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(0) | \
+ EBC_BXAP_WBN_ENCODE(0) | \
+ EBC_BXAP_WBF_ENCODE(0) | \
+ EBC_BXAP_TH_ENCODE(0) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_DELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CFG_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | \
+ EBC_BXCR_BS_16MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 1 (Xilinx System ACE controller) initialization */
+#define CFG_EBC_PB1AP 0x7F8FFE80
+#define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/*-------------------------------------------------------------------------
+ * Initialize EBC CONFIG -
+ * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
+ * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
+ *-------------------------------------------------------------------------*/
+#define CFG_EBC_CFG (EBC_CFG_LE_UNLOCK | \
+ EBC_CFG_PTD_ENABLE | \
+ EBC_CFG_RTC_16PERCLK | \
+ EBC_CFG_ATC_PREVIOUS | \
+ EBC_CFG_DTC_PREVIOUS | \
+ EBC_CFG_CTC_PREVIOUS | \
+ EBC_CFG_OEO_PREVIOUS | \
+ EBC_CFG_EMC_DEFAULT | \
+ EBC_CFG_PME_DISABLE | \
+ EBC_CFG_PR_16)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index f60973b..621a81c 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -265,6 +265,7 @@
*/
#if !defined(CONFIG_PRS200)
#define CONFIG_LCD 1
+#define CONFIG_PROGRESSBAR 1
#endif
#if defined(CONFIG_LCD)
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
index ccb0293..0c10294 100644
--- a/include/configs/mecp5200.h
+++ b/include/configs/mecp5200.h
@@ -88,10 +88,10 @@
/* USB */
#if 0
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
#else
-#define ADD_USB_CMD 0
+#define ADD_USB_CMD 0
#endif
/*
@@ -100,7 +100,7 @@
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_EEPROM | \
CFG_CMD_FAT | \
- CFG_CMD_EXT2 | \
+ CFG_CMD_EXT2 | \
CFG_CMD_I2C | \
CFG_CMD_IDE | \
CFG_CMD_BSP | \
@@ -110,11 +110,11 @@
#include <cmd_confdefs.h>
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
-# define CFG_LOWBOOT 1
+# define CFG_LOWBOOT 1
# define CFG_LOWBOOT16 1
#endif
#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
-# define CFG_LOWBOOT 1
+# define CFG_LOWBOOT 1
# define CFG_LOWBOOT08 1
#endif
@@ -131,20 +131,20 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
- "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
- "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
- "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
- "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
- "loadaddr=01000000\0" \
- "serverip=192.168.2.99\0" \
- "gatewayip=10.0.0.79\0" \
- "user=mu\0" \
- "target=mecp5200.esd\0" \
- "script=mecp5200.bat\0" \
- "image=/tftpboot/vxWorks_mecp5200\0" \
- "ipaddr=10.0.13.196\0" \
- "netmask=255.255.0.0\0" \
+ "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
+ "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
+ "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
+ "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
+ "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
+ "loadaddr=01000000\0" \
+ "serverip=192.168.2.99\0" \
+ "gatewayip=10.0.0.79\0" \
+ "user=mu\0" \
+ "target=mecp5200.esd\0" \
+ "script=mecp5200.bat\0" \
+ "image=/tftpboot/vxWorks_mecp5200\0" \
+ "ipaddr=10.0.13.196\0" \
+ "netmask=255.255.0.0\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
@@ -171,12 +171,12 @@
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_EEPROM_PAGE_WRITE_BITS 5
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CFG_I2C_MULTI_EEPROMS 1
+#define CFG_I2C_MULTI_EEPROMS 1
/*
* Flash configuration
*/
#define CFG_FLASH_BASE 0xFFC00000
-#define CFG_FLASH_SIZE 0x00400000
+#define CFG_FLASH_SIZE 0x00400000
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x003E0000)
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CFG_MAX_FLASH_SECT 512
@@ -200,15 +200,15 @@
#define CONFIG_ENV_OVERWRITE 1
#endif
-#define CFG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
+#define CFG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
#if 0
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#endif
-#define CFG_FLASH_INCREMENT 0x00400000 /* size of flash bank */
+#define CFG_FLASH_INCREMENT 0x00400000 /* size of flash bank */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
-#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */
+#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */
/*
@@ -272,7 +272,7 @@
#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
@@ -339,7 +339,7 @@
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET (0x005C)
-/* Interval between registers */
-#define CFG_ATA_STRIDE 4
+/* Interval between registers */
+#define CFG_ATA_STRIDE 4
#endif /* __CONFIG_H */
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
new file mode 100644
index 0000000..5328e8d
--- /dev/null
+++ b/include/configs/motionpro.h
@@ -0,0 +1,305 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Based on PRO Motion board config file by Andy Joseph, andy@promessdev.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+/*
+ * High Level Configuration Options
+ */
+
+
+/* CPU and board */
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
+#define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */
+
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_IMMAP | \
+ CFG_CMD_ELF | \
+ CFG_CMD_MII | \
+ CFG_CMD_BEDBUG | \
+ CFG_CMD_NET | \
+ CFG_CMD_PING)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#define CONFIG_NETCONSOLE 1 /* network console */
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_PHY_ADDR 0x2
+#define CONFIG_PHY_TYPE 0x79c874
+
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR "\x1b\x1b"
+#define DEBUG_BOOTKEYS 0
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#undef CONFIG_BOOTARGS
+#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
+ "press \"<Esc><Esc>\" to stop\n"
+
+#define CONFIG_ETHADDR 00:50:C2:40:10:00
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+
+/*
+ * Default environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "sdram_test=0\0" \
+ "netdev=eth0\0" \
+ "hostname=motionpro\0" \
+ "netmask=255.255.0.0\0" \
+ "ipaddr=192.168.160.22\0" \
+ "serverip=192.168.1.1\0" \
+ "gatewayip=192.168.1.1\0" \
+ "kernel_addr=200000\0" \
+ "u-boot_addr=100000\0" \
+ "kernel_sector=20\0" \
+ "kernel_size=1000\0" \
+ "console=ttyS0,115200\0" \
+ "rootpath=/opt/eldk-4.1/ppc_6xx\0" \
+ "bootfile=/tftpboot/motionpro/uImage\0" \
+ "u-boot=/tftpboot/motionpro/u-boot.bin\0" \
+ "load=tftp $(u-boot_addr) $(u-boot)\0" \
+ "update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; " \
+ "cp.b $(u-boot_addr) fff00000 $(filesize);" \
+ "prot on fff00000 fff3ffff\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) console=$(console) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):" \
+ "$(netmask):$(hostname):$(netdev):off panic=1\0" \
+ "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip;bootm $(kernel_addr) " \
+ "$(ramdisk_addr)\0" \
+ "net_nfs=tftp $(kernel_addr) $(bootfile); run nfsargs addip; " \
+ "bootm $(kernel_addr)\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "fstype=ext3\0" \
+ "fatargs=setenv bootargs init=/linuxrc rw\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run net_nfs"
+
+
+/*
+ * do board-specific init
+ */
+#define CONFIG_BOARD_EARLY_INIT_R 1
+
+
+/*
+ * Low level configuration
+ */
+
+
+/*
+ * Clock configuration: SYS_XTALIN = 25MHz
+ */
+#define CFG_MPC5XXX_CLKIN 25000000
+
+
+/*
+ * Memory map
+ */
+/*
+ * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000.
+ * Setting MBAR to otherwise will cause system hang when using SmartDMA such
+ * as network commands.
+ */
+#define CFG_MBAR 0xf0000000
+#define CFG_SDRAM_BASE 0x00000000
+
+/*
+ * If building for running out of SDRAM, then MBAR has been set up beforehand
+ * (e.g., by the BDI). Otherwise we must specify the default boot-up value of
+ * MBAR, as given in the doccumentation.
+ */
+#if TEXT_BASE == 0x00100000
+#define CFG_DEFAULT_MBAR 0xf0000000
+#else /* TEXT_BASE != 0x00100000 */
+#define CFG_DEFAULT_MBAR 0x80000000
+#define CFG_LOWBOOT 1
+#endif /* TEXT_BASE == 0x00100000 */
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT 1
+#endif
+
+#define CFG_MONITOR_LEN (256 << 10) /* 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
+
+
+/*
+ * Chip selects configuration
+ */
+/* Boot Chipselect */
+#define CFG_BOOTCS_START CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG 0x03035D00
+
+/* Flash memory addressing */
+#define CFG_CS0_START CFG_FLASH_BASE
+#define CFG_CS0_SIZE CFG_FLASH_SIZE
+#define CFG_CS0_CFG CFG_BOOTCS_CFG
+
+/* Dual Port SRAM -- Kollmorgen Drive memory addressing */
+#define CFG_CS1_START 0x50000000
+#define CFG_CS1_SIZE 0x10000
+#define CFG_CS1_CFG 0x05055800
+
+/* Local register access */
+#define CFG_CS2_START 0x50010000
+#define CFG_CS2_SIZE 0x10000
+#define CFG_CS2_CFG 0x05055800
+
+/* Anybus CompactCom Module memory addressing */
+#define CFG_CS3_START 0x50020000
+#define CFG_CS3_SIZE 0x10000
+#define CFG_CS3_CFG 0x05055800
+
+/* No burst and dead cycle = 2 for all CSs */
+#define CFG_CS_BURST 0x00000000
+#define CFG_CS_DEADCYCLE 0x22222222
+
+
+/*
+ * SDRAM configuration
+ */
+/* 2 x MT48LC16M16A2BG-75 IT:D, CASL 2, 32 bit data bus */
+#define SDRAM_CONFIG1 0x52222600
+#define SDRAM_CONFIG2 0x88b70000
+#define SDRAM_CONTROL 0x50570000
+#define SDRAM_MODE 0x008d0000
+
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1
+#define CFG_FLASH_BASE 0xff000000
+#define CFG_FLASH_SIZE 0x01000000
+#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
+#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
+
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+/* This has to be a multiple of the Flash sector size */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_ENV_SIZE 0x1000
+#define CFG_ENV_SECT_SIZE 0x10000
+
+
+/*
+ * Pin multiplexing configuration
+ */
+
+/* PSC1: UART1
+ * PSC2: GPIO (default)
+ * PSC3: GPIO (default)
+ * USB: 2xUART4/5
+ * Ethernet: Ethernet 100Mbit with MD
+ * Timer: CAN2/GPIO
+ * PSC6/IRDA: GPIO (default)
+ */
+#define CFG_GPS_PORT_CONFIG 0x1105a004
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x03f00000 /* 1 ... 64 MiB in DRAM */
+
+#define CFG_LOAD_ADDR 0x200000 /* default kernel load addr */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+
+
+/* Not needed for MPC 5xxx U-Boot, but used by tools/updater */
+#define CFG_RESET_ADDRESS 0xfff00100
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index b767449..f2f0598 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -115,7 +115,7 @@
":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm ${kernel_addr}\0" \
- "flash_nand=nand_args addip addcon;bootm ${kernel_addr}\0" \
+ "flash_nand=run nand_args addip addcon;bootm ${kernel_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/sc3/uImage\0" \
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 098aa3f..29f3b40 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -391,7 +391,7 @@
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CFG_EBC_PB0AP 0x03017300
+#define CFG_EBC_PB0AP 0x03017200
#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000)
/* Memory Bank 3 (NAND-FLASH) initialization */
@@ -400,7 +400,7 @@
#else
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
/* Memory Bank 3 (NOR-FLASH) initialization */
-#define CFG_EBC_PB3AP 0x03017300
+#define CFG_EBC_PB3AP 0x03017200
#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000)
/* Memory Bank 0 (NAND-FLASH) initialization */