diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/Adder.h | 185 | ||||
| -rw-r--r-- | include/configs/mx1ads.h | 185 |
2 files changed, 370 insertions, 0 deletions
diff --git a/include/configs/Adder.h b/include/configs/Adder.h new file mode 100644 index 0000000..11a82c9 --- /dev/null +++ b/include/configs/Adder.h @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2004 Arabella Software Ltd. + * Yuli Barcohen <yuli@arabellasw.com> + * + * Support for Analogue&Micro Adder boards family. + * Tested on AdderII and Adder87x. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T) +#define CONFIG_MPC875 +#endif + +#define CONFIG_ADDER /* Analogue&Micro Adder board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_FEC_ENET /* Ethernet is on FEC */ +#ifdef CONFIG_FEC_ENET +#define CFG_DISCOVER_PHY +#define FEC_ENET +#endif /* CONFIG_FEC_ENET */ + +#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) + +/* This must be included AFTER the definition of CONFIG_COMMANDS */ +#include <cmd_confdefs.h> + +#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ +#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */ +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" + +#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ +#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* #undef to save memory */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* Max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x100000 /* Default load address */ + +#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * RAM configuration (note that CFG_SDRAM_BASE must be zero) + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ + +#define CFG_OR1_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_ACS_DIV2) +#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V) + +#define CFG_MAMR 0x00802114 + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00700000 /* 1 ... 7 MB in SDRAM */ + +#define CFG_RESET_ADDRESS 0x09900000 + +/*----------------------------------------------------------------------- + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 KB for Monitor */ +#ifdef CONFIG_BZIP2 +#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ +#else +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ +#endif /* CONFIG_BZIP2 */ + +/*----------------------------------------------------------------------- + * Flash organisation + */ +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ + +/* Environment is in flash */ +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + +#define CFG_OR0_PRELIM 0xFF000774 +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V) + +/*----------------------------------------------------------------------- + * Internal Memory Map Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Configuration registers + */ +#ifdef CONFIG_WATCHDOG +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ + SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \ + SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ + SYPCR_SWF | SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +#define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11) + +/* TBSCR - Time Base Status and Control Register */ +#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE) + +/* PISCR - Periodic Interrupt Status and Control */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/* PLPRCR - PLL, Low-Power, and Reset Control Register */ +/* #define CFG_PLPRCR PLPRCR_TEXPS */ + +/* SCCR - System Clock and reset Control Register */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR SCCR_RTSEL + +#define CFG_DER 0 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */ + +/*----------------------------------------------------------------------- + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h new file mode 100644 index 0000000..9d4ab2b --- /dev/null +++ b/include/configs/mx1ads.h @@ -0,0 +1,185 @@ +/* + * include/configs/mx1ads.h + * + * (c) Copyright 2004 + * Techware Information Technology, Inc. + * http://www.techware.com.tw/ + * + * Ming-Len Wu <minglen_wu@techware.com.tw> + * + * This is the Configuration setting for Motorola MX1ADS board + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#define CONFIG_INIT_CRITICAL /* undef for developing */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_MC9328 1 /* It's a Motorola MC9328 SoC */ +#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */ + +#define BOARD_LATE_INIT 1 + + +#define USE_920T_MMU 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#if 0 +#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ +#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ +#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ +#endif + +/* + * Size of malloc() pool + */ + +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * CS8900 Ethernet drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x15000300 +#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ + +/* + * select serial console configuration + */ + +#define CONFIG_UART1 1 +/* #define CONFIG_UART2 1 */ + +#define CONFIG_BAUDRATE 115200 + +/*********************************************************** + * Command definition + ***********************************************************/ + +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | \ + CFG_CMD_CACHE | \ + /*CFG_CMD_NAND |*/ \ + /*CFG_CMD_EEPROM |*/ \ + /*CFG_CMD_I2C |*/ \ + /*CFG_CMD_USB |*/ \ + CFG_CMD_REGINFO | \ + CFG_CMD_ELF) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "root=/dev/docbp mem=48M" +#define CONFIG_ETHADDR 08:00:3e:26:0a:5c +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.0.22 +#define CONFIG_SERVERIP 192.168.0.11 +#define CONFIG_BOOTFILE "mx1ads" +/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ + /* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ + +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ + +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "MX1ADS$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "MX1ADS=> " /* Monitor Command Prompt */ +#endif + +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) + /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x09000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x08800000 /* default load address */ + + +#define CFG_HZ 1000 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ + + +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ +#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define CFG_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */ +#define CFG_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */ +#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ + + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + + +#define CONFIG_SYNCFLASH 1 +#define PHYS_FLASH_SIZE 0x01000000 +#define CFG_MAX_FLASH_SECT (16) +#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x00ff0000) + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x0f000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x100000 +#endif /* __CONFIG_H */ |