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-rw-r--r--include/configs/SBC8560.h398
-rw-r--r--include/configs/sbc8240.h365
-rw-r--r--include/configs/sbc8260.h1281
3 files changed, 661 insertions, 1383 deletions
diff --git a/include/configs/SBC8560.h b/include/configs/SBC8560.h
deleted file mode 100644
index cf5ef63..0000000
--- a/include/configs/SBC8560.h
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
- * Added support for Wind River SBC8560 board
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* mpc8560ads board configuration file */
-/* please refer to doc/README.mpc85xx for more info */
-/* make sure you change the MAC address and other network params first,
- * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
-#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
-
-
-#define CONFIG_MPC8560 1 /* MPC8560 specific */
-#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
-
-/* XXX flagging this as something I might want to delete */
-#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
-
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#undef CONFIG_PCI /* pci ethernet support */
-#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
-
-
-#define CONFIG_ENV_OVERWRITE
-
-/* Using Localbus SDRAM to emulate flash before we can program the flash,
- * normally you need a flash-boot image(u-boot.bin), if so undef this.
- */
-#undef CONFIG_RAM_AS_FLASH
-
-#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
- #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
-#else
- #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
-#endif
-
-/* below can be toggled for performance analysis. otherwise use default */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#undef CONFIG_BTB /* toggle branch predition */
-#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-
-#undef CFG_DRAM_TEST /* memory test, takes time */
-#define CFG_MEMTEST_START 0x00200000 /* memtest region */
-#define CFG_MEMTEST_END 0x00400000
-
-#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
- defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
- defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
-#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
-#endif
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
-
-#if XXX
- #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
-#else
- #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */
-#endif
-#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
-
-#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
-#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
-#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */
-#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */
-
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-
-#if defined(CONFIG_MPC85xx_REV1)
- #define CONFIG_DDR_DLL /* possible DLL fix needed */
-#endif
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-#if defined(CONFIG_RAM_AS_FLASH)
- #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
- #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
- #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */
- #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
-#else /* Boot from real Flash */
- #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
- #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
- #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */
- #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
-#endif
-#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-/* local bus definitions */
-#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
-#define CFG_OR1_PRELIM 0xfc000ff7
-
-#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */
-#define CFG_OR2_PRELIM 0x00000000
-
-#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
-#define CFG_OR3_PRELIM 0xfc000cc1
-
-#if defined(CONFIG_RAM_AS_FLASH)
- #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
-#else
- #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
-#endif
-#define CFG_OR4_PRELIM 0xfc000cc1
-
-#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
-#if 1
- #define CFG_OR5_PRELIM 0xff000ff7
-#else
- #define CFG_OR5_PRELIM 0xff0000f0
-#endif
-
-#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
-#define CFG_OR6_PRELIM 0xfc000ff7
-#define CFG_LBC_LCRR 0x00030002 /* local bus freq */
-#define CFG_LBC_LBCR 0x00000000
-#define CFG_LBC_LSRT 0x20000000
-#define CFG_LBC_MRTPR 0x20000000
-#define CFG_LBC_LSDMR_1 0x2861b723
-#define CFG_LBC_LSDMR_2 0x0861b723
-#define CFG_LBC_LSDMR_3 0x0861b723
-#define CFG_LBC_LSDMR_4 0x1861b723
-#define CFG_LBC_LSDMR_5 0x4061b723
-
-/* just hijack the MOT BCSR def for SBC8560 misc devices */
-#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
-/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
-
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
-#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
-
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-
-#define CONFIG_CONS_INDEX 1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE 1
-#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */
-#define CONFIG_BAUDRATE 9600
-
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
-#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
-
-/* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-#endif
-
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-
-#define CFG_PCI_MEM_BASE 0xC0000000
-#define CFG_PCI_MEM_PHYS 0xC0000000
-#define CFG_PCI_MEM_SIZE 0x10000000
-
-#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
-
- #define CONFIG_NET_MULTI 1
- #define CONFIG_PHY_BCM5421S 1 /* GigaBit Ether PHY */
- #define CONFIG_MII 1 /* MII PHY management */
- #define CONFIG_PHY_ADDR 25 /* PHY address */
-
-#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
-
- #undef CONFIG_ETHER_NONE /* define if ether on something else */
- #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
- #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
-
- #if (CONFIG_ETHER_INDEX == 2)
- /*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers
- * - Full duplex
- */
- #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
- #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
- #define CFG_CPMFCR_RAMTYPE 0
- #define CFG_FCC_PSMR (FCC_PSMR_FDE)
-
- #elif (CONFIG_ETHER_INDEX == 3)
- /* need more definitions here for FE3 */
- #endif /* CONFIG_ETHER_INDEX */
-
- #define CONFIG_MII /* MII PHY management */
- #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
- /*
- * GPIO pins used for bit-banged MII communications
- */
- #define MDIO_PORT 2 /* Port C */
- #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
- #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
- #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
-
- #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
-
- #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
- else iop->pdat &= ~0x00200000
-
- #define MIIDELAY udelay(1)
-
-#endif
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#if 0
-#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CFG_FLASH_PROTECTION /* use hardware protection */
-#endif
-#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
-
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-
-#if 0
-/* XXX This doesn't work and I don't want to fix it */
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
- #define CFG_RAMBOOT
-#else
- #undef CFG_RAMBOOT
-#endif
-#endif
-
-/* Environment */
-#if !defined(CFG_RAMBOOT)
- #if defined(CONFIG_RAM_AS_FLASH)
- #define CFG_ENV_IS_NOWHERE
- #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
- #define CFG_ENV_SIZE 0x2000
- #else
- #define CFG_ENV_IS_IN_FLASH 1
- #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
- #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */
- #endif
-#else
- #define CFG_NO_FLASH 1 /* Flash is not usable now */
- #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
- #define CFG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
-/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
-#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
-#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV | \
- CFG_CMD_LOADS ))
- #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C) & \
- ~(CFG_CMD_ENV))
- #endif
-#else
- #if defined(CONFIG_PCI)
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
- CFG_CMD_PING | CFG_CMD_I2C)
- #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
- CFG_CMD_PING | CFG_CMD_I2C)
- #endif
-#endif
-
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
- #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_LOAD_ADDR 0x1000000 /* default load address */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
- #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
- #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
- #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*Note: change below for your network setting!!! */
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_ETHADDR 00:01:af:07:9b:8a
- #define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
- #define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
-#endif
-
-#define CONFIG_SERVERIP 192.168.0.131
-#define CONFIG_IPADDR 192.168.0.105
-#define CONFIG_GATEWAYIP 0.0.0.0
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_HOSTNAME SBC8560
-#define CONFIG_ROOTPATH /home/ppc
-#define CONFIG_BOOTFILE pImage
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/sbc8240.h b/include/configs/sbc8240.h
new file mode 100644
index 0000000..d891e07
--- /dev/null
+++ b/include/configs/sbc8240.h
@@ -0,0 +1,365 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Configuration settings for the sbc8240 board.
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X 1
+#define CONFIG_MPC8240 1
+#define CONFIG_WRSBC8240 1
+
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 9600
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type \"? or help\" to get on-line help;echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_BOOTCOMMAND "version;echo;tftpboot $loadaddr $loadfile;bootvx" /* autoboot command */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st " \
+ "e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 " \
+ "tn=sbc8240 o=fei \0" \
+ "env_startaddr=FFF70000\0" \
+ "env_endaddr=FFF7FFFF\0" \
+ "loadfile=vxWorks.st\0" \
+ "loadaddr=0x01000000\0" \
+ "net_load=tftpboot $loadaddr $loadfile\0" \
+ "uboot_startaddr=FFF00000\0" \
+ "uboot_endaddr=FFF3FFFF\0" \
+ "update=tftp $loadaddr /u-boot.bin;" \
+ "protect off $uboot_startaddr $uboot_endaddr;" \
+ "era $uboot_startaddr $uboot_endaddr;" \
+ "cp.b $loadaddr $uboot_startaddr $filesize;" \
+ "protect on $uboot_startaddr $uboot_endaddr\0" \
+ "zapenv=protect off $env_startaddr $env_endaddr;" \
+ "era $env_startaddr $env_endaddr;" \
+ "protect on $env_startaddr $env_endaddr\0"
+
+#define CONFIG_BOOTDELAY 5
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_BSP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ELF | \
+ CFG_CMD_ENV | \
+ CFG_CMD_FLASH | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_SDRAM | \
+ 0 )
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+
+#if 1
+#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
+#endif
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
+#define CONFIG_IPADDR 192.168.193.102
+#define CONFIG_NETMASK 255.255.255.248
+#define CONFIG_SERVERIP 192.168.193.99
+
+#define CONFIG_STATUS_LED /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
+
+#define STATUS_LED_BIT 0x00000001
+#define STATUS_LED_PERIOD (CFG_HZ / 2)
+#define STATUS_LED_STATE STATUS_LED_BLINKING
+#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
+#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
+#ifndef __ASSEMBLY__
+/* LEDs */
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+ do { \
+ *((volatile char *) (CFG_LED_BASE)) ^= (_msk); \
+ } while(0)
+
+#define __led_set(_msk, _st) \
+ do { \
+ if ((_st)) \
+ *((volatile char *) (CFG_LED_BASE)) |= (_msk); \
+ else \
+ *((volatile char *) (CFG_LED_BASE)) &= ~(_msk); \
+ } while(0)
+
+#define __led_init(msk, st) __led_set(msk, st)
+
+#endif
+
+#define CONFIG_MISC_INIT_R
+#define CFG_LED_BASE 0xFFE80000
+
+/* Print Buffer Size
+ */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFFF00000
+
+#define CFG_RESET_ADDRESS 0xFFF00100
+
+#define CFG_EUMB_ADDR 0xFCE00000
+
+#define CFG_MONITOR_BASE TEXT_BASE
+
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
+#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
+
+ /* Maximum amount of RAM.
+ */
+#define CFG_MAX_RAM_SIZE 0x10000000
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#undef CFG_RAMBOOT
+#else
+#define CFG_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+ /* Size in bytes reserved for initial data
+ */
+#define CFG_GBL_DATA_SIZE 128
+
+#define CFG_INIT_RAM_ADDR 0x40000000
+#define CFG_INIT_RAM_END 0x1000
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE 1
+
+#define CFG_NS16550_CLK 3686400
+
+#define CFG_NS16550_COM1 0xFFF80000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ 33000000
+#define CFG_HZ 1000
+#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
+
+ /* Bit-field values for MCCR1.
+ */
+#define CFG_ROMNAL 0
+#define CFG_ROMFAL 7
+
+ /* Bit-field values for MCCR2.
+ */
+#define CFG_REFINT 430 /* Refresh interval */
+
+ /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+ */
+#define CFG_BSTOPRE 192
+
+ /* Bit-field values for MCCR3.
+ */
+#define CFG_REFREC 2 /* Refresh to activate interval */
+#define CFG_RDLAT 3 /* Data latancy from read command */
+
+ /* Bit-field values for MCCR4.
+ */
+#define CFG_PRETOACT 2 /* Precharge to activate interval */
+#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
+#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
+#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
+#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
+#define CFG_ACTORW 2
+#define CFG_REGISTERD_TYPE_BUFFER 1
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CFG_BANK0_START 0x00000000
+#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE 1
+#define CFG_BANK1_START 0x3ff00000
+#define CFG_BANK1_END 0x3fffffff
+#define CFG_BANK1_ENABLE 0
+#define CFG_BANK2_START 0x3ff00000
+#define CFG_BANK2_END 0x3fffffff
+#define CFG_BANK2_ENABLE 0
+#define CFG_BANK3_START 0x3ff00000
+#define CFG_BANK3_END 0x3fffffff
+#define CFG_BANK3_ENABLE 0
+#define CFG_BANK4_START 0x3ff00000
+#define CFG_BANK4_END 0x3fffffff
+#define CFG_BANK4_ENABLE 0
+#define CFG_BANK5_START 0x3ff00000
+#define CFG_BANK5_END 0x3fffffff
+#define CFG_BANK5_ENABLE 0
+#define CFG_BANK6_START 0x3ff00000
+#define CFG_BANK6_END 0x3fffffff
+#define CFG_BANK6_ENABLE 0
+#define CFG_BANK7_START 0x3ff00000
+#define CFG_BANK7_END 0x3fffffff
+#define CFG_BANK7_ENABLE 0
+
+#define CFG_ODCR 0xff
+
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
+#define CFG_MAX_FLASH_SECT 256 /* Max number of sectors in one bank */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
+
+ /* Warining: environment is not EMBEDDED in the U-Boot code.
+ * It's stored in flash separately.
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR 0xFFF70000
+#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */
+#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
+#define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* we need Plug 'n Play */
+#define CONFIG_NET_MULTI /* Multi ethernet cards support */
+#define CONFIG_TULIP
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
+#endif /* __CONFIG_H */
diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h
index 251d62a..cf5ef63 100644
--- a/include/configs/sbc8260.h
+++ b/include/configs/sbc8260.h
@@ -1,17 +1,9 @@
/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
*
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Jay Monkman <jtm@smoothsmoothie.com>
- *
- * Configuration settings for the WindRiver SBC8260 board.
- * See http://www.windriver.com/products/html/sbc8260.html
+ * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+ * Added support for Wind River SBC8560 board
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -32,1056 +24,375 @@
* MA 02111-1307 USA
*/
+/* mpc8560ads board configuration file */
+/* please refer to doc/README.mpc85xx for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
#ifndef __CONFIG_H
#define __CONFIG_H
-/* Enable debug prints */
-#undef DEBUG /* General debug */
-#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
+#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
-/*****************************************************************************
- *
- * These settings must match the way _your_ board is set up
- *
- *****************************************************************************/
-/* What is the oscillator's (UX2) frequency in Hz? */
-#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
-
-/*-----------------------------------------------------------------------
- * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
- *-----------------------------------------------------------------------
- * What should MODCK_H be? It is dependent on the oscillator
- * frequency, MODCK[1-3], and desired CPM and core frequencies.
- * Here are some example values (all frequencies are in MHz):
- *
- * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
- * ------- ---------- --- --- ---- ----- ----- -----
- * 0x1 0x5 33 100 133 Open Close Open
- * 0x1 0x6 33 100 166 Open Open Close
- * 0x1 0x7 33 100 200 Open Open Open
- *
- * 0x2 0x2 33 133 133 Close Open Close
- * 0x2 0x3 33 133 166 Close Open Open
- * 0x2 0x4 33 133 200 Open Close Close
- * 0x2 0x5 33 133 233 Open Close Open
- * 0x2 0x6 33 133 266 Open Open Close
- *
- * 0x5 0x5 66 133 133 Open Close Open
- * 0x5 0x6 66 133 166 Open Open Close
- * 0x5 0x7 66 133 200 Open Open Open
- * 0x6 0x0 66 133 233 Close Close Close
- * 0x6 0x1 66 133 266 Close Close Open
- * 0x6 0x2 66 133 300 Close Open Close
- */
-#define CFG_SBC_MODCK_H 0x05
+#define CONFIG_MPC8560 1 /* MPC8560 specific */
+#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
-/* Define this if you want to boot from 0x00000100. If you don't define
- * this, you will need to program the bootloader to 0xfff00000, and
- * get the hardware reset config words at 0xfe000000. The simplest
- * way to do that is to program the bootloader at both addresses.
- * It is suggested that you just let U-Boot live at 0x00000000.
- */
-#define CFG_SBC_BOOT_LOW 1
+/* XXX flagging this as something I might want to delete */
+#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
- * The main FLASH is whichever is connected to *CS0. U-Boot expects
- * this to be the SIMM.
- */
-#define CFG_FLASH0_BASE 0x40000000
-#define CFG_FLASH0_SIZE 4
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#undef CONFIG_PCI /* pci ethernet support */
+#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
-/* What should the base address of the secondary FLASH be and how big
- * is it (in Mbytes)? The secondary FLASH is whichever is connected
- * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
- * want it enabled, don't define these constants.
- */
-#define CFG_FLASH1_BASE 0x60000000
-#define CFG_FLASH1_SIZE 2
-/* What should be the base address of SDRAM DIMM and how big is
- * it (in Mbytes)?
-*/
-#define CFG_SDRAM0_BASE 0x00000000
-#define CFG_SDRAM0_SIZE 64
+#define CONFIG_ENV_OVERWRITE
-/* What should be the base address of the LEDs and switch S0?
- * If you don't want them enabled, don't define this.
+/* Using Localbus SDRAM to emulate flash before we can program the flash,
+ * normally you need a flash-boot image(u-boot.bin), if so undef this.
*/
-#define CFG_LED_BASE 0xa0000000
+#undef CONFIG_RAM_AS_FLASH
+#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
+ #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
+#else
+ #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
+#endif
-/*
- * SBC8260 with 16 MB DIMM:
- *
- * 0x0000 0000 Exception Vector code, 8k
- * :
- * 0x0000 1FFF
- * 0x0000 2000 Free for Application Use
- * :
- * :
- *
- * :
- * :
- * 0x00F5 FF30 Monitor Stack (Growing downward)
- * Monitor Stack Buffer (0x80)
- * 0x00F5 FFB0 Board Info Data
- * 0x00F6 0000 Malloc Arena
- * : CFG_ENV_SECT_SIZE, 256k
- * : CFG_MALLOC_LEN, 128k
- * 0x00FC 0000 RAM Copy of Monitor Code
- * : CFG_MONITOR_LEN, 256k
- * 0x00FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
- */
+/* below can be toggled for performance analysis. otherwise use default */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#undef CONFIG_BTB /* toggle branch predition */
+#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
-/*
- * SBC8260 with 64 MB DIMM:
- *
- * 0x0000 0000 Exception Vector code, 8k
- * :
- * 0x0000 1FFF
- * 0x0000 2000 Free for Application Use
- * :
- * :
- *
- * :
- * :
- * 0x03F5 FF30 Monitor Stack (Growing downward)
- * Monitor Stack Buffer (0x80)
- * 0x03F5 FFB0 Board Info Data
- * 0x03F6 0000 Malloc Arena
- * : CFG_ENV_SECT_SIZE, 256k
- * : CFG_MALLOC_LEN, 128k
- * 0x03FC 0000 RAM Copy of Monitor Code
- * : CFG_MONITOR_LEN, 256k
- * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
- */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest region */
+#define CFG_MEMTEST_END 0x00400000
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere.
- */
-#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on neither */
-#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
+#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
+ defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
+ defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
+#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
+#endif
/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
*/
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
-#undef CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_ON_FCC
-#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
-
-#ifdef CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
-#endif /* CONFIG_ETHER_ON_SCC */
-
-#ifdef CONFIG_ETHER_ON_FCC
-#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
-#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
-/*
- * Port pins used for bit-banged MII communictions (if applicable).
- */
-#define MDIO_PORT 2 /* Port C */
-#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
-#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
-#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
+#if XXX
+ #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
+#else
+ #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */
+#endif
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
-#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */
+#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */
-#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
- else iop->pdat &= ~0x00200000
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define MIIDELAY udelay(1)
-#endif /* CONFIG_ETHER_ON_FCC */
+#if defined(CONFIG_MPC85xx_REV1)
+ #define CONFIG_DDR_DLL /* possible DLL fix needed */
+#endif
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#if defined(CONFIG_RAM_AS_FLASH)
+ #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
+ #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
+ #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */
+ #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
+#else /* Boot from real Flash */
+ #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
+ #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
+ #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */
+ #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
+#endif
+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-/*
- * - RX clk is CLK11
- * - TX clk is CLK12
- */
-# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
+/* local bus definitions */
+#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
+#define CFG_OR1_PRELIM 0xfc000ff7
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */
+#define CFG_OR2_PRELIM 0x00000000
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE 0
-# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
+#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
+#define CFG_OR3_PRELIM 0xfc000cc1
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+#if defined(CONFIG_RAM_AS_FLASH)
+ #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
+#else
+ #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
+#endif
+#define CFG_OR4_PRELIM 0xfc000cc1
-/*
- * Select SPI support configuration
- */
-#undef CONFIG_SPI /* Disable SPI driver */
+#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
+#if 1
+ #define CFG_OR5_PRELIM 0xff000ff7
+#else
+ #define CFG_OR5_PRELIM 0xff0000f0
+#endif
-/*
- * Select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
+#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
+#define CFG_OR6_PRELIM 0xfc000ff7
+#define CFG_LBC_LCRR 0x00030002 /* local bus freq */
+#define CFG_LBC_LBCR 0x00000000
+#define CFG_LBC_LSRT 0x20000000
+#define CFG_LBC_MRTPR 0x20000000
+#define CFG_LBC_LSDMR_1 0x2861b723
+#define CFG_LBC_LSDMR_2 0x0861b723
+#define CFG_LBC_LSDMR_3 0x0861b723
+#define CFG_LBC_LSDMR_4 0x1861b723
+#define CFG_LBC_LSDMR_5 0x4061b723
+
+/* just hijack the MOT BCSR def for SBC8560 misc devices */
+#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
+/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#ifdef CONFIG_SOFT_I2C
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SOFT_I2C */
-
-
-/* Define this to reserve an entire FLASH sector (256 KB) for
- * environment variables. Otherwise, the environment will be
- * put in the same sector as U-Boot, and changing variables
- * will erase U-Boot temporarily
- */
-#define CFG_ENV_IN_OWN_SECT 1
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
-/* Define to allow the user to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
+/* Serial Port */
+#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
+#undef CONFIG_CONS_NONE /* define if console on something else */
-/* What should the console's baud rate be? */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */
#define CONFIG_BAUDRATE 9600
-/* Ethernet MAC address
- * Note: We are using the EST Corporation OUI (00:a0:1e:xx:xx:xx)
- * http://standards.ieee.org/regauth/oui/index.shtml
- */
-#define CONFIG_ETHADDR 00:a0:1e:a8:7b:cb
-
-/*
- * Define this to set the last octet of the ethernet address from the
- * DS0-DS7 switch and light the LEDs with the result. The DS0-DS7
- * switch and the LEDs are backwards with respect to each other. DS7
- * is on the board edge side of both the LED strip and the DS0-DS7
- * switch.
- */
-#undef CONFIG_MISC_INIT_R
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-/* Set to a positive value to delay for running BOOTCOMMAND */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
+#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
-/* Be selective on what keys can delay or stop the autoboot process
- * To stop use: " "
- */
-#undef CONFIG_AUTOBOOT_KEYED
-#ifdef CONFIG_AUTOBOOT_KEYED
-# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"
-# define CONFIG_AUTOBOOT_STOP_STR " "
-# undef CONFIG_AUTOBOOT_DELAY_STR
-# define DEBUG_BOOTKEYS 0
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* Define this to contain any number of null terminated strings that
- * will be part of the default enviroment compiled into the boot image.
- *
- * Variable Usage
- * -------------- -------------------------------------------------------
- * serverip server IP address
- * ipaddr my IP address
- * reprog Reload flash with a new copy of U-Boot
- * zapenv Erase the environment area in flash
- * root-on-initrd Set the bootcmd variable to allow booting of an initial
- * ram disk.
- * root-on-nfs Set the bootcmd variable to allow booting of a NFS
- * mounted root filesystem.
- * boot-hook Convenient stub to do something useful before the
- * bootm command is executed.
- *
- * Example usage of root-on-initrd and root-on-nfs :
- *
- * Note: The lines have been wrapped to improved its readability.
- *
- * => printenv bootcmd
- * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
- * nfsroot=$(serverip):$(rootpath)
- * ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;run boot-hook;bootm
- *
- * => run root-on-initrd
- * => printenv bootcmd
- * bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw
- * ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;run boot-hook;bootm
- *
- * => run root-on-nfs
- * => printenv bootcmd
- * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
- * nfsroot=$(serverip):$(rootpath)
- * ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;run boot-hook;bootm
- *
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "serverip=192.168.123.205\0\0" \
- "ipaddr=192.168.123.213\0" \
- "reprog="\
- "bootp;" \
- "tftpboot 0x140000 /bdi2000/u-boot.bin;" \
- "protect off 1:0;" \
- "erase 1:0;" \
- "cp.b 140000 40000000 $(filesize);" \
- "protect on 1:0\0" \
- "zapenv="\
- "protect off 1:1;" \
- "erase 1:1;" \
- "protect on 1:1\0" \
- "root-on-initrd="\
- "setenv bootcmd "\
- "version;" \
- "echo;" \
- "bootp;" \
- "setenv bootargs root=/dev/ram0 rw " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
- "run boot-hook;" \
- "bootm\0" \
- "root-on-nfs="\
- "setenv bootcmd "\
- "version;" \
- "echo;" \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
- "run boot-hook;" \
- "bootm\0" \
- "boot-hook=echo\0"
-
-/* Define a command string that is automatically executed when no character
- * is read on the console interface withing "Boot Delay" after reset.
- */
-#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
-#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
-
-#ifdef CONFIG_BOOT_ROOT_INITRD
-#define CONFIG_BOOTCOMMAND \
- "version;" \
- "echo;" \
- "bootp;" \
- "setenv bootargs root=/dev/ram0 rw " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
- "bootm"
-#endif /* CONFIG_BOOT_ROOT_INITRD */
-
-#ifdef CONFIG_BOOT_ROOT_NFS
-#define CONFIG_BOOTCOMMAND \
- "version;" \
- "echo;" \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
- "bootm"
-#endif /* CONFIG_BOOT_ROOT_NFS */
-
-/* Add support for a few extra bootp options like:
- * - File size
- * - DNS (up to 2 servers)
- * - Send hostname to DHCP server
- */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME)
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+
+#define CFG_PCI_MEM_BASE 0xC0000000
+#define CFG_PCI_MEM_PHYS 0xC0000000
+#define CFG_PCI_MEM_SIZE 0x10000000
+
+#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
+
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_PHY_BCM5421S 1 /* GigaBit Ether PHY */
+ #define CONFIG_MII 1 /* MII PHY management */
+ #define CONFIG_PHY_ADDR 25 /* PHY address */
+
+#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
+
+ #undef CONFIG_ETHER_NONE /* define if ether on something else */
+ #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
+ #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
+
+ #if (CONFIG_ETHER_INDEX == 2)
+ /*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers
+ * - Full duplex
+ */
+ #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+ #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+ #define CFG_CPMFCR_RAMTYPE 0
+ #define CFG_FCC_PSMR (FCC_PSMR_FDE)
+
+ #elif (CONFIG_ETHER_INDEX == 3)
+ /* need more definitions here for FE3 */
+ #endif /* CONFIG_ETHER_INDEX */
+
+ #define CONFIG_MII /* MII PHY management */
+ #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
+ /*
+ * GPIO pins used for bit-banged MII communications
+ */
+ #define MDIO_PORT 2 /* Port C */
+ #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
+ #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
+ #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
+
+ #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
+ else iop->pdat &= ~0x00400000
-/* undef this to save memory */
-#define CFG_LONGHELP
+ #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
+ else iop->pdat &= ~0x00200000
-/* Monitor Command Prompt */
-#define CFG_PROMPT "=> "
+ #define MIIDELAY udelay(1)
-#undef CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
- * of an image is printed by image commands like bootm or iminfo.
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
*/
-#define CONFIG_TIMESTAMP
-/* If this variable is defined, an environment variable named "ver"
- * is created by U-Boot showing the U-Boot version.
- */
-#define CONFIG_VERSION_VARIABLE
-
-/* What U-Boot subsytems do you want enabled? */
-#ifdef CONFIG_ETHER_ON_FCC
-# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
- CFG_CMD_ASKENV | \
- CFG_CMD_ECHO | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IMMAP | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM )
-#else
-# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
- CFG_CMD_ASKENV | \
- CFG_CMD_ECHO | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IMMAP | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM )
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#undef CONFIG_WATCHDOG /* disable the watchdog */
-
-/* Where do the internal registers live? */
-#define CFG_IMMR 0xF0000000
-
-/*****************************************************************************
- *
- * You should not have to modify any of the following settings
- *
- *****************************************************************************/
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#if 0
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_PROTECTION /* use hardware protection */
+#endif
+#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
-#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-/*
- * Miscellaneous configurable options
- */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#if 0
+/* XXX This doesn't work and I don't want to fix it */
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+ #define CFG_RAMBOOT
#else
-# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+ #undef CFG_RAMBOOT
+#endif
#endif
-/* Print Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
-
-#define CFG_MAXARGS 32 /* max number of command args */
-
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_LOAD_ADDR 0x400000 /* default load address */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+/* Environment */
+#if !defined(CFG_RAMBOOT)
+ #if defined(CONFIG_RAM_AS_FLASH)
+ #define CFG_ENV_IS_NOWHERE
+ #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
+ #define CFG_ENV_SIZE 0x2000
+ #else
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
+ #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */
+ #endif
+#else
+ #define CFG_NO_FLASH 1 /* Flash is not usable now */
+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+ #define CFG_ENV_SIZE 0x2000
+#endif
-#define CFG_ALT_MEMTEST /* Select full-featured memory test */
-#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
- /* the exception vector table */
- /* to the end of the DRAM */
- /* less monitor and malloc area */
-#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
-#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
- + CFG_MALLOC_LEN \
- + CFG_ENV_SECT_SIZE \
- + CFG_STACK_USAGE )
+#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
+/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
+#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
+#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+ #if defined(CONFIG_PCI)
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
+ CFG_CMD_PING | CFG_CMD_I2C) & \
+ ~(CFG_CMD_ENV | \
+ CFG_CMD_LOADS ))
+ #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
+ CFG_CMD_PING | CFG_CMD_I2C) & \
+ ~(CFG_CMD_ENV))
+ #endif
+#else
+ #if defined(CONFIG_PCI)
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
+ CFG_CMD_PING | CFG_CMD_I2C)
+ #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
+ CFG_CMD_PING | CFG_CMD_I2C)
+ #endif
+#endif
-#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
- - CFG_MEM_END_USAGE )
+#include <cmd_confdefs.h>
-/* valid baudrates */
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CFG_FLASH_BASE CFG_FLASH0_BASE
-#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
-#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
-#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
+ * Miscellaneous configurable options
*/
-#if defined(CFG_SBC_BOOT_LOW)
-# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-# define CFG_SBC_HRCW_BOOT_FLAGS (0)
-#endif /* defined(CFG_SBC_BOOT_LOW) */
-
-/* get the HRCW ISB field from CFG_IMMR */
-#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
- ((CFG_IMMR & 0x01000000) >> 7) | \
- ((CFG_IMMR & 0x00100000) >> 4) )
-
-#define CFG_HRCW_MASTER ( HRCW_BPS11 | \
- HRCW_DPPC11 | \
- CFG_SBC_HRCW_IMMR | \
- HRCW_MMR00 | \
- HRCW_LBPC11 | \
- HRCW_APPC10 | \
- HRCW_CS10PC00 | \
- (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \
- CFG_SBC_HRCW_BOOT_FLAGS )
-
-/* no slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_RAM_ADDR CFG_IMMR
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
- */
-#define CFG_MONITOR_BASE CFG_FLASH0_BASE
-
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-# define CFG_RAMBOOT
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x1000000 /* default load address */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
-
-#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
-
-#ifndef CFG_RAMBOOT
-# define CFG_ENV_IS_IN_FLASH 1
-
-# ifdef CFG_ENV_IN_OWN_SECT
-# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
-# define CFG_ENV_SECT_SIZE 0x40000
-# else
-# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
-# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
-# endif /* CFG_ENV_IN_OWN_SECT */
-
-#else
-# define CFG_ENV_IS_IN_NVRAM 1
-# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
-# define CFG_ENV_SIZE 0x200
-#endif /* CFG_RAMBOOT */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+ #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CFG_HID0_INIT (HID0_ICE |\
- HID0_DCE |\
- HID0_ICFI |\
- HID0_DCI |\
- HID0_IFEM |\
- HID0_ABE)
-
-#define CFG_HID0_FINAL (HID0_ICE |\
- HID0_IFEM |\
- HID0_ABE |\
- HID0_EMCP)
-#define CFG_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register
- *-----------------------------------------------------------------------
- */
-#define CFG_RMR 0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define CFG_BCR (BCR_ETM)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-
-#define CFG_SIUMCR (SIUMCR_DPPC11 |\
- SIUMCR_L2CPC00 |\
- SIUMCR_APPC10 |\
- SIUMCR_MMR00)
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR (SYPCR_SWTC |\
- SYPCR_BMT |\
- SYPCR_PBME |\
- SYPCR_LBME |\
- SYPCR_SWRI |\
- SYPCR_SWP |\
- SYPCR_SWE)
-#else
-#define CFG_SYPCR (SYPCR_SWTC |\
- SYPCR_BMT |\
- SYPCR_PBME |\
- SYPCR_LBME |\
- SYPCR_SWRI |\
- SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CFG_TMCNTSC (TMCNTSC_SEC |\
- TMCNTSC_ALR |\
- TMCNTSC_TCF |\
- TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CFG_PISCR (PISCR_PS |\
- PISCR_PTF |\
- PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- */
-#define CFG_SCCR 0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CFG_RCCR 0
-
/*
- * Initialize Memory Controller:
- *
- * Bank Bus Machine PortSz Device
- * ---- --- ------- ------ ------
- * 0 60x GPCM 32 bit FLASH (SIMM - 4MB) *
- * 1 60x GPCM 32 bit FLASH (SIMM - Unused)
- * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB)
- * 3 60x SDRAM 64 bit SDRAM (DIMM - Unused)
- * 4 Local SDRAM 32 bit SDRAM (on board - 4MB)
- * 5 60x GPCM 8 bit EEPROM (8KB)
- * 6 60x GPCM 8 bit FLASH (on board - 2MB) *
- * 7 60x GPCM 8 bit LEDs, switches
- *
- * (*) This configuration requires the SBC8260 be configured
- * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
- * the on board FLASH. In other words, JP24 should have
- * pins 1 and 2 jumpered and pins 3 and 4 jumpered.
- *
- */
-
-/*-----------------------------------------------------------------------
- * BR0,BR1 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR0,OR1 - Option Register
- * Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 0,1 - FLASH SIMM
- *
- * This expects the FLASH SIMM to be connected to *CS0
- * It consists of 4 AM29F080B parts.
- *
- * Note: For the 4 MB SIMM, *CS1 is unused.
- */
-
-/* BR0 is configured as follows:
- *
- * - Base address of 0x40000000
- * - 32 bit port size
- * - Data errors checking is disabled
- * - Read and write access
- * - GPCM 60x bus
- * - Access are handled by the memory controller according to MSEL
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- */
-#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-/* OR0 is configured as follows:
- *
- * - 4 MB
- * - *BCTL0 is asserted upon access to the current memory bank
- * - *CW / *WE are negated a quarter of a clock earlier
- * - *CS is output at the same time as the address lines
- * - Uses a clock cycle length of 5
- * - *PSDVAL is generated internally by the memory controller
- * unless *GTA is asserted earlier externally.
- * - Relaxed timing is generated by the GPCM for accesses
- * initiated to this memory region.
- * - One idle clock is inserted between a read access from the
- * current bank and the next access.
- */
-#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_TRLX |\
- ORxG_EHTR)
-
-/*-----------------------------------------------------------------------
- * BR2,BR3 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR2,OR3 - Option Register
- * Ref: Section 10.3.2 on page 10-16
- *-----------------------------------------------------------------------
- */
-
-/* Bank 2,3 - SDRAM DIMM
- *
- * 16MB DIMM: P/N
- * 64MB DIMM: P/N 1W-8864X8-4-P1-EST
- *
- * Note: *CS3 is unused for this DIMM
- */
-
-/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
- *
- * - Base address of 0x00000000
- * - 64 bit port size (60x bus only)
- * - Data errors checking is disabled
- * - Read and write access
- * - SDRAM 60x bus
- * - Access are handled by the memory controller according to MSEL
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- */
-#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-#define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
-
-/* With a 16 MB DIMM, the OR2 is configured as follows:
- *
- * - 16 MB
- * - 2 internal banks per device
- * - Row start address bit is A9 with PSDMR[PBI] = 0
- * - 11 row address lines
- * - Back-to-back page mode
- * - Internal bank interleaving within save device enabled
- */
-#if (CFG_SDRAM0_SIZE == 16)
-#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
- ORxS_BPD_2 |\
- ORxS_ROWST_PBI0_A9 |\
- ORxS_NUMR_11)
-#endif
-
-/* With a 64 MB DIMM, the OR2 is configured as follows:
- *
- * - 64 MB
- * - 4 internal banks per device
- * - Row start address bit is A8 with PSDMR[PBI] = 0
- * - 12 row address lines
- * - Back-to-back page mode
- * - Internal bank interleaving within save device enabled
- */
-#if (CFG_SDRAM0_SIZE == 64)
-#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A8 |\
- ORxS_NUMR_12)
-#endif
-
-/*-----------------------------------------------------------------------
- * PSDMR - 60x Bus SDRAM Mode Register
- * Ref: Section 10.3.3 on page 10-21
- *-----------------------------------------------------------------------
- */
-
-/* Address that the DIMM SPD memory lives at.
- */
-#define SDRAM_SPD_ADDR 0x54
-
-#if (CFG_SDRAM0_SIZE == 16)
-/* With a 16 MB DIMM, the PSDMR is configured as follows:
+ * Internal Definitions
*
- * - Bank Based Interleaving,
- * - Refresh Enable,
- * - Address Multiplexing where A5 is output on A14 pin
- * (A6 on A15, and so on),
- * - use address pins A16-A18 as bank select,
- * - A9 is output on SDA10 during an ACTIVATE command,
- * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- * is 3 clocks,
- * - earliest timing for READ/WRITE command after ACTIVATE command is
- * 2 clocks,
- * - earliest timing for PRECHARGE after last data was read is 1 clock,
- * - earliest timing for PRECHARGE after last data was written is 1 clock,
- * - CAS Latency is 2.
+ * Boot Flags
*/
-#define CFG_PSDMR (PSDMR_RFEN |\
- PSDMR_SDAM_A14_IS_A5 |\
- PSDMR_BSMA_A16_A18 |\
- PSDMR_SDA10_PBI0_A9 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_3W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
-#endif
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CFG_SDRAM0_SIZE == 64)
-/* With a 64 MB DIMM, the PSDMR is configured as follows:
- *
- * - Bank Based Interleaving,
- * - Refresh Enable,
- * - Address Multiplexing where A5 is output on A14 pin
- * (A6 on A15, and so on),
- * - use address pins A14-A16 as bank select,
- * - A9 is output on SDA10 during an ACTIVATE command,
- * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- * is 3 clocks,
- * - earliest timing for READ/WRITE command after ACTIVATE command is
- * 2 clocks,
- * - earliest timing for PRECHARGE after last data was read is 1 clock,
- * - earliest timing for PRECHARGE after last data was written is 1 clock,
- * - CAS Latency is 2.
- */
-#define CFG_PSDMR (PSDMR_RFEN |\
- PSDMR_SDAM_A14_IS_A5 |\
- PSDMR_BSMA_A14_A16 |\
- PSDMR_SDA10_PBI0_A9 |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_3W |\
- PSDMR_ACTTORW_2W |\
- PSDMR_LDOTOPRE_1C |\
- PSDMR_WRC_1C |\
- PSDMR_CL_2)
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
-/*
- * Shoot for approximately 1MHz on the prescaler.
- */
-#if (CONFIG_8260_CLKIN == (66 * 1000 * 1000))
-#define CFG_MPTPR MPTPR_PTP_DIV64
-#elif (CONFIG_8260_CLKIN == (33 * 1000 * 1000))
-#define CFG_MPTPR MPTPR_PTP_DIV32
-#else
-#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
-#define CFG_MPTPR MPTPR_PTP_DIV32
+/*Note: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_ETHADDR 00:01:af:07:9b:8a
+ #define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
+ #define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
#endif
-#define CFG_PSRT 14
-
-
-/* Bank 4 - On board SDRAM
- *
- * This is not implemented yet.
- */
-
-/*-----------------------------------------------------------------------
- * BR6 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR6 - Option Register
- * Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 6 - On board FLASH
- *
- * This expects the on board FLASH SIMM to be connected to *CS6
- * It consists of 1 AM29F016A part.
- */
-#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
-/* BR6 is configured as follows:
- *
- * - Base address of 0x60000000
- * - 8 bit port size
- * - Data errors checking is disabled
- * - Read and write access
- * - GPCM 60x bus
- * - Access are handled by the memory controller according to MSEL
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- */
-# define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-/* OR6 is configured as follows:
- *
- * - 2 MB
- * - *BCTL0 is asserted upon access to the current memory bank
- * - *CW / *WE are negated a quarter of a clock earlier
- * - *CS is output at the same time as the address lines
- * - Uses a clock cycle length of 5
- * - *PSDVAL is generated internally by the memory controller
- * unless *GTA is asserted earlier externally.
- * - Relaxed timing is generated by the GPCM for accesses
- * initiated to this memory region.
- * - One idle clock is inserted between a read access from the
- * current bank and the next access.
- */
-# define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_TRLX |\
- ORxG_EHTR)
-#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
-
-/*-----------------------------------------------------------------------
- * BR7 - Base Register
- * Ref: Section 10.3.1 on page 10-14
- * OR7 - Option Register
- * Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 7 - LEDs and switches
- *
- * LEDs are at 0x00001 (write only)
- * switches are at 0x00001 (read only)
- */
-#ifdef CFG_LED_BASE
-
-/* BR7 is configured as follows:
- *
- * - Base address of 0xA0000000
- * - 8 bit port size
- * - Data errors checking is disabled
- * - Read and write access
- * - GPCM 60x bus
- * - Access are handled by the memory controller according to MSEL
- * - Not used for atomic operations
- * - No data pipelining is done
- * - Valid
- */
-# define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
-
-/* OR7 is configured as follows:
- *
- * - 1 byte
- * - *BCTL0 is asserted upon access to the current memory bank
- * - *CW / *WE are negated a quarter of a clock earlier
- * - *CS is output at the same time as the address lines
- * - Uses a clock cycle length of 15
- * - *PSDVAL is generated internally by the memory controller
- * unless *GTA is asserted earlier externally.
- * - Relaxed timing is generated by the GPCM for accesses
- * initiated to this memory region.
- * - One idle clock is inserted between a read access from the
- * current bank and the next access.
- */
-# define CFG_OR7_PRELIM (ORxG_AM_MSK |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_15_CLK |\
- ORxG_TRLX |\
- ORxG_EHTR)
-#endif /* CFG_LED_BASE */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SERVERIP 192.168.0.131
+#define CONFIG_IPADDR 192.168.0.105
+#define CONFIG_GATEWAYIP 0.0.0.0
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_HOSTNAME SBC8560
+#define CONFIG_ROOTPATH /home/ppc
+#define CONFIG_BOOTFILE pImage
#endif /* __CONFIG_H */
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