diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/MPC8260ADS.h | 98 |
1 files changed, 95 insertions, 3 deletions
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 98a063a..61a1c27 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -13,6 +13,10 @@ * Ported to PQ2FADS-ZU and PQ2FADS-VR boards. * Ported to MPC8272ADS board. * + * Copyright (c) 2005 MontaVista Software, Inc. + * Vitaly Bordug <vbordug@ru.mvista.com> + * Added support for PCI bridge on MPC8272ADS + * * See file CREDITS for list of people who contributed to this * project. * @@ -173,6 +177,15 @@ #endif #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ +/*PCI*/ +#ifdef CONFIG_MPC8272 +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_BOOTDELAY 0 +#define CONFIG_PCI_SCAN_SHOW +#endif + + #ifndef CONFIG_SDRAM_PBI #define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */ #endif @@ -205,7 +218,6 @@ CFG_CMD_KGDB | \ CFG_CMD_MMC | \ CFG_CMD_NAND | \ - CFG_CMD_PCI | \ CFG_CMD_PCMCIA | \ CFG_CMD_REISER | \ CFG_CMD_SCSI | \ @@ -216,14 +228,21 @@ CFG_CMD_VFD | \ CFG_CMD_XIMG -#if CONFIG_ADSTYPE >= CFG_PQ2FADS +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_SDRAM | \ + CFG_CMD_I2C | \ + CFG_EXCLUDE ) ) +#elif CONFIG_ADSTYPE >= CFG_PQ2FADS #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ CFG_CMD_SDRAM | \ CFG_CMD_I2C | \ + CFG_CMD_PCI | \ CFG_EXCLUDE ) ) #else #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_EXCLUDE ) ) + CMD_CFG_PCI | \ + CFG_EXCLUDE ) ) #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -295,6 +314,9 @@ #define CFG_IMMR 0xF0000000 #define CFG_BCSR 0xF4500000 +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CFG_PCI_INT 0xF8200000 +#endif #define CFG_SDRAM_BASE 0x00000000 #define CFG_LSDRAM_BASE 0xFD000000 @@ -385,6 +407,13 @@ #define CFG_BR1_PRELIM CFG_BCSR | 0x00001801 #define CFG_OR1_PRELIM 0xFFFF8010 +/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/ + +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CFG_BR3_PRELIM (CFG_PCI_INT | 0x1801) /* PCI interrupt controller */ +#define CFG_OR3_PRELIM 0xFFFF8010 +#endif + #define CFG_RMR RMR_CSRE #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) @@ -417,4 +446,67 @@ #define CFG_RESET_ADDRESS 0x04400000 +#if CONFIG_ADSTYPE == CFG_8272ADS + +/* PCI Memory map (if different from default map */ +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ +#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ +#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ + PICMR_PREFETCH_EN) + +/* + * These are the windows that allow the CPU to access PCI address space. + * All three PCI master windows, which allow the CPU to access PCI + * prefetch, non prefetch, and IO space (see below), must all fit within + * these windows. + */ + + + +/* + * Master window that allows the CPU to access PCI Memory (prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ +#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ +#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL +#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) + +/* + * Master window that allows the CPU to access PCI Memory (non-prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ +#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ +#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL +#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) + +/* + * Master window that allows the CPU to access PCI IO space. + * This window will be setup with the first set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ +#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ +#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL +#define CFG_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ +#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) + + +/* PCIBR0 - for PCI IO*/ +#define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */ +#define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ +/* PCIBR1 - prefetch and non-prefetch regions joined together */ +#define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL +#define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U) + +#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/ + #endif /* __CONFIG_H */ |