7 files changed, 12 insertions, 12 deletions
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index a949454..72f7b3f 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -252,7 +252,7 @@
 #define CFG_PEHLPAR		0xC0
 #define CFG_PUAPAR		0x0F		/* UA0..UA3 = Uart 0 +1 */
 #define CFG_DDRUA		0x05
-#define CFG_PJPAR		0xFF;
+#define CFG_PJPAR		0xFF
 
 /*-----------------------------------------------------------------------
  * CCM configuration
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index d2dcdd2..35f048e 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -156,8 +156,8 @@
  * You should know what you are doing if you make changes here.
  */
 #define CFG_MBAR		0x10000000	/* Register Base Addrs */
-#define CFG_SCR			0x0003;
-#define CFG_SPR			0xffff;
+#define CFG_SCR			0x0003
+#define CFG_SPR			0xffff
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 5cc64c1..1bc877a 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -246,6 +246,6 @@
 #define CFG_PEHLPAR		0xC0
 #define CFG_PUAPAR		0x0F	/* UA0..UA3 = Uart 0 +1 */
 #define CFG_DDRUA		0x05
-#define CFG_PJPAR		0xFF;
+#define CFG_PJPAR		0xFF
 
 #endif				/* _CONFIG_M5282EVB_H */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 09bb87e..30c4243 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -153,12 +153,12 @@
 				| SDRAM_CFG_32_BE )
 				/* 0x43080000 */
 #endif
-#define CFG_SDRAM_CFG2		0x00401000;
+#define CFG_SDRAM_CFG2		0x00401000
 /* set burst length to 8 for 32-bit data path */
 #define CFG_DDR_MODE		( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
 				| ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
 				/* 0x44480632 */
-#define CFG_DDR_MODE_2		0x8000C000;
+#define CFG_DDR_MODE_2		0x8000C000
 
 #define CFG_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 				/*0x02000000*/
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index f818b0f..4650b8d 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -207,7 +207,7 @@
 #define CFG_DDR_MODE		((0x0440 << SDRAM_MODE_ESD_SHIFT) \
 				| (0x0442 << SDRAM_MODE_SD_SHIFT))
 				/* 0x04400442 */ /* DDR400 */
-#define CFG_DDR_MODE2		0x00000000;
+#define CFG_DDR_MODE2		0x00000000
 
 /*
  * Memory test
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 9b729ac..ee5116e 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -262,8 +262,8 @@ from which user programs will be started */
  * ---
  */
 
-#define CFG_SCR			0x0003;
-#define CFG_SPR			0xffff;
+#define CFG_SCR			0x0003
+#define CFG_SPR			0xffff
 
 /* ---
  * Ethernet settings
diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
index 592cef1..6594849 100644
--- a/include/configs/spc1920.h
+++ b/include/configs/spc1920.h
@@ -374,7 +374,7 @@
 #define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
 					       BR_MS_UPMA | \
 					       BR_PS_16 | \
-					       BR_V);
+					       BR_V)
 
 #define CFG_MAMR (MAMR_GPL_A4DIS | \
 		MAMR_RLFA_5X | \
@@ -405,7 +405,7 @@
 					OR_SCY_4_CLK | \
 					OR_TRLX)
 
-#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 
 /*
  * PLD CS5
@@ -420,7 +420,7 @@
 					OR_SCY_0_CLK | \
 					OR_TRLX)
 
-#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 
 /*
  * Internal Definitions