diff options
Diffstat (limited to 'include/configs')
169 files changed, 6897 insertions, 1922 deletions
diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h index 8d21b3f..821efe5 100644 --- a/include/configs/ADCIOP.h +++ b/include/configs/ADCIOP.h @@ -184,7 +184,7 @@ * Cache Configuration */ #define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ -#define CFG_CACHELINE_SIZE 16 /* For IBM 401/403 CPUs */ +#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h index c23fcc7..14d56bf 100644 --- a/include/configs/AMX860.h +++ b/include/configs/AMX860.h @@ -55,8 +55,8 @@ #define CONFIG_BOOTCOMMAND \ "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" /* autoboot command */ #undef CONFIG_BOOTARGS diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h new file mode 100644 index 0000000..ba4b1a2 --- /dev/null +++ b/include/configs/AP1000.h @@ -0,0 +1,249 @@ +/* + * AMIRIX.h: AMIRIX specific config options + * + * Author : Frank Smith (smith at amirix dot com) + * + * Derived from : other configuration header files in this tree + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL) version 2, incorporated herein by + * reference. Drivers based on or derived from this code fall under the GPL + * and must retain the authorship, copyright and this license notice. This + * file is not a complete program and may only be used when the entire + * program is licensed under the GPL. + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#undef DEBUG + +#define CONFIG_405 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ + +#define CONFIG_AP1000 1 /* ...on an AP1000 board */ + +#define CONFIG_PCI 1 + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#define CFG_PROMPT "0> " +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CONFIG_COMMAND_EDIT 1 +#define CONFIG_COMMAND_HISTORY 1 +#define CONFIG_COMPLETE_ADDRESSES 1 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_FLASH_USE_BUFFER_WRITE + +#ifdef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#else +#ifdef CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_IN_NVRAM +#endif +#endif + +#define CONFIG_BAUDRATE 57600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#define CONFIG_BOOTCOMMAND "" /* autoboot command */ + +/* Size (bytes) of interrupt driven serial port buffer. + * Set to 0 to use polling instead of interrupts. + * Setting to 0 will also disable RTS/CTS handshaking. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO + +#define CONFIG_BOOTARGS "console=ttyS0,57600" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_IRQ | \ + CFG_CMD_MVENV | \ + CFG_CMD_PCI | \ + CFG_CMD_PING \ + ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SYS_CLK_FREQ 30000000 + +#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +/* usually: (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) */ +#define CFG_PBSIZE (CFG_CBSIZE+4+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_ALT_MEMTEST 1 +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01000000 /* 4 ... 16 MB in DRAM */ + +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ + +#define CFG_NS16550_CLK 40000000 +#define CFG_DUART_CHAN 0 +#define CFG_NS16550_COM1 (0x4C000000 + 0x1000) +#define CFG_NS16550_COM2 (0x4C800000 + 0x1000) +#define CFG_NS16550_REG_SIZE 4 +#define CFG_NS16550 1 +#define CFG_INIT_CHAN1 1 +#define CFG_INIT_CHAN2 0 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#define CFG_LOAD_ADDR 0x00200000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x20000000 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI 1 +#define CFG_PROGFLASH_BASE CFG_FLASH_BASE +#define CFG_CONFFLASH_BASE 0x24000000 + +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ + +/* BEG ENVIRONNEMENT FLASH */ +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* see README - env sector total size */ +#endif +/* END ENVIRONNEMENT FLASH */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ + +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ +#endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + +/* Configuration Port location */ +#define CONFIG_PORT_ADDR 0xF0000500 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + +#define CFG_INIT_RAM_ADDR 0x400000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + */ +#define SPD_EEPROM_ADDRESS 0x50 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* JFFS2 stuff */ + +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +#define CFG_JFFS2_FIRST_SECTOR 1 + +#define CONFIG_NET_MULTI +#define CONFIG_E1000 + +#define CFG_ETH_DEV_FN 0x0800 +#define CFG_ETH_IOBASE 0x31000000 +#define CFG_ETH_MEMBASE 0x32000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 2b38927..3df99a0 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -49,12 +49,12 @@ #undef CONFIG_BOOTARGS #define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm ffc00000 ffca0000" #define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm ffc00000" #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND @@ -263,7 +263,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) @@ -357,7 +357,7 @@ #define CFG_LCD_MEM CFG_LCD_BIG_MEM #define CFG_LCD_REG CFG_LCD_BIG_REG -#define CFG_LCD_LOGO_MAX_SIZE (1024*1024) +#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20) /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) diff --git a/include/configs/AR405.h b/include/configs/AR405.h index dfa6220..1cd0280 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -204,7 +204,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 8e3f34f..9841893 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -264,7 +264,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h index 9a3acfe..c08b2c3 100644 --- a/include/configs/Alaska8220.h +++ b/include/configs/Alaska8220.h @@ -90,6 +90,7 @@ CFG_CMD_SNTP ) #define CONFIG_NET_MULTI +#define CONFIG_MII /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h index 81c8d59..46bdfa2 100644 --- a/include/configs/BAB7xx.h +++ b/include/configs/BAB7xx.h @@ -59,8 +59,8 @@ #define CONFIG_BOOTCOMMAND \ "bootp 1000000; " \ "setenv bootargs root=ramfs console=ttyS00,9600 " \ - "ip=$(ipaddr):$(serverip):$(rootpath):$(gatewayip):" \ - "$(netmask):$(hostname):eth0:none; " \ + "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \ + "${netmask}:${hostname}:eth0:none; " \ "bootm" #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index 21bc441..e0262a8 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -171,7 +171,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index 776fce5..ffe89cb 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -409,7 +409,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/CCM.h b/include/configs/CCM.h index 9401db1..e8994ff 100644 --- a/include/configs/CCM.h +++ b/include/configs/CCM.h @@ -59,8 +59,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND "setenv bootargs " \ - "mem=$(mem) " \ - "root=/dev/ram rw ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off " \ + "mem=${mem} " \ + "root=/dev/ram rw ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ "wt_8xx=timeout:3600; " \ "bootm" diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h new file mode 100644 index 0000000..6025886 --- /dev/null +++ b/include/configs/CMS700.h @@ -0,0 +1,393 @@ +/* + * (C) Copyright 2005 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CMS700.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405EP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_VOM405 1 /* ...on a VOM405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_SEND_HOSTNAME ) + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_BSP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_NAND | \ + CFG_CMD_I2C | \ + CFG_CMD_DATE | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +#undef CONFIG_PRAM /* no "protected RAM" */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * RTC stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_RTC_DS1337 +#define CFG_I2C_RTC_ADDR 0x68 + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *----------------------------------------------------------------------- + */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ +#undef CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* test-only */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ +#endif + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) +# define CFG_RAMBOOT 1 +#else +# undef CFG_RAMBOOT +#endif + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +#define CFG_EEPROM_WREN 1 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ +#define CFG_PLD_BASE 0xf0000000 +#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ +#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs -> GPIO + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ +/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ +/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ +/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ +#define CFG_GPIO0_OSRH 0x40000500 /* 0 ... 15 */ +#define CFG_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ +#define CFG_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ +#define CFG_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ +#define CFG_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ +#define CFG_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ +#define CFG_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ + +#define CFG_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ +#define CFG_PLD_RESET (0x80000000 >> 12) /* GPIO12 */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Default speed selection (cpu_plb_opb_ebc) in mhz. + * This value will be set if iic boot eprom is disabled. + */ +#if 0 +#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 +#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 +#endif +#if 0 +#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 +#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 +#endif +#if 1 +#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 +#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h new file mode 100644 index 0000000..56fd9a6 --- /dev/null +++ b/include/configs/CPCI2DP.h @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2005 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ + +#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ + +#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_LOOPW 1 /* enable loopw command */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ + +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */ +#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/ + +#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ +#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xef000000 /* point to internal regs + PB0/1 */ +#define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ + +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +#define CFG_EEPROM_WREN 1 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ +#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 2 (PB0) initialization */ +#define CFG_EBC_PB2AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */ +#define CFG_EBC_PB2CR 0xEF018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (PB1) initialization */ +#define CFG_EBC_PB3AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */ +#define CFG_EBC_PB3CR 0xEF118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ + +#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * GPIO definitions + */ +#define CFG_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */ +#define CFG_SELF_RST (0x80000000 >> 14) /* GPIO14 */ +#define CFG_PB_LED (0x80000000 >> 16) /* GPIO16 */ +#define CFG_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index b159182..efc3ada 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -151,8 +151,8 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ +#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ @@ -256,7 +256,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index d1498ee..1347f2a 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -178,8 +178,8 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ +#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ @@ -306,7 +306,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 29bd3da..9d52815 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -161,8 +161,8 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ +#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ @@ -278,7 +278,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 6673073..946a0fd 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -183,8 +183,8 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ +#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ @@ -309,7 +309,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h index efb27cc..a5bc773 100644 --- a/include/configs/CPCI440.h +++ b/include/configs/CPCI440.h @@ -265,7 +265,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */ +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 8bfd0ee..150e526 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -70,10 +70,12 @@ #define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX" /*#define CFG_HUSH_PARSER*/ -#undef CFG_HUSH_PARSER +#define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_AUTO_COMPLETE 1 + /* Define which ETH port will be used for connecting the network */ #define CFG_ETH_PORT ETH_0 @@ -155,6 +157,18 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CONFIG_USE_CPCIDVI + +#ifdef CONFIG_USE_CPCIDVI +#define CONFIG_VIDEO +#define CONFIG_VIDEO_CT69000 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VIDEO_LOGO +#define CONFIG_I8042_KBD +#define CFG_ISA_IO 0 +#endif + /* * Miscellaneous configurable options */ @@ -401,6 +415,8 @@ #define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) #define CFG_PCI1_IO_SPACE_PCI 0x00000000 +#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE) + #if defined (CONFIG_750CX) #define CFG_PCI_IDSEL 0x0 #else diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index ae54683..93d49f3 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -187,7 +187,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index 09185b1..16a9ea5 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -118,8 +118,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /*----------------------------------------------------------------------- diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h index c50870f..a23d7e5 100644 --- a/include/configs/CPU87.h +++ b/include/configs/CPU87.h @@ -122,8 +122,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /*----------------------------------------------------------------------- diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h index 5ff9b9e..997e1ba 100644 --- a/include/configs/DASA_SIM.h +++ b/include/configs/DASA_SIM.h @@ -183,7 +183,7 @@ * Cache Configuration */ #define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ -#define CFG_CACHELINE_SIZE 16 /* For IBM 401/403 CPUs */ +#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h index e2b4b1d..bd7aff1 100644 --- a/include/configs/DB64360.h +++ b/include/configs/DB64360.h @@ -174,8 +174,8 @@ if we use PCI it has its own MAC addr */ /* ronen - autoboot using tftp */ #if (CONFIG_BOOTDELAY >= 0) #define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ - setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ - ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; " + setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ + ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " #define CONFIG_BOOTARGS "console=ttyS0,115200" @@ -190,8 +190,8 @@ cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ "bootargs_root=root=/dev/nfs rw\0" \ "bootargs_end=:::DB64360:eth0:none \0"\ "ethprime=mv_enet0\0"\ - "standalone=fsload 0x400000 uImage;setenv bootargs $(bootargs) root=/dev/mtdblock/0 rw \ -ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000;\0" + "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ +ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" /* --------------------------------------------------------------------------------------------------------------- */ /* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */ diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h index 5f541bb..4b72e9b 100644 --- a/include/configs/DB64460.h +++ b/include/configs/DB64460.h @@ -112,8 +112,8 @@ /* ronen - autoboot using tftp */ #if (CONFIG_BOOTDELAY >= 0) #define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ - setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ - ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; " + setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ + ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " #define CONFIG_BOOTARGS "console=ttyS0,115200" @@ -128,8 +128,8 @@ cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ "bootargs_root=root=/dev/nfs rw\0" \ "bootargs_end=:::DB64460:eth0:none \0"\ "ethprime=mv_enet0\0"\ - "standalone=fsload 0x400000 uImage;setenv bootargs $(bootargs) root=/dev/mtdblock/0 rw \ -ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000;\0" + "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ +ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" /* --------------------------------------------------------------------------------------------------------------- */ /* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */ diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 6bebaaa..2ae794d 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -232,7 +232,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/DU405.h b/include/configs/DU405.h index a251298..5489a53 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -223,7 +223,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h index e51d058..2c99b4b 100644 --- a/include/configs/ELPPC.h +++ b/include/configs/ELPPC.h @@ -59,8 +59,8 @@ #define CONFIG_BOOTCOMMAND \ "bootp 1000000; " \ "setenv bootargs root=ramfs console=ttyS00,9600 " \ - "ip=$(ipaddr):$(serverip):$(rootpath):$(gatewayip):" \ - "$(netmask):$(hostname):eth0:none; " \ + "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \ + "${netmask}:${hostname}:eth0:none; " \ "bootm" #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h index 5bfdc9b..e73bcec 100644 --- a/include/configs/ELPT860.h +++ b/include/configs/ELPT860.h @@ -68,12 +68,12 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "rootargs=setenv rootpath /tftp/$(ipaddr)\0" \ + "rootargs=setenv rootpath /tftp/${ipaddr}\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):eth0:off panic=1\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:eth0:off panic=1\0" \ "ramboot=tftp 400000 /home/paugaml/pMulti;" \ "run ramargs;bootm\0" \ "nfsboot=tftp 400000 /home/paugaml/uImage;" \ diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index 1643dee..c203aea 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -323,7 +323,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h index 137b1a7..d55eb7d 100644 --- a/include/configs/ETX094.h +++ b/include/configs/ETX094.h @@ -66,12 +66,12 @@ "setenv bootargs root=/dev/ram rw ramdisk_size=4690 " \ "U-Boot_version=U-Boot-1.0.x-Date " \ "panic=1 " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_NFSBOOTCOMMAND \ "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(nfsip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${nfsip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h index 726ab37..1b562d6 100644 --- a/include/configs/FADS823.h +++ b/include/configs/FADS823.h @@ -96,8 +96,8 @@ #define CONFIG_BOOTCOMMAND \ "bootp ;" \ "setenv bootargs console=tty0 console=ttyS0 " \ -"root=/dev/nfs nfsroot=$(serverip):$(rootpath) " \ -"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off ;" \ +"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ +"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \ "bootm" #else #define CONFIG_BOOTDELAY 0 /* autoboot disabled */ diff --git a/include/configs/G2000.h b/include/configs/G2000.h index af96c7c..db42fd0 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -54,19 +54,19 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off\0" \ - "addmisc=setenv bootargs $(bootargs) " \ - "console=ttyS0,$(baudrate) " \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off\0" \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ "panic=1\0" \ "flash_nfs=run nfsargs addip addmisc;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addmisc;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};" \ "run nfsargs addip addmisc;bootm\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=/tftpboot/g2000/pImage\0" \ @@ -321,7 +321,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index 0702c2c..de8f7ae 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -92,8 +92,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /* diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h index ef2cb3a..8c01d97 100644 --- a/include/configs/GENIETV.h +++ b/include/configs/GENIETV.h @@ -96,8 +96,8 @@ #define CONFIG_BOOTCOMMAND \ "bootp; tftp; " \ "setenv bootargs console=tty0 console=ttyS0 " \ -"root=/dev/nfs nfsroot=$(serverip):$(rootpath) " \ -"ip=$(ipaddr):$(serverip):$(gatewayip):$(subnetmask):$(hostname):eth0:off ;" \ +"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ +"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \ "bootm " #else #define CONFIG_BOOTDELAY 0 /* autoboot disabled */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 828592b..131c215 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -2,6 +2,9 @@ * (C) Copyright 2001-2004 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * * See file CREDITS for list of people who contributed to this * project. * @@ -52,6 +55,10 @@ #define CONFIG_PREBOOT "autoupd" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "pciconfighost=1\0" \ + "" + #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_MII 1 /* MII PHY management */ @@ -60,17 +67,48 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ +/* + * Video console + */ +#define CONFIG_VIDEO /* for sm501 video support */ + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_SM501 +#if 0 +#define CONFIG_VIDEO_SM501_32BPP +#else +#define CONFIG_VIDEO_SM501_16BPP +#endif +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN +#define CFG_CONSOLE_IS_IN_ENV +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */ +#define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */ + +#define ADD_BMP_CMD CFG_CMD_BMP +#else +#define ADD_BMP_CMD 0 +#endif /* CONFIG_VIDEO */ + #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ CFG_CMD_DHCP | \ CFG_CMD_PCI | \ CFG_CMD_IRQ | \ CFG_CMD_IDE | \ CFG_CMD_FAT | \ + CFG_CMD_EXT2 | \ CFG_CMD_ELF | \ CFG_CMD_NAND | \ CFG_CMD_I2C | \ + CFG_CMD_DATE | \ CFG_CMD_MII | \ CFG_CMD_PING | \ + ADD_BMP_CMD | \ CFG_CMD_EEPROM ) #define CONFIG_MAC_PARTITION @@ -111,7 +149,7 @@ #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ +#undef CFG_CONSOLE_INFO_QUIET /* print console @ startup */ #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ @@ -140,6 +178,13 @@ #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ /*----------------------------------------------------------------------- + * RTC stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_RTC_DS1338 +#define CFG_I2C_RTC_ADDR 0x68 + +/*----------------------------------------------------------------------- * NAND-FLASH stuff *----------------------------------------------------------------------- */ @@ -263,7 +308,7 @@ #define CFG_FLASH_BASE 0xFFF80000 #define CFG_MONITOR_BASE TEXT_BASE #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */ +#define CFG_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */ #if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) # define CFG_RAMBOOT 1 @@ -294,6 +339,8 @@ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ +#define CFG_EEPROM_WREN 1 + #if 1 /* test-only */ /* CAT24WC08/16... */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ @@ -317,7 +364,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) @@ -362,8 +409,6 @@ #define CFG_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ #define CFG_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ -#define CFG_LCD_LOGO_MAX_SIZE (1024*1024) - /*----------------------------------------------------------------------- * Universal Interrupt Controller (UIC) Setup */ @@ -449,7 +494,8 @@ #define CFG_GPIO0_TCR 0xF7FE0017 #define CFG_LCD_ENDIAN (0x80000000 >> 7) -#define CFG_TOUCH_RST (0x80000000 >> 9) +#define CFG_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ +#define CFG_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */ #define CFG_LCD0_RST (0x80000000 >> 30) #define CFG_LCD1_RST (0x80000000 >> 31) diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h index 6645b8b..7cce876 100644 --- a/include/configs/HMI10.h +++ b/include/configs/HMI10.h @@ -67,16 +67,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/HMI10/uImage\0" \ "kernel_addr=40040000\0" \ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index 0fa5299..eb627e8 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -266,7 +266,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h index fd15b85..35d84ae 100644 --- a/include/configs/IAD210.h +++ b/include/configs/IAD210.h @@ -71,8 +71,8 @@ #undef CONFIG_BOOTARGS /* #define CONFIG_BOOTCOMMAND \ "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" */ @@ -88,6 +88,7 @@ # undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ # define CONFIG_FEC_ENET 1 /* use FEC ethernet */ +# define CONFIG_MII 1 # define CFG_DISCOVER_PHY 1 # define CONFIG_FEC_UTOPIA 1 # define CONFIG_ETHADDR 08:00:06:26:A2:6D diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h index b0c8ac6..cd17935 100644 --- a/include/configs/ICU862.h +++ b/include/configs/ICU862.h @@ -73,8 +73,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -85,6 +85,7 @@ #undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ #define CONFIG_FEC_ENET 1 /* use FEC ethernet */ +#define CONFIG_MII 1 #if 1 #define CFG_DISCOVER_PHY 1 #else diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index 729b048..aaa44c5 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -50,17 +50,17 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw " \ "console=ttyS0,115200\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_82xx\0" \ "bootfile=/tftpboot/IDS8247/uImage\0" \ "kernel_addr=ff800000\0" \ diff --git a/include/configs/IP860.h b/include/configs/IP860.h index aa2243f..0e20e56 100644 --- a/include/configs/IP860.h +++ b/include/configs/IP860.h @@ -42,13 +42,13 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \ -"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 $(filesize)\0" +"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0" #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 6a9a05d..afba5c6 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -71,6 +71,7 @@ #define CFG_XLB_PIPELINING 1 #define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 #define CONFIG_EEPRO100 1 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 @@ -79,6 +80,7 @@ #else /* MPC5100 */ +#define CONFIG_MII 1 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ #endif @@ -138,16 +140,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_82xx\0" \ "bootfile=/tftpboot/MPC5200/uImage\0" \ "" diff --git a/include/configs/JSE.h b/include/configs/JSE.h index 2257ab2..ccd1f19 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -135,16 +135,16 @@ #define CONFIG_PHY_ADDR 1 /* PHY address */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_FLASH | \ - CFG_CMD_NET | \ CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_MII | \ CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ CFG_CMD_FAT | \ - CFG_CMD_ELF ) + CFG_CMD_FLASH | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_PCI | \ + CFG_CMD_PING ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -269,7 +269,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 331131a..7bbceb0 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -166,6 +166,7 @@ #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 #define CONFIG_HAS_ETH3 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ #define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ #define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ @@ -277,7 +278,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h index 3457770..9b950fc 100644 --- a/include/configs/KUP4K.h +++ b/include/configs/KUP4K.h @@ -61,16 +61,16 @@ "run addhw; diskboot 200000 2:1; bootm 200000\0" \ "nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0" \ "panic_boot=echo No Bootdevice !!! reset\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \ +"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ -"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip)" \ - ":$(netmask):$(hostname):$(netdev):off\0" \ -"addhw=setenv bootargs $(bootargs) hw=$(hw) key1=$(key1) panic=1\0" \ +"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \ + ":${netmask}:${hostname}:${netdev}:off\0" \ +"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \ "netdev=eth0\0" \ "contrast=55\0" \ "silent=1\0" \ "load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \ -"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 $(filesize);" \ +"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};" \ "cp.b 200000 40050000 14000\0" #define CONFIG_BOOTCOMMAND \ @@ -141,6 +141,7 @@ #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ #define CFG_DISCOVER_PHY +#define CONFIG_MII #if 0 #define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */ diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h index 5bad824..cd38b0f 100644 --- a/include/configs/KUP4X.h +++ b/include/configs/KUP4X.h @@ -72,15 +72,15 @@ usb stop; bootm 200000\0" \ "nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \ "panic_boot=echo No Bootdevice !!! reset\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \ +"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ -"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip)" \ - ":$(netmask):$(hostname):$(netdev):off\0" \ -"addhw=setenv bootargs $(bootargs) hw=$(hw) key1=$(key1) panic=1\0" \ +"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \ + ":${netmask}:${hostname}:${netdev}:off\0" \ +"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \ "netdev=eth0\0" \ "silent=1\0" \ "load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \ -"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 $(filesize);" \ +"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};" \ "cp.b 200000 40040000 14000\0" #define CONFIG_BOOTCOMMAND \ @@ -150,6 +150,7 @@ #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ #define CFG_DISCOVER_PHY +#define CONFIG_MII #if 0 #define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */ diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h index 933a42c..e44f1cc 100644 --- a/include/configs/LANTEC.h +++ b/include/configs/LANTEC.h @@ -86,6 +86,7 @@ #define CONFIG_CMD_FULL (CFG_CMD_ALL & ~CFG_CMD_BEDBUG \ & ~CFG_CMD_BMP \ & ~CFG_CMD_BSP \ + & ~CFG_CMD_DISPLAY \ & ~CFG_CMD_DOC \ & ~CFG_CMD_DTT \ & ~CFG_CMD_EEPROM \ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 2b4a33f..b965571 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -230,6 +230,7 @@ #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 #define CONFIG_HAS_ETH3 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ #define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ #define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ @@ -345,7 +346,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h index cd21c2d..53684ca 100644 --- a/include/configs/MHPC.h +++ b/include/configs/MHPC.h @@ -58,8 +58,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 6c2f17d..db2147b 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -257,7 +257,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 0x4000 /* For IBM 405GPr CPUs */ +#define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/ML2.h b/include/configs/ML2.h index 6e54d71..d8805ea 100644 --- a/include/configs/ML2.h +++ b/include/configs/ML2.h @@ -193,7 +193,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 9188ae5..6195bca 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -13,6 +13,10 @@ * Ported to PQ2FADS-ZU and PQ2FADS-VR boards. * Ported to MPC8272ADS board. * + * Copyright (c) 2005 MontaVista Software, Inc. + * Vitaly Bordug <vbordug@ru.mvista.com> + * Added support for PCI bridge on MPC8272ADS + * * See file CREDITS for list of people who contributed to this * project. * @@ -48,10 +52,9 @@ * Figure out if we are booting low via flash HRCW or high via the BCSR. */ #if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */ -# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT 1 #endif - /* ADS flavours */ #define CFG_8260ADS 1 /* MPC8260ADS */ #define CFG_8266ADS 2 /* MPC8266ADS */ @@ -143,7 +146,7 @@ #define CFG_MDIO_PIN 0x00002000 /* PC18 */ #define CFG_MDC_PIN 0x00001000 /* PC19 */ #else -#define CFG_MDIO_PIN 0x00400000 /* PC9 */ +#define CFG_MDIO_PIN 0x00400000 /* PC9 */ #define CFG_MDC_PIN 0x00200000 /* PC10 */ #endif /* CONFIG_ADSTYPE == CFG_8272ADS */ @@ -169,12 +172,20 @@ #define CFG_I2C_SLAVE 0x7F #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR) -#define CONFIG_SPD_ADDR 0x50 +#define CONFIG_SPD_ADDR 0x50 #endif #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ +/*PCI*/ +#ifdef CONFIG_MPC8272 +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_BOOTDELAY 0 +#define CONFIG_PCI_SCAN_SHOW +#endif + #ifndef CONFIG_SDRAM_PBI -#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */ +#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */ #endif #ifndef CONFIG_8260_CLKIN @@ -187,16 +198,17 @@ #define CONFIG_BAUDRATE 115200 -#define CFG_EXCLUDE CFG_CMD_BEDBUG | \ +#define CFG_EXCLUDE CFG_CMD_BEDBUG | \ CFG_CMD_BMP | \ CFG_CMD_BSP | \ CFG_CMD_DATE | \ + CFG_CMD_DISPLAY | \ CFG_CMD_DOC | \ CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ CFG_CMD_EXT2 | \ - CFG_CMD_FAT | \ + CFG_CMD_FAT | \ CFG_CMD_FDC | \ CFG_CMD_FDOS | \ CFG_CMD_HWFLOW | \ @@ -204,8 +216,7 @@ CFG_CMD_KGDB | \ CFG_CMD_MMC | \ CFG_CMD_NAND | \ - CFG_CMD_PCI | \ - CFG_CMD_PCMCIA | \ + CFG_CMD_PCMCIA | \ CFG_CMD_REISER | \ CFG_CMD_SCSI | \ CFG_CMD_SPI | \ @@ -215,14 +226,21 @@ CFG_CMD_VFD | \ CFG_CMD_XIMG -#if CONFIG_ADSTYPE >= CFG_PQ2FADS +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_SDRAM | \ + CFG_CMD_I2C | \ + CFG_EXCLUDE ) ) +#elif CONFIG_ADSTYPE >= CFG_PQ2FADS #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ CFG_CMD_SDRAM | \ CFG_CMD_I2C | \ + CFG_CMD_PCI | \ CFG_EXCLUDE ) ) #else #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_EXCLUDE ) ) + CMD_CFG_PCI | \ + CFG_EXCLUDE ) ) #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -241,7 +259,7 @@ #endif #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ /* * Miscellaneous configurable options @@ -294,6 +312,9 @@ #define CFG_IMMR 0xF0000000 #define CFG_BCSR 0xF4500000 +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CFG_PCI_INT 0xF8200000 +#endif #define CFG_SDRAM_BASE 0x00000000 #define CFG_LSDRAM_BASE 0xFD000000 @@ -311,7 +332,6 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - #ifdef CFG_LOWBOOT /* PQ2FADS flash HRCW = 0x0EB4B645 */ #define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ @@ -363,13 +383,11 @@ # define CFG_ENV_SIZE 0x200 #endif /* CFG_RAMBOOT */ - #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif - #define CFG_HID0_INIT 0 #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) @@ -384,6 +402,13 @@ #define CFG_BR1_PRELIM CFG_BCSR | 0x00001801 #define CFG_OR1_PRELIM 0xFFFF8010 +/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/ + +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CFG_BR3_PRELIM (CFG_PCI_INT | 0x1801) /* PCI interrupt controller */ +#define CFG_OR3_PRELIM 0xFFFF8010 +#endif + #define CFG_RMR RMR_CSRE #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) @@ -416,4 +441,69 @@ #define CFG_RESET_ADDRESS 0x04400000 +#if CONFIG_ADSTYPE == CFG_8272ADS + +/* PCI Memory map (if different from default map */ +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ +#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ +#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ + PICMR_PREFETCH_EN) + +/* + * These are the windows that allow the CPU to access PCI address space. + * All three PCI master windows, which allow the CPU to access PCI + * prefetch, non prefetch, and IO space (see below), must all fit within + * these windows. + */ + +/* + * Master window that allows the CPU to access PCI Memory (prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ +#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ +#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL +#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) + +/* + * Master window that allows the CPU to access PCI Memory (non-prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ +#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ +#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL +#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) + +/* + * Master window that allows the CPU to access PCI IO space. + * This window will be setup with the first set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ +#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ +#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL +#define CFG_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ +#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) + + +/* PCIBR0 - for PCI IO*/ +#define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */ +#define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ +/* PCIBR1 - prefetch and non-prefetch regions joined together */ +#define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL +#define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U) + +#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/ + +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CONFIG_HAS_ETH1 +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index 0a4b04d..4953b70 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -31,13 +31,13 @@ */ /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - !! !! + !! !! !! This configuration requires JP3 to be in position 1-2 to work !! - !! To make it work for the default, the TEXT_BASE define in !! + !! To make it work for the default, the TEXT_BASE define in !! !! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !! !! 0xfff00000 !! !! The CFG_HRCW_MASTER define below must also be changed to match !! - !! !! + !! !! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */ @@ -139,23 +139,24 @@ * Definitions for Serial Presence Detect EEPROM address * (to get SDRAM settings) */ -#define SPD_EEPROM_ADDRESS 0x50 +#define SPD_EEPROM_ADDRESS 0x50 #define CONFIG_8260_CLKIN 66000000 /* in Hz */ #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS ( CFG_CMD_ALL & ~( \ - CFG_CMD_BEDBUG | \ +#define CONFIG_COMMANDS ( CFG_CMD_ALL & ~( \ + CFG_CMD_BEDBUG | \ CFG_CMD_BMP | \ CFG_CMD_BSP | \ CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ + CFG_CMD_DHCP | \ + CFG_CMD_DISPLAY | \ CFG_CMD_DOC | \ CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ CFG_CMD_EXT2 | \ CFG_CMD_FDC | \ CFG_CMD_FDOS | \ @@ -165,7 +166,7 @@ CFG_CMD_KGDB | \ CFG_CMD_MMC | \ CFG_CMD_NAND | \ - CFG_CMD_PCMCIA | \ + CFG_CMD_PCMCIA | \ CFG_CMD_REISER | \ CFG_CMD_SCSI | \ CFG_CMD_SPI | \ @@ -178,8 +179,8 @@ /* Define a command string that is automatically executed when no character * is read on the console interface withing "Boot Delay" after reset. */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ -#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ +#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ +#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ #ifdef CONFIG_BOOT_ROOT_INITRD #define CONFIG_BOOTCOMMAND \ @@ -187,7 +188,7 @@ "echo;" \ "bootp;" \ "setenv bootargs root=/dev/ram0 rw " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" #endif /* CONFIG_BOOT_ROOT_INITRD */ @@ -196,8 +197,8 @@ "version;" \ "echo;" \ "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" #endif /* CONFIG_BOOT_ROOT_NFS */ @@ -457,7 +458,7 @@ /*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 + * HIDx - Hardware Implementation-dependent Registers 2-11 *----------------------------------------------------------------------- * HID0 also contains cache control - initially enable both caches and * invalidate contents, then the final state leaves only the instruction @@ -489,7 +490,7 @@ * 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window * 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window * 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory - * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window + * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window * 0xF8000000-0xF8007FFF 32KB BCSR * 0xF8100000-0xF8107FFF 32KB ATM UNI * 0xF8200000-0xF8207FFF 32KB PCI interrupt controller @@ -543,10 +544,10 @@ * in the bridge. */ -#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ -#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ -#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL -#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ +#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ +#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ +#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL +#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ #define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) /* @@ -555,11 +556,11 @@ * in the bridge. */ -#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ -#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ -#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL -#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ -#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) +#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ +#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ +#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL +#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) /* * Master window that allows the CPU to access PCI IO space. @@ -567,11 +568,11 @@ * in the bridge. */ -#define CFG_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */ -#define CFG_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */ -#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL -#define CFG_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */ -#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO) +#define CFG_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */ +#define CFG_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */ +#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL +#define CFG_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */ +#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO) /* * JFFS2 partitions diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index db878cb..2d5031b 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -43,7 +43,9 @@ #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_TSEC_ENET /* tsec ethernet support */ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ diff --git a/include/configs/MPC885ADS.h b/include/configs/MPC885ADS.h index 7f0b06a..74318e5 100644 --- a/include/configs/MPC885ADS.h +++ b/include/configs/MPC885ADS.h @@ -42,4 +42,6 @@ #define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ #define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) +#define CONFIG_HAS_ETH1 + #endif /* __CONFIG_H */ diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h index 32f9e91..88eefa1 100644 --- a/include/configs/MVBLUE.h +++ b/include/configs/MVBLUE.h @@ -111,9 +111,9 @@ "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \ "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \ "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" \ - "addcons=setenv bootargs $(bootargs) console=ttyS$(console_nr),$(baudrate)N8\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ + "addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \ "mv_version=" MV_VERSION "\0" \ "bootretry=30\0" diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h index 49bdc45..5995918 100644 --- a/include/configs/MVS1.h +++ b/include/configs/MVS1.h @@ -50,8 +50,8 @@ #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" #define CONFIG_BOOTCOMMAND \ "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/NC650.h b/include/configs/NC650.h index d24d05f..371ea17 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -71,8 +71,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -99,19 +99,17 @@ #define SCL 0x1000 /* PA 3 */ #define SDA 0x2000 /* PA 2 */ -#define PAR immr->im_ioport.iop_papar -#define DIR immr->im_ioport.iop_padir -#define DAT immr->im_ioport.iop_padat - -#define I2C_INIT {PAR &= ~(SCL | SDA); DIR |= SCL;} -#define I2C_ACTIVE (DIR |= SDA) -#define I2C_TRISTATE (DIR &= ~SDA) -#define I2C_READ ((DAT & SDA) != 0) -#define I2C_SDA(bit) if (bit) DAT |= SDA; \ - else DAT &= ~SDA -#define I2C_SCL(bit) if (bit) DAT |= SCL; \ - else DAT &= ~SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#define __I2C_DIR immr->im_ioport.iop_padir +#define __I2C_DAT immr->im_ioport.iop_padat +#define __I2C_PAR immr->im_ioport.iop_papar +#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \ + __I2C_DIR |= (SDA|SCL); } +#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0) +#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; } +#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; } +#define I2C_DELAY { udelay(5); } +#define I2C_ACTIVE { __I2C_DIR |= SDA; } +#define I2C_TRISTATE { __I2C_DIR &= ~SDA; } #define CONFIG_RTC_PCF8563 #define CFG_I2C_RTC_ADDR 0x51 diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h index db86cf3..d994420 100644 --- a/include/configs/NSCU.h +++ b/include/configs/NSCU.h @@ -56,16 +56,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/NSCU/uImage\0" \ "kernel_addr=40080000\0" \ diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 4a629e0..aa9d1ba 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -213,7 +213,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index 4cc67bc..2e7c505 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -211,7 +211,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h index 7d6bbf5..a933e1b 100644 --- a/include/configs/P3G4.h +++ b/include/configs/P3G4.h @@ -90,17 +90,17 @@ "netdev=eth0\0" \ "hostname=p3g4\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ "flash_nfs=run nfsargs addip addtty;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ "rootpath=/opt/eldk/ppc_74xx\0" \ "bootfile=/tftpboot/p3g4/uImage\0" \ @@ -108,7 +108,7 @@ "ramdisk_addr=ff010000\0" \ "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \ "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ - "cp.b 100000 fff00000 $(filesize);" \ + "cp.b 100000 fff00000 ${filesize};" \ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ "" diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 469d88f..9d5c4f4 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -241,7 +241,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 9ac5715..9668fb0 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -224,7 +224,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 7ee95df..54ecfa4 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -330,7 +330,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/PM520.h b/include/configs/PM520.h index 49ae55c..e73ad51 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -72,6 +72,7 @@ #define CONFIG_PCI_IO_SIZE 0x01000000 #define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 #define CONFIG_EEPRO100 1 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #undef CONFIG_NS8382X @@ -137,16 +138,16 @@ "netdev=eth0\0" \ "hostname=pm520\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk30/ppc_82xx\0" \ "bootfile=/tftpboot/PM520/uImage\0" \ "" @@ -199,12 +200,13 @@ * Flash configuration (8,16 or 32 MB) * TEXT base always at 0xFFF00000 * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFC000000 for 32 MB + * FLASH_BASE at 0xFA000000 for 64 MB + * 0xFC000000 for 32 MB * 0xFD000000 for 16 MB * 0xFD800000 for 8 MB */ -#define CFG_FLASH_BASE 0xfc000000 -#define CFG_FLASH_SIZE 0x02000000 +#define CFG_FLASH_BASE 0xFA000000 +#define CFG_FLASH_SIZE 0x04000000 #define CFG_BOOTROM_BASE 0xFFF00000 #define CFG_BOOTROM_SIZE 0x00080000 #define CFG_ENV_ADDR (0xFDF00000 + 0x40000) @@ -213,17 +215,18 @@ * Flash configuration (8,16 or 32 MB) * TEXT base always at 0xFFF00000 * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFE000000 for 32 MB + * FLASH_BASE at 0xFC000000 for 64 MB + * 0xFE000000 for 32 MB * 0xFF000000 for 16 MB * 0xFF800000 for 8 MB */ -#define CFG_FLASH_BASE 0xfe000000 -#define CFG_FLASH_SIZE 0x02000000 +#define CFG_FLASH_BASE 0xFC000000 +#define CFG_FLASH_SIZE 0x04000000 #define CFG_ENV_ADDR (0xFFF00000 + 0x40000) #endif #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ @@ -324,11 +327,11 @@ #define CFG_CS0_SIZE CFG_BOOTROM_SIZE #define CFG_CS1_START CFG_FLASH_BASE #define CFG_CS1_SIZE CFG_FLASH_SIZE -#define CFG_CS1_CFG 0x0004fb00 +#define CFG_CS1_CFG 0x0004FF00 #else #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x0004fb00 +#define CFG_BOOTCS_CFG 0x0004FF00 #define CFG_CS0_START CFG_FLASH_BASE #define CFG_CS0_SIZE CFG_FLASH_SIZE #define CFG_CS1_START CFG_DOC_BASE diff --git a/include/configs/PM826.h b/include/configs/PM826.h index 9ca1e52..6e5e3bb 100644 --- a/include/configs/PM826.h +++ b/include/configs/PM826.h @@ -48,8 +48,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /* enable I2C and select the hardware/software driver */ diff --git a/include/configs/PM828.h b/include/configs/PM828.h index 7d98df5..982a1f8 100644 --- a/include/configs/PM828.h +++ b/include/configs/PM828.h @@ -48,8 +48,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" /* enable I2C and select the hardware/software driver */ diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 89b5f36..da01186 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -235,8 +235,9 @@ #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP +#define CONFIG_EEPRO100 +#define CONFIG_E1000 +#undef CONFIG_TULIP #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 @@ -320,6 +321,7 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_EEPROM \ | CFG_CMD_DATE \ + | CFG_CMD_MII \ | CFG_CMD_PCI \ | CFG_CMD_PING \ | CFG_CMD_I2C) @@ -327,6 +329,7 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_EEPROM \ | CFG_CMD_DATE \ + | CFG_CMD_MII \ | CFG_CMD_PING \ | CFG_CMD_I2C) #endif diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 11d6fa7..6e0bd7f 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -53,9 +53,15 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ CFG_CMD_BSP | \ @@ -154,15 +160,24 @@ #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */ +#define CFG_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID: Non-Monarch */ +#define CFG_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID: Monarch */ +#define CFG_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid() + #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ + +#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ +#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#if 1 +#define CFG_PCI_PTM2LA 0xef000000 /* point to internal regs */ +#define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ +#else /* old mapping */ #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - +#endif /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) @@ -183,14 +198,17 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#undef CFG_FLASH_PROTECTION /* don't use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_FLASH_BASE 0xFE000000 #define CFG_FLASH_INCREMENT 0x01000000 +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_PROTECTION 1 /* don't use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + CFG_FLASH_INCREMENT } +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ /* @@ -200,8 +218,8 @@ /* No command line, one static partition, whole device */ #undef CONFIG_JFFS2_CMDLINE #define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 +#define CONFIG_JFFS2_PART_SIZE 0x01b00000 +#define CONFIG_JFFS2_PART_OFFSET 0x00400000 /* mtdparts command line support */ /* Note: fake mtd_id used, no linux mtd map file */ @@ -242,7 +260,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) @@ -256,7 +274,7 @@ #define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ #define CAN_BA 0xF0000000 /* CAN Base Address */ #define RTC_BA 0xF0000500 /* RTC Base Address */ -#define CF_BA 0xF0100000 /* CompactFlash Base Address */ +#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */ /* Memory Bank 0 (Flash Bank 0) initialization */ #define CFG_EBC_PB0AP 0x92015480 @@ -270,9 +288,11 @@ #define CFG_EBC_PB2AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ #define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */ -#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ +/* Memory Bank 3 -> unused */ + +/* Memory Bank 4 (NVRAM) initialization */ +#define CFG_EBC_PB4AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ +#define CFG_EBC_PB4CR NVRAM_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ /*----------------------------------------------------------------------- * FPGA stuff @@ -290,6 +310,15 @@ #define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ /*----------------------------------------------------------------------- + * GPIOs + */ +#define CFG_NONMONARCH (0x80000000 >> 14) /* GPIO24 */ +#define CFG_XEREADY (0x80000000 >> 15) /* GPIO15 */ +#define CFG_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */ +#define CFG_SELF_RST (0x80000000 >> 21) /* GPIO21 */ +#define CFG_REV1_2 (0x80000000 >> 23) /* GPIO23 */ + +/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) */ diff --git a/include/configs/PN62.h b/include/configs/PN62.h index 5f748a0..a717659 100644 --- a/include/configs/PN62.h +++ b/include/configs/PN62.h @@ -68,8 +68,8 @@ #define CONFIG_BOOTCOMMAND \ "setenv verify y;" \ "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ - "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip)::$(netmask):pn62:eth0:off;" \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ "loadp 100000; bootm" /* "tftpboot 100000 uImage; bootm" */ #else @@ -78,7 +78,7 @@ "setenv verify n;" \ "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ "root=/dev/ram rw " \ - "ip=$(ipaddr):$(serverip)::$(netmask):pn62:eth0:off;" \ + "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ "loadp 200000; bootm" #endif diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 2d89f3f..c406c8f 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -188,10 +188,14 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ + +/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */ +#define CONFIG_NEW_NAND_CODE #define CFG_NAND0_BASE 0xFF400000 #define CFG_NAND1_BASE 0xFF000000 - -#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, CFG_NAND1_BASE } +#define NAND_BIG_DELAY_US 25 +#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ #define SECTORSIZE 512 #define NAND_NO_RB @@ -213,6 +217,83 @@ #define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ #define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ +#ifdef CONFIG_NEW_NAND_CODE +#define MACRO_NAND_DISABLE_CE(nandptr) do \ +{ \ + switch((unsigned long)nandptr) \ + { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \ + break; \ + } \ +} while(0) + +#define MACRO_NAND_ENABLE_CE(nandptr) do \ +{ \ + switch((unsigned long)nandptr) \ + { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \ + break; \ + } \ +} while(0) + +#define MACRO_NAND_CTL_CLRALE(nandptr) do \ +{ \ + switch((unsigned long)nandptr) \ + { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \ + break; \ + } \ +} while(0) + +#define MACRO_NAND_CTL_SETALE(nandptr) do \ +{ \ + switch((unsigned long)nandptr) \ + { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \ + break; \ + } \ +} while(0) + +#define MACRO_NAND_CTL_CLRCLE(nandptr) do \ +{ \ + switch((unsigned long)nandptr) \ + { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \ + break; \ + } \ +} while(0) + +#define MACRO_NAND_CTL_SETCLE(nandptr) do { \ + switch((unsigned long)nandptr) { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \ + break; \ + } \ +} while(0) +#else #define NAND_DISABLE_CE(nand) do \ { \ switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ @@ -288,6 +369,7 @@ break; \ } \ } while(0) +#endif /* !CONFIG_NEW_NAND_CODE */ #ifdef NAND_NO_RB /* constant delay (see also tR in the datasheet) */ @@ -338,16 +420,16 @@ #define CFG_SDRAM_BASE 0x00000000 /* Reserve 256 kB for Monitor */ +/* #define CFG_FLASH_BASE 0xFFFC0000 #define CFG_MONITOR_BASE CFG_FLASH_BASE #define CFG_MONITOR_LEN (256 * 1024) +*/ /* Reserve 320 kB for Monitor */ -/* #define CFG_FLASH_BASE 0xFFFB0000 #define CFG_MONITOR_BASE CFG_FLASH_BASE #define CFG_MONITOR_LEN (320 * 1024) -*/ #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ @@ -422,7 +504,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h index 8d29a31..32faa61 100644 --- a/include/configs/QS860T.h +++ b/include/configs/QS860T.h @@ -56,6 +56,7 @@ #define CONFIG_QS860T 1 /* ...on a QS860T module */ #define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */ +#define CONFIG_MII #define FEC_INTERRUPT SIU_LEVEL1 #undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */ #define CFG_DISCOVER_PHY @@ -78,8 +79,8 @@ #undef CONFIG_BOOTARGS /* TODO compare against CADM860 */ #define CONFIG_BOOTCOMMAND "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h index d7b093b..82228c0 100644 --- a/include/configs/R360MPI.h +++ b/include/configs/R360MPI.h @@ -63,8 +63,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #undef CONFIG_SCC1_ENET diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index 4d47d3e..242c837 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -66,8 +66,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -97,6 +97,7 @@ #define CONFIG_COMMANDS ( CFG_CMD_ALL & \ ~CFG_CMD_BSP & \ ~CFG_CMD_DATE & \ + ~CFG_CMD_DISPLAY& \ ~CFG_CMD_DTT & \ ~CFG_CMD_EXT2 & \ ~CFG_CMD_FDC & \ diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h index 7294561..591382c 100644 --- a/include/configs/RPXClassic.h +++ b/include/configs/RPXClassic.h @@ -79,8 +79,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h index 04293f3..6b65031 100644 --- a/include/configs/RPXlite.h +++ b/include/configs/RPXlite.h @@ -58,8 +58,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h index ea01bc4..8cd7df1 100644 --- a/include/configs/RPXlite_DW.h +++ b/include/configs/RPXlite_DW.h @@ -83,25 +83,25 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \ - "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "gatewayip=172.16.115.254\0" \ "netmask=255.255.255.0\0" \ "kernel_addr=ff040000\0" \ "ramdisk_addr=ff200000\0" \ - "ku=era $(kernel_addr) ff1fffff;cp.b 100000 $(kernel_addr) " \ - "$(filesize);md $(kernel_addr);" \ + "ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} " \ + "${filesize};md ${kernel_addr};" \ "echo kernel updating finished\0" \ "uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \ - "$(filesize);md ff000000;" \ + "${filesize};md ff000000;" \ "echo u-boot updating finished\0" \ "eu=protect off 1:6;era 1:6;reset\0" \ "lcd=setenv stdout lcd;setenv stdin lcd\0" \ diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h index 7f2c8a4..3885bcd 100644 --- a/include/configs/RRvision.h +++ b/include/configs/RRvision.h @@ -65,22 +65,22 @@ "netdev=eth0\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip)" \ - ":$(gatewayip):$(netmask):$(hostname):$(netdev):off\0" \ - "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "nfsroot=${serverip}:${rootpath}\0" \ + "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}" \ + ":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ "load=tftp 100000 /tftpboot/u-boot.bin\0" \ "update=protect off 1:0-8;era 1:0-8;" \ - "cp.b 100000 40000000 $(filesize);" \ + "cp.b 100000 40000000 ${filesize};" \ "setenv filesize;saveenv\0" \ "kernel_addr=40040000\0" \ "ramdisk_addr=40100000\0" \ "kernel_img=/tftpboot/uImage\0" \ - "kernel_load=tftp 200000 $(kernel_img)\0" \ + "kernel_load=tftp 200000 ${kernel_img}\0" \ "net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \ - "flash_nfs=run nfsargs addip addtty;bootm $(kernel_addr)\0" \ + "flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" + "bootm ${kernel_addr} ${ramdisk_addr}\0" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/SCM.h b/include/configs/SCM.h index 91914e8..e263db6 100644 --- a/include/configs/SCM.h +++ b/include/configs/SCM.h @@ -68,8 +68,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /* enable I2C and select the hardware/software driver */ diff --git a/include/configs/SM850.h b/include/configs/SM850.h index c23b386..4977629 100644 --- a/include/configs/SM850.h +++ b/include/configs/SM850.h @@ -55,8 +55,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h index 9ce83b4..c1c765f 100644 --- a/include/configs/SXNI855T.h +++ b/include/configs/SXNI855T.h @@ -142,6 +142,7 @@ # define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ #define CONFIG_FEC_ENET 1 /* use FEC ethernet */ +#define CONFIG_MII 1 #define CFG_DISCOVER_PHY diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h index 7c4feee..f4339ec 100644 --- a/include/configs/Sandpoint8240.h +++ b/include/configs/Sandpoint8240.h @@ -61,16 +61,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "net_self=tftp $(kernel_addr) $(bootfile);" \ - "tftp $(ramdisk_addr) $(ramdisk);" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "net_self=tftp ${kernel_addr} ${bootfile};" \ + "tftp ${ramdisk_addr} ${ramdisk};" \ "run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp $(kernel_addr) $(bootfile);" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp ${kernel_addr} ${bootfile};" \ "run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_82xx\0" \ "bootfile=/tftpboot/SP8240/uImage\0" \ diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h index e46f5e4..f41dbd0 100644 --- a/include/configs/TOP5200.h +++ b/include/configs/TOP5200.h @@ -167,16 +167,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_82xx\0" \ "bootfile=/tftpboot/MPC5200/uImage\0" \ "" diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h index af74f9d..2344b96 100644 --- a/include/configs/TOP860.h +++ b/include/configs/TOP860.h @@ -181,17 +181,20 @@ #if defined (CONFIG_SOFT_I2C) #define SDA 0x00010 #define SCL 0x00020 -#define DIR immr->im_cpm.cp_pbdir -#define DAT immr->im_cpm.cp_pbdat -#define PAR immr->im_cpm.cp_pbpar -#define ODR immr->im_cpm.cp_pbodr -#define I2C_INIT {PAR&=~(SDA|SCL);ODR&=~(SDA|SCL);DAT|=(SDA|SCL);DIR|=(SDA|SCL);} -#define I2C_READ ((DAT&SDA)?1:0) -#define I2C_SDA(x) {if(x)DAT|=SDA;else DAT&=~SDA;} -#define I2C_SCL(x) {if(x)DAT|=SCL;else DAT&=~SCL;} -#define I2C_DELAY {udelay(5);} -#define I2C_ACTIVE {DIR|=SDA;} -#define I2C_TRISTATE {DIR&=~SDA;} +#define __I2C_DIR immr->im_cpm.cp_pbdir +#define __I2C_DAT immr->im_cpm.cp_pbdat +#define __I2C_PAR immr->im_cpm.cp_pbpar +#define __I2C_ODR immr->im_cpm.cp_pbodr +#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \ + __I2C_ODR &= ~(SDA|SCL); \ + __I2C_DAT |= (SDA|SCL); \ + __I2C_DIR|=(SDA|SCL); } +#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0) +#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; } +#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; } +#define I2C_DELAY { udelay(5); } +#define I2C_ACTIVE { __I2C_DIR |= SDA; } +#define I2C_TRISTATE { __I2C_DIR &= ~SDA; } #endif #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } @@ -401,8 +404,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /* diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index b60e3cd..5ad1939 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -83,7 +83,7 @@ #define CONFIG_PCI_IO_SIZE 0x01000000 #define CONFIG_NET_MULTI 1 -#define CONFIG_EEPRO100 1 +#define CONFIG_EEPRO100 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 #endif /* CONFIG_STK52XX */ @@ -164,12 +164,14 @@ CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ CFG_CMD_MII | \ CFG_CMD_NFS | \ CFG_CMD_PING | \ CFG_CMD_POST_DIAG | \ CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) + CFG_CMD_SNTP | \ + CFG_CMD_BSP) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -206,21 +208,21 @@ "rootpath=/opt/eldk/ppc_6xx\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 $(u-boot)\0" \ + "load=tftp 200000 ${u-boot}\0" \ "u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \ "update=protect off FC000000 FC05FFFF;" \ "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 $(filesize);" \ + "cp.b 200000 FC000000 ${filesize};" \ "protect on FC000000 FC05FFFF\0" \ "" @@ -321,6 +323,15 @@ #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +/* Dynamic MTD partition support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM5200-0" +#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ + "1408k(kernel)," \ + "2m(initrd)," \ + "4m(small-fs)," \ + "16m(big-fs)," \ + "8m(misc)" /* * Environment settings @@ -358,7 +369,7 @@ #endif #define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* @@ -416,7 +427,12 @@ /* * RTC configuration */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ +#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100) +# define CONFIG_RTC_M41T11 1 +# define CFG_I2C_RTC_ADDR 0x68 +#else +# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ +#endif /* * Miscellaneous configurable options diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index d12aabe..b1c70f8 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -58,16 +58,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM823L/uImage\0" \ "kernel_addr=40040000\0" \ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index a838a95..9f958f5 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -58,16 +58,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM823M/uImage\0" \ "kernel_addr=40080000\0" \ diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h index e6266b5..49c3872 100644 --- a/include/configs/TQM8260.h +++ b/include/configs/TQM8260.h @@ -73,16 +73,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_82xx\0" \ "bootfile=/tftpboot/TQM8260/uImage\0" \ "kernel_addr=40040000\0" \ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h new file mode 100644 index 0000000..41f44c5 --- /dev/null +++ b/include/configs/TQM834x.h @@ -0,0 +1,511 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * TQM8349 board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define DEBUG +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC834X 1 /* MPC834X specific */ +#define CONFIG_TQM834X 1 /* TQM834X board specific */ + +/* IMMR Base Addres Register, use Freescale default: 0xff400000 */ +#define CFG_IMMRBAR 0xff400000 + +/* System clock. Primary input clock when in PCI host mode */ +#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ + +/* + * Local Bus LCRR + * LCRR: DLL bypass, Clock divider is 8 + * + * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz + * + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) + +/* board pre init: do not call, nothing to do */ +#undef CONFIG_BOARD_EARLY_INIT_F + +/* detect the number of flash banks */ +#define CONFIG_BOARD_EARLY_INIT_R + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define DDR_CASLAT_25 /* CASLAT set to 2.5 */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 /* memtest region */ +#define CFG_MEMTEST_END 0x00100000 + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_BASE 0x80000000 /* start of FLASH */ + +/* buffered writes in the AMD chip set is not supported yet */ +#undef CFG_FLASH_USE_BUFFER_WRITE + +/* + * FLASH bank number detection + */ + +/* + * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash + * banks has to be determined at runtime and stored in a gloabl variable + * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only + * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and + * should be made sufficiently large to accomodate the number of banks that + * might actually be detected. Since most (all?) Flash related functions use + * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is + * defined as tqm834x_num_flash_banks. + */ +#define CFG_MAX_FLASH_BANKS_DETECT 2 +#ifndef __ASSEMBLY__ +extern int tqm834x_num_flash_banks; +#endif +#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks) + +#define CFG_MAX_FLASH_SECT 512 /* max sectors per device */ + +/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) | \ + BR_MS_GPCM | BR_PS_32 | BR_V) + +/* FLASH timing (0x0000_0c54) */ +#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \ + OR_GPCM_SCY_5 | OR_GPCM_TRLX) + +#define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) + +#define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */ + +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ + +/* disable remaining mappings */ +#define CFG_BR1_PRELIM 0x00000000 +#define CFG_OR1_PRELIM 0x00000000 +#define CFG_LBLAWBAR1_PRELIM 0x00000000 +#define CFG_LBLAWAR1_PRELIM 0x00000000 + +#define CFG_BR2_PRELIM 0x00000000 +#define CFG_OR2_PRELIM 0x00000000 +#define CFG_LBLAWBAR2_PRELIM 0x00000000 +#define CFG_LBLAWAR2_PRELIM 0x00000000 + +#define CFG_BR3_PRELIM 0x00000000 +#define CFG_OR3_PRELIM 0x00000000 +#define CFG_LBLAWBAR3_PRELIM 0x00000000 +#define CFG_LBLAWAR3_PRELIM 0x00000000 + +#define CFG_BR4_PRELIM 0x00000000 +#define CFG_OR4_PRELIM 0x00000000 +#define CFG_LBLAWBAR4_PRELIM 0x00000000 +#define CFG_LBLAWAR4_PRELIM 0x00000000 + +#define CFG_BR5_PRELIM 0x00000000 +#define CFG_OR5_PRELIM 0x00000000 +#define CFG_LBLAWBAR5_PRELIM 0x00000000 +#define CFG_LBLAWAR5_PRELIM 0x00000000 + +#define CFG_BR6_PRELIM 0x00000000 +#define CFG_OR6_PRELIM 0x00000000 +#define CFG_LBLAWBAR6_PRELIM 0x00000000 +#define CFG_LBLAWAR6_PRELIM 0x00000000 + +#define CFG_BR7_PRELIM 0x00000000 +#define CFG_OR7_PRELIM 0x00000000 +#define CFG_LBLAWBAR7_PRELIM 0x00000000 +#define CFG_LBLAWAR7_PRELIM 0x00000000 + +/* + * Monitor config + */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) +#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) + +/* + * I2C + */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */ +#define CFG_I2C_SLAVE 0x7F /* slave address */ +#define CFG_I2C_OFFSET 0x3000 + +/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ +#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ + +/* I2C RTC */ +#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_MII + +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMRBAR + CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMRBAR + CFG_TSEC2_OFFSET) + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif + +#define CONFIG_MPC83XX_TSEC1 1 +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC83XX_TSEC2 1 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_PCI + +#if defined(CONFIG_PCI) + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +/* PCI1 host bridge */ +#define CFG_PCI1_MEM_BASE 0xc0000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + + +#undef CONFIG_EEPRO100 +#define CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE + #define PCI_ENET0_MEMADDR CFG_PCI1_MEM_BASE + #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ +#endif + +#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* Common commands */ +#define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\ + | CFG_CMD_PING | CFG_CMD_EEPROM \ + | CFG_CMD_MII | CFG_CMD_JFFS2 + +#if defined(CFG_RAMBOOT) + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \ + | CFG_CMD_TQM8349_COMMON) \ + & \ + ~(CFG_CMD_ENV | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_TQM8349_COMMON) \ + & \ + ~(CFG_CMD_ENV | CFG_CMD_LOADS)) +#endif + +#else /* CFG_RAMBOOT */ + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \ + | CFG_CMD_TQM8349_COMMON) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_TQM8349_COMMON) +#endif + +#endif /* CFG_RAMBOOT */ + +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) + +#if defined(PCI_64BIT) +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#endif + +/* i-cache and d-cache disabled */ +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT +#define CFG_HID2 0x000000000 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR D2:DA:5E:44:BC:29 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53 +#endif + +#define CONFIG_IPADDR 192.168.205.1 + +#define CONFIG_HOSTNAME tqm8349 +#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx +#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=tqm83xx\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=/tftpboot/tqm83xx/uImage\0" \ + "kernel_addr=80060000\0" \ + "ramdisk_addr=80160000\0" \ + "load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \ + "update=protect off 80000000 8003ffff; " \ + "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \ + "upd=run load;run update\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +/* + * JFFS2 partitions + */ +/* mtdparts command line support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM834x-0" + +/* default mtd partition table */ +#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\ + "1m(kernel),2m(initrd),"\ + "-(user);"\ + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 83eb40f..16b2ce3 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -54,16 +54,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM850L/uImage\0" \ "kernel_addr=40040000\0" \ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index f20d246..bbc6960 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -52,16 +52,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM850M/uImage\0" \ "kernel_addr=40080000\0" \ diff --git a/include/configs/TQM8540.h b/include/configs/TQM8540.h deleted file mode 100644 index 8438b93..0000000 --- a/include/configs/TQM8540.h +++ /dev/null @@ -1,432 +0,0 @@ -/* - * Copyright 2005 DENX Software Engineering - * Wolfgang Denk <wd@denx.de> - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao <X.Xiao@motorola.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * TQM8540 board configuration file - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC8540 1 /* MPC8540 specific */ -#define CONFIG_TQM8540 1 /* TQM8540 board specific */ - -#undef CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33000000 -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00000000 /* memtest region */ -#define CFG_MEMTEST_END 0x10000000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ - -#else - /* - * Manually set up DDR parameters - */ - #define CFG_SDRAM_SIZE 512 /* DDR is 256MB */ - #define CFG_DDR_CS0_BNDS 0x0000001f /* 0-256MB */ - #define CFG_DDR_CS0_CONFIG 0x80000102 - #define CFG_DDR_TIMING_1 0x47445331 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ - #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ - #define CFG_DDR_MODE 0x40020062 /* DLL,normal,seq,4/2.5 */ - #define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */ -#endif - -/* - * Flash on the Local Bus - */ -#define CFG_LBC_FLASH_BASE 0xfe000000 /* Localbus SDRAM */ -#define CFG_LBC_FLASH_SIZE 32 /* LBC SDRAM is 32MB */ - -#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH 32M */ -#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */ - -#define CFG_OR0_PRELIM 0xfe000040 /* 32MB Flash */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - -#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR5 \ - | CFG_LBC_LSDMR_PRETOACT3 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC2 \ - | CFG_LBC_LSDMR_CL3 \ - | CFG_LBC_LSDMR_RFEN \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -/* RapidIO MMU */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#define CONFIG_MPC85XX_FEC 1 -#define CONFIG_MPC85XX_FEC_NAME "FEC" -#define FEC_PHY_ADDR 2 -#define FEC_PHYIDX 0 - -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 - -/* Options are TSEC[0-1], FEC */ -#define CONFIG_ETHPRIME "TSEC1" - -#endif /* CONFIG_TSEC_ENET */ - - -/* - * Environment - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000) - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 - #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET-CFG_ENV_SECT_SIZE) - #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#if defined(CFG_RAMBOOT) -# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL & ~(CFG_CMD_ENV | CFG_CMD_LOADS)) -#else -# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#endif - -#if defined(CONFIG_PCI) -# define ADD_PCI_CMD (CFG_CMD_PCI) -#else -# define ADD_PCI_CMD 0 -#endif - -#define CONFIG_COMMANDS (CONFIG_CMD_PRIV | \ - ADD_PCI_CMD | \ - CFG_CMD_I2C | \ - CFG_CMD_PING ) -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consdev=ttyS0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ - ":$hostname:$netdev:off panic=1\0" \ - "addcons=setenv bootargs $bootargs " \ - "console=$consdev,$baudrate\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm $kernel_addr\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm $kernel_addr $ramdisk_addr\0" \ - "net_nfs=tftp $loadaddr $bootfile;" \ - "run nfsargs addip addcons;bootm\0" \ - "rootpath=/opt/eldk/ppc_85xx\0" \ - "bootfile=/tftpboot/tqm8540/uImage\0" \ - "kernel_addr=FE000000\0" \ - "ramdisk_addr=FE100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 24071ff..198db19 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -57,16 +57,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM855L/uImage\0" \ "kernel_addr=40040000\0" \ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 95a41e8..e25a7a2 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -57,16 +57,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM855M/uImage\0" \ "kernel_addr=40080000\0" \ diff --git a/include/configs/TQM8560.h b/include/configs/TQM8560.h deleted file mode 100644 index 1466f31..0000000 --- a/include/configs/TQM8560.h +++ /dev/null @@ -1,421 +0,0 @@ -/* - * Copyright 2005 DENX Software Engineering - * Wolfgang Denk <wd@denx.de> - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao <X.Xiao@motorola.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * TQM8560 board configuration file - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC8560 1 /* MPC8560 specific */ -#define CONFIG_TQM8560 1 /* TQM8560 board specific */ - -#undef CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33000000 -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00000000 /* memtest region */ -#define CFG_MEMTEST_END 0x10000000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ - -#else - /* - * Manually set up DDR parameters - */ - #define CFG_SDRAM_SIZE 512 /* DDR is 256MB */ - #define CFG_DDR_CS0_BNDS 0x0000001f /* 0-256MB */ - #define CFG_DDR_CS0_CONFIG 0x80000102 - #define CFG_DDR_TIMING_1 0x47445331 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ - #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ - #define CFG_DDR_MODE 0x40020062 /* DLL,normal,seq,4/2.5 */ - #define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */ -#endif - -/* - * Flash on the Local Bus - */ -#define CFG_LBC_FLASH_BASE 0xfe000000 /* Localbus SDRAM */ -#define CFG_LBC_FLASH_SIZE 32 /* LBC SDRAM is 32MB */ - -#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH 32M */ -#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */ - -#define CFG_OR0_PRELIM 0xfe000040 /* 32MB Flash */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - -#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR5 \ - | CFG_LBC_LSDMR_PRETOACT3 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC2 \ - | CFG_LBC_LSDMR_CL3 \ - | CFG_LBC_LSDMR_RFEN \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -/* RapidIO MMU */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#define TSEC2_PHY_ADDR 1 -#define TSEC2_PHYIDX 0 - -#endif /* CONFIG_TSEC_ENET */ - -#define CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_ON_FCC3 -#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) -#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#define CONFIG_ETHPRIME "TSEC1" - -/* - * Environment - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000) - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 - #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET-CFG_ENV_SECT_SIZE) - #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#if defined(CFG_RAMBOOT) -# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL & ~(CFG_CMD_ENV | CFG_CMD_LOADS)) -#else -# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#endif - -#if defined(CONFIG_PCI) -# define ADD_PCI_CMD (CFG_CMD_PCI) -#else -# define ADD_PCI_CMD 0 -#endif - -#define CONFIG_COMMANDS (CONFIG_CMD_PRIV | \ - ADD_PCI_CMD | \ - CFG_CMD_I2C | \ - CFG_CMD_PING ) -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consdev=ttyS0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ - ":$hostname:$netdev:off panic=1\0" \ - "addcons=setenv bootargs $bootargs " \ - "console=$consdev,$baudrate\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm $kernel_addr\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm $kernel_addr $ramdisk_addr\0" \ - "net_nfs=tftp $loadaddr $bootfile;" \ - "run nfsargs addip addcons;bootm\0" \ - "rootpath=/opt/eldk/ppc_85xx\0" \ - "bootfile=/tftpboot/tqm8560/uImage\0" \ - "kernel_addr=FE000000\0" \ - "ramdisk_addr=FE100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h new file mode 100644 index 0000000..18197f2 --- /dev/null +++ b/include/configs/TQM85xx.h @@ -0,0 +1,452 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Wolfgang Denk <wd@denx.de> + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao <X.Xiao@motorola.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * TQM85xx (8560/40/55/41) board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ + +#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ + +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/* + * Only MPC8540 doesn't have CPM module + */ +#ifndef CONFIG_MPC8540 +#define CONFIG_CPM2 1 /* has CPM2 */ +#endif + +/* + * sysclk for MPC85xx + * + * Two valid values are: + * 33000000 + * 66000000 + * + * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz + * is likely the desired value here, so that is now the default. + * The board, however, can run at 66MHz. In any event, this value + * must match the settings of some switches. Details can be found + * in the README.mpc85xxads. + */ + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 33333333 +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 +#define CFG_MEMTEST_END 0x10000000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/ + +#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) +/* TQM8540 & 8560 need DLL-override */ +#define CONFIG_DDR_DLL /* DLL fix needed */ +#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ +#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */ + +#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) +#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ +#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */ + +/* + * Flash on the Local Bus + */ +#define CFG_FLASH0 0xFC000000 +#define CFG_FLASH1 0xF8000000 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } + +#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ +#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ + +#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ +#define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */ +#define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */ +#define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */ + +#define CFG_FLASH_CFI /* flash is CFI compat. */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ + +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 512 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#if defined(CONFIG_TQM8560) + +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ + +#else + +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +#endif /* CONFIG_TQM8560 */ + +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ + +/* I2C RTC */ +#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* I2C EEPROM */ +/* + * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also). + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +/* RapidIO MMU */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#define CONFIG_NET_MULTI 1 + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define FEC_PHY_ADDR 3 +#define FEC_PHYIDX 0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 + +/* Options are TSEC[0-1], FEC */ +#define CONFIG_ETHPRIME "TSEC0" + +#if defined(CONFIG_TQM8540) +/* + * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC. + * The FEC port is connected on the same signals as the FCC3 port + * of the TQM8560 to the baseboard (STK85xx Starterkit). + * + * On the STK85xx Starterkit the X47/X50 jumper has to be set to + * a - d (X50.2 - 3) to enable the FEC port. + */ +#define CONFIG_MPC85XX_FEC 1 +#define CONFIG_MPC85XX_FEC_NAME "FEC" +#endif + +#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) +/* + * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port + * can be used at once, since only one FCC port is available on the STK85xx + * Starterkit. + * + * To use this port you have to configure U-Boot to use the FCC port 1...2 + * and set the X47/X50 jumper to: + * FCC1: a - b (X47.2 - X50.2) + * FCC2: a - c (X50.2 - 1) + */ +#define CONFIG_ETHER_ON_FCC +#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */ +#endif + +#if defined(CONFIG_TQM8560) +/* + * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port + * can be used at once, since only one FCC port is available on the STK85xx + * Starterkit. + * + * To use this port you have to configure U-Boot to use the FCC port 1...3 + * and set the X47/X50 jumper to: + * FCC1: a - b (X47.2 - X50.2) + * FCC2: a - c (X50.2 - 1) + * FCC3: a - d (X50.2 - 3) + */ +#define CONFIG_ETHER_ON_FCC +#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */ +#endif + +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) +#define CONFIG_ETHER_ON_FCC1 +#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) +#define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) +#endif + +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) +#define CONFIG_ETHER_ON_FCC2 +#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13) +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) +#endif + +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) +#define CONFIG_ETHER_ON_FCC3 +#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) +#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) +#endif + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000) +#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_TIMESTAMP /* Print image info with ts */ + +#if defined(CONFIG_PCI) +# define ADD_PCI_CMD (CFG_CMD_PCI) +#else +# define ADD_PCI_CMD 0 +#endif + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP | \ + ADD_PCI_CMD | \ + CFG_CMD_I2C | \ + CFG_CMD_DATE | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DTT | \ + CFG_CMD_MII | \ + CFG_CMD_PING ) +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CFG_BOOTFILE \ + "netdev=eth0\0" \ + "consdev=ttyS0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $bootargs " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ + ":$hostname:$netdev:off panic=1\0" \ + "addcons=setenv bootargs $bootargs " \ + "console=$consdev,$baudrate\0" \ + "flash_nfs=run nfsargs addip addcons;" \ + "bootm $kernel_addr\0" \ + "flash_self=run ramargs addip addcons;" \ + "bootm $kernel_addr $ramdisk_addr\0" \ + "net_nfs=tftp $loadaddr $bootfile;" \ + "run nfsargs addip addcons;bootm\0" \ + "rootpath=/opt/eldk/ppc_85xx\0" \ + "kernel_addr=FE000000\0" \ + "ramdisk_addr=FE100000\0" \ + "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 655427e..4a1a432 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -57,16 +57,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM860L/uImage\0" \ "kernel_addr=40040000\0" \ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index f67cbd2..4b754ba 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -57,16 +57,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM860M/uImage\0" \ "kernel_addr=40080000\0" \ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index 2586518..1dc9f74 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -60,16 +60,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM862L/uImage\0" \ "kernel_addr=40040000\0" \ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 8c15499..3df060c 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -60,16 +60,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM862M/uImage\0" \ "kernel_addr=40080000\0" \ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index ea51e89..8f9c2c9 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -69,16 +69,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM866M/uImage\0" \ "kernel_addr=40080000\0" \ diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 7e3c11e..8175703 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -100,6 +100,7 @@ #define CONFIG_PCI_IO_SIZE 0x01000000 #define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 #define CONFIG_EEPRO100 1 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 @@ -108,6 +109,7 @@ #else /* MGT5100 */ +#define CONFIG_MII 1 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ #endif @@ -161,16 +163,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_82xx\0" \ "bootfile=/tftpboot/MPC5200/uImage\0" \ "" diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index d8370ed..3ca137e 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -314,7 +314,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) @@ -362,7 +362,7 @@ #define CFG_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ #define CFG_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ -#define CFG_LCD_LOGO_MAX_SIZE (1024*1024) +#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20) /*----------------------------------------------------------------------- * FPGA stuff diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 4aade44..f2f3ea7 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -52,9 +52,13 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ CONFIG_BOOTP_DNS | \ @@ -237,7 +241,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h index d7f8749..92bade5 100644 --- a/include/configs/VoVPN-GW.h +++ b/include/configs/VoVPN-GW.h @@ -165,18 +165,18 @@ #undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ "clean_nv=erase fff20000 ffffffff\0" \ -"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 $(filesize); tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 $(filesize)\0" \ -"update_lx=tftp 100000 $(kernel); erase $(kernel_addr) ffefffff; cp.b 100000 $(kernel_addr) $(filesize)\0" \ -"update_fs=tftp 100000 $(fs).$(fstype); erase ff840000 ffdfffff; cp.b 100000 ff840000 $(filesize)\0" \ -"update_ub=tftp 100000 $(uboot); protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 $(filesize); protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \ -"flashargs=setenv bootargs root=$(rootdev) rw rootfstype=$(fstype)\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \ -"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):$(netdev):off\0" \ -"addmisc=setenv bootargs $(bootargs) console=$(console),$(baudrate) ethaddr=$(ethaddr) panic=1\0" \ -"net_nfs=tftpboot 400000 $(kernel); run nfsargs addip addmisc; bootm\0" \ -"net_self=tftpboot 400000 $(kernel); run flashargs addmisc; bootm\0" \ -"flash_self=run flashargs addmisc; bootm $(kernel_addr)\0" \ -"flash_nfs=run nfsargs addip addmisc; bootm $(kernel_addr)\0" \ +"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \ +"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \ +"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \ +"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \ +"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \ +"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ +"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \ +"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \ +"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \ +"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \ +"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \ +"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \ "fstype=cramfs\0" \ "rootpath=/root_fs\0" \ "uboot=PPC/u-boot.bin\0" \ diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index ae3f1f4..8dc623e 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -275,7 +275,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 2a78082..2bd98b3 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -276,7 +276,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 5c9950f..d92f81f 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -265,7 +265,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 347bb50..9b32514 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -24,7 +24,7 @@ * config for XPedite1000 from XES Inc. * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com> * (C) Copyright 2003 Sandburst Corporation - * board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony) + * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) ***********************************************************************/ #ifndef __CONFIG_H @@ -175,6 +175,7 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */ #define CONFIG_NET_MULTI 1 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ @@ -252,7 +253,7 @@ extern void out32(unsigned int, unsigned long); /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 440GX CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 440GX CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h index 2d3c0e5..37ef105 100644 --- a/include/configs/Yukon8220.h +++ b/include/configs/Yukon8220.h @@ -90,6 +90,7 @@ CFG_CMD_SNTP ) #define CONFIG_NET_MULTI +#define CONFIG_MII /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> diff --git a/include/configs/aev.h b/include/configs/aev.h index ca6e52b..aa6bc91 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -142,22 +142,22 @@ "rootpath=/opt/eldk/ppc_6xx\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath) " \ - "console=ttyS0,$(baudrate)\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "nfsroot=${serverip}:${rootpath} " \ + "console=ttyS0,${baudrate}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 $(u-boot)\0" \ + "load=tftp 200000 ${u-boot}\0" \ "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ "update=protect off FC000000 FC05FFFF;" \ "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 $(filesize);" \ + "cp.b 200000 FC000000 ${filesize};" \ "protect on FC000000 FC05FFFF\0" \ "" diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h new file mode 100644 index 0000000..9a1c559 --- /dev/null +++ b/include/configs/armadillo.h @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * Configuation settings for the EP7312 board. + * + * Modified to work on Armadillo HT1070 ARM720T board + * (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +/*#define CONFIG_INIT_CRITICAL*/ /* undef for developing */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_ARMADILLO 1 /* on an Armadillo Board */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ + +#undef CONFIG_USE_IRQ /* don't need them anymore */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x20000300 /* armadillo board */ +#define CS8900_BUS16 1 +#undef CS8900_BUS32 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) /* | CFG_CMD_JFFS2)*/ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200" + +#define CONFIG_BOOTCOMMAND "bootm 40000 180000" + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "ARMADILLO # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00040000 /* default load address for armadillo: kernel img is here*/ + +#define CFG_HZ 2000 /* decrementer freq: 2 kHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB armadillo SDRAM */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#endif /* __CONFIG_H */ diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index f0c0283..8fad55d 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -98,7 +98,7 @@ /* #define CONFIG_ENV_OVERWRITE 1 */ #define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | \ + ((CONFIG_CMD_DFL | CFG_CMD_MII |\ CFG_CMD_DHCP ) & \ ~(CFG_CMD_BDI | \ CFG_CMD_IMI | \ diff --git a/include/configs/atc.h b/include/configs/atc.h index 881a4ca..bf6c170 100644 --- a/include/configs/atc.h +++ b/include/configs/atc.h @@ -113,8 +113,8 @@ #define CONFIG_BOOTCOMMAND \ "bootp;" \ "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\ + "nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\ "bootm" /*----------------------------------------------------------------------- diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 64ea6be..eacc744 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -73,7 +73,7 @@ * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ -#define CFG_INIT_RAM_END (8 << 10) +#define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -205,8 +205,9 @@ * DDR SDRAM *----------------------------------------------------------------------------- */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x50,0x51} /* SPD i2c spd addresses */ -#define CFG_SDRAM_ONBOARD_SIZE (64 << 20) /* Bamboo has onboard and DIMM-slots!*/ +#undef CONFIG_DDR_ECC /* don't use ECC */ +#define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */ +#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51} /*----------------------------------------------------------------------- * I2C @@ -238,17 +239,17 @@ "netdev=eth0\0" \ "hostname=bamboo\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ "flash_nfs=run nfsargs addip addtty;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=/tftpboot/bamboo/uImage\0" \ @@ -275,17 +276,17 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ +#define CONFIG_PHY1_ADDR 1 #ifndef CONFIG_BAMBOO_NAND -#define CONFIG_NET_MULTI 1 /* required for netconsole */ -#define CONFIG_PHY1_ADDR 1 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #endif /* CONFIG_BAMBOO_NAND */ -#define CONFIG_NO_PHY_RESET 1 /* no PHY reset on bamboo!!! */ - #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI 1 /* required for netconsole */ + /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -323,9 +324,13 @@ CFG_CMD_REGINFO | \ CFG_CMD_SDRAM | \ CFG_CMD_USB | \ + CFG_CMD_FAT | \ + CFG_CMD_EXT2 | \ _CFG_CMD_NAND | \ CFG_CMD_SNTP ) +#define CONFIG_SUPPORT_VFAT + /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -380,7 +385,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/barco.h b/include/configs/barco.h new file mode 100644 index 0000000..624fa1d --- /dev/null +++ b/include/configs/barco.h @@ -0,0 +1,364 @@ +/******************************************************************** + * + * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms + * + * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/include/configs/barco.h,v $ + * $Revision: 1.2 $ + * $Author: mleeman $ + * $Date: 2005/02/21 12:48:58 $ + * + * Last ChangeLog Entry + * $Log: barco.h,v $ + * Revision 1.2 2005/02/21 12:48:58 mleeman + * update of copyright years (feedback wd) + * + * Revision 1.1 2005/02/14 09:29:25 mleeman + * moved barcohydra.h to barco.h + * + * Revision 1.4 2005/02/09 12:56:23 mleeman + * add generic header to track changes in sources + * + * + *******************************************************************/ + +/* + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_BARCOBCD_STREAMING 1 + +#undef USE_DINK32 + +#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ +#define CONFIG_BAUDRATE 9600 +#define CONFIG_DRAM_SPEED 100 /* MHz */ + +#define CONFIG_BOOTARGS "mem=32M" + +/* Add support for a few extra bootp options like: + * - File size + * - DNS + */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE | \ + CONFIG_BOOTP_DNS) + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_PCI ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTCOMMAND "boot_default" + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP +#undef CFG_CMD_NET + +#define PCI_ENET0_IOADDR 0x80000000 +#define PCI_ENET0_MEMADDR 0x80000000 +#define PCI_ENET1_IOADDR 0x81000000 +#define PCI_ENET1_MEMADDR 0x81000000 + + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x02000000 + +#define CONFIG_LOGBUFFER +#ifdef CONFIG_LOGBUFFER +#define CFG_STDOUT_ADDR 0x1FFC000 +#else +#define CFG_STDOUT_ADDR 0x2B9000 +#endif + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#if defined (USE_DINK32) +#define CFG_MONITOR_LEN 0x00030000 +#define CFG_MONITOR_BASE 0x00090000 +#define CFG_RAMBOOT 1 +#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_INIT_RAM_END 0x10000 +#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#else +#undef CFG_RAMBOOT +#define CFG_MONITOR_LEN 0x00030000 +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_GBL_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +#endif + +#define CFG_FLASH_BASE 0xFFF00000 +#define CFG_FLASH_SIZE (8 * 1024 * 1024) /* Unity has onboard 1MByte flash */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x000047A4 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ +/* #define ENV_CRC 0x8BF6F24B XXX - FIXME: gets defined automatically */ + +#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ + +#define CFG_EUMB_ADDR 0xFDF00000 + +#define CFG_FLASH_RANGE_BASE 0xFFC00000 /* flash memory address range */ +#define CFG_FLASH_RANGE_SIZE 0x00400000 +#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ +#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ + +/* + * select i2c support configuration + * + * Supported configurations are {none, software, hardware} drivers. + * If the software driver is chosen, there are some additional + * configuration items that the driver uses to drive the port pins. + */ +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#ifdef CONFIG_SOFT_I2C +#error "Soft I2C is not configured properly. Please review!" +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + +#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } +#define CFG_DBUS_SIZE2 1 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + + + /* + * NS16550 Configuration (internal DUART) + */ + /* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CFG_ROMNAL 0x0F /*rom/flash next access time */ +#define CFG_ROMFAL 0x1E /*rom/flash access time */ + +#define CFG_REFINT 0x8F /* no of clock cycles between CBR refresh cycles */ + +/* the following are for SDRAM only*/ +#define CFG_BSTOPRE 0x25C /* Burst To Precharge, sets open page interval */ +#define CFG_REFREC 8 /* Refresh to activate interval */ +#define CFG_RDLAT 4 /* data latency from read command */ +#define CFG_PRETOACT 3 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_ACTORW 2 /* Activate to R/W */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ + +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 0 +#define CFG_REGDIMM 0 + + +/* memory bank settings*/ +/* + * only bits 20-29 are actually used from these vales to set the + * start/end address the upper two bits will be 0, and the lower 20 + * bits will be set to 0x00000 for a start address, or 0xfffff for an + * end address + */ +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END 0x01FFFFFF +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x02000000 +#define CFG_BANK1_END 0x02ffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x03f00000 +#define CFG_BANK2_END 0x03ffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x04000000 +#define CFG_BANK3_END 0x04ffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x05000000 +#define CFG_BANK4_END 0x05FFFFFF +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x06000000 +#define CFG_BANK5_END 0x06FFFFFF +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x07000000 +#define CFG_BANK6_END 0x07FFFFFF +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x08000000 +#define CFG_BANK7_END 0x08FFFFFF +#define CFG_BANK7_ENABLE 0 +/* + * Memory bank enable bitmask, specifying which of the banks defined above + are actually present. MSB is for bank #7, LSB is for bank #0. + */ +#define CFG_BANK_ENABLE 0x01 + +#define CFG_ODCR 0xff /* configures line driver impedances, */ + /* see 8240 book for bit definitions */ +#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ + /* currently accessed page in memory */ + /* see 8240 book for details */ + +/* SDRAM 0 - 256MB */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE @ 1GB (no backing mem) */ +#if defined(USE_DINK32) +#define CFG_IBAT1L (0x40000000 | BATL_PP_00 ) +#define CFG_IBAT1U (0x40000000 | BATU_BL_128K ) +#else +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#endif + +/* PCI memory */ +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +/* Flash, config addrs, etc */ +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_CHECKSUM + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* values according to the manual */ + +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ + +#define CONFIG_DISK_SPINUP_TIME 1000000 + + +#endif /* __CONFIG_H */ diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index bc5aaf8..4a79835 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -90,17 +90,17 @@ "netdev=eth0\0" \ "hostname=bubinga\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ "flash_nfs=run nfsargs addip addtty;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=/tftpboot/bubinga/uImage\0" \ @@ -132,6 +132,8 @@ #define CONFIG_NET_MULTI 1 #define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_NETCONSOLE /* include NetConsole support */ + #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ @@ -308,7 +310,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h index c1499f4..ae75539 100644 --- a/include/configs/c2mon.h +++ b/include/configs/c2mon.h @@ -55,8 +55,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/canmb.h b/include/configs/canmb.h index 9b91d58..2c160a4 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -92,16 +92,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ "bootfile=/tftpboot/canmb/uImage\0" \ "" diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index 12d0cca..46280f7 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -26,14 +26,13 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define AT91C_MAIN_CLOCK 207360000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */ +#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ #define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define USE_920T_MMU 1 @@ -54,7 +53,7 @@ #define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ /* clocks */ -#define PLLAR_VAL 0x202CBE04 /* 207.360 MHz for PCK */ +#define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */ #define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ #define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */ @@ -217,30 +216,30 @@ struct bd_info_ext { #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "net_nfs=tftp $(loadaddr) $(bootfile);run nfsargs addip addcons " \ + "net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \ "addmtd;bootm\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "net_cramfs=tftp $(loadaddr) $(bootfile); run flashargs addip " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \ "addcons addmtd; bootm\0" \ "flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \ "flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \ - "addip=setenv bootargs $(bootargs) ethaddr=$(ethaddr) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \ - "$(hostname)::off\0" \ - "addcons=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0" \ - "addmtd=setenv bootargs $(bootargs) mtdparts=cmc_pu2:128k(uboot)ro," \ + "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "${hostname}::off\0" \ + "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \ "64k(environment),768k(linux),4096k(root),-\0" \ - "load=tftp $(loadaddr) $(loadfile)\0" \ + "load=tftp ${loadaddr} ${loadfile}\0" \ "update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \ - "cp.b $(loadaddr) 10000000 $(filesize);" \ + "cp.b ${loadaddr} 10000000 ${filesize};" \ "protect on 10000000 1001ffff\0" \ - "updatel=era 10030000 100effff;tftp $(loadaddr) $(bootfile); " \ - "cp.b $(loadaddr) 10030000 $(filesize)\0" \ - "updatec=era 100f0000 104effff;tftp $(loadaddr) $(cramfsimage); " \ - "cp.b $(loadaddr) 100f0000 $(filesize)\0" \ - "updatej=era 104f0000 107fffff;tftp $(loadaddr) $(jffsimage); " \ - "cp.b $(loadaddr) 104f0000 $(filesize)\0" \ + "updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \ + "cp.b ${loadaddr} 10030000 ${filesize}\0" \ + "updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \ + "cp.b ${loadaddr} 100f0000 ${filesize}\0" \ + "updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \ + "cp.b ${loadaddr} 104f0000 ${filesize}\0" \ "cramfsimage=cramfs_cmc-pu2.img\0" \ "jffsimage=jffs2_cmc-pu2.img\0" \ "loadfile=u-boot_cmc-pu2.bin\0" \ diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h new file mode 100644 index 0000000..f9586fb --- /dev/null +++ b/include/configs/cpci5200.h @@ -0,0 +1,417 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + + */ + +/************************************************************************* + * (c) 2005 esd gmbh Hannover + * + * + * from IceCube.h file + * by Reinhard Arlt reinhard.arlt@esd-electronics.com + * + *************************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_ICECUBE 1 /* ... on IceCube board */ +#define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */ +#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#if 1 +#define CONFIG_PCI 1 +#if 1 +#define CONFIG_PCI_PNP 1 +#endif +#define CONFIG_PCI_SCAN_SHOW 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 +#endif + +#define CONFIG_MII +#if 0 /* test-only !!! */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_EEPRO100 1 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_NS8382X 1 +#endif + +#define ADD_PCI_CMD CFG_CMD_PCI + +#else /* MPC5100 */ + +#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ + +#endif + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* USB */ +#if 0 +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define CONFIG_USB_STORAGE +#else +#define ADD_USB_CMD 0 +#endif + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_IDE | \ + CFG_CMD_I2C | \ + CFG_CMD_BSP | \ + CFG_CMD_ELF | \ + CFG_CMD_EXT2 | \ + CFG_CMD_DATE | \ + ADD_PCI_CMD ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT16 1 +#endif +#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT08 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Welcome to esd CPU CPCI/5200;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ + "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ + "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \ + "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \ + "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \ + "loadaddr=01000000\0" \ + "serverip=192.168.2.99\0" \ + "gatewayip=10.0.0.79\0" \ + "user=mu\0" \ + "target=cpci5200.esd\0" \ + "script=cpci5200.bat\0" \ + "image=/tftpboot/vxWorks_cpci5200\0" \ + "ipaddr=10.0.13.196\0" \ + "netmask=255.255.0.0\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_vxworks0" + +#if defined(CONFIG_MPC5200) + +#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ +#define CFG_NVRAM_BASE_ADDR 0xfd010000 +#define CFG_NVRAM_SIZE 32*1024 + +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#endif +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 86000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CFG_I2C_MULTI_EEPROMS 1 +/* + * Flash configuration + */ + +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_SIZE 0x02000000 +#define CFG_FLASH_INCREMENT 0x01000000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000) +#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 128 + +#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +/* + * Environment settings + */ +#if 1 /* test-only */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x20000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_OVERWRITE 1 +#else +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */ + /* total size of a CAT24WC32 is 8192 bytes */ +#define CONFIG_ENV_OVERWRITE 1 +#endif + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_UDP_CHECKSUM 1 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x01052444 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x0004DD00 + +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS1_START 0xfd000000 +#define CFG_CS1_SIZE 0x00010000 +#define CFG_CS1_CFG 0x10101410 + +#define CFG_CS3_START 0xfd010000 +#define CFG_CS3_SIZE 0x00010000 +#define CFG_CS3_CFG 0x10109410 + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +/*----------------------------------------------------------------------- + * CPLD stuff + */ +#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ +#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ + +/* CPLD program pin configuration */ +#define CFG_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */ +#define CFG_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */ +#define CFG_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */ +#define CFG_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */ + +#define JTAG_GPIO_ADDR_TMS (CFG_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */ +#define JTAG_GPIO_ADDR_TCK (CFG_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */ +#define JTAG_GPIO_ADDR_TDI (CFG_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */ +#define JTAG_GPIO_ADDR_TDO (CFG_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */ + +#define JTAG_GPIO_ADDR_CFG (CFG_MBAR + 0xB00) +#define JTAG_GPIO_CFG_SET 0x00000000 +#define JTAG_GPIO_CFG_RESET 0x00F00000 + +#define JTAG_GPIO_ADDR_EN_TMS (CFG_MBAR + 0xB04) +#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */ +#define JTAG_GPIO_TMS_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TMS (CFG_MBAR + 0xB0C) +#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */ +#define JTAG_GPIO_TMS_DDR_RESET 0x00000000 + +#define JTAG_GPIO_ADDR_EN_TCK (CFG_MBAR + 0xC00) +#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */ +#define JTAG_GPIO_TCK_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TCK (CFG_MBAR + 0xC08) +#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */ +#define JTAG_GPIO_TCK_DDR_RESET 0x00000000 + +#define JTAG_GPIO_ADDR_EN_TDI (CFG_MBAR + 0xC00) +#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */ +#define JTAG_GPIO_TDI_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TDI (CFG_MBAR + 0xC08) +#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */ +#define JTAG_GPIO_TDI_DDR_RESET 0x00000000 + +#define JTAG_GPIO_ADDR_EN_TDO (CFG_MBAR + 0xB04) +#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */ +#define JTAG_GPIO_TDO_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TDO (CFG_MBAR + 0xB0C) +#define JTAG_GPIO_TDO_DDR_SET 0x00000000 +#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/csb272.h b/include/configs/csb272.h index ac1cead..27d64c1 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -58,7 +58,7 @@ #define CONFIG_BOOTCOMMAND \ "setenv bootargs console=ttyS0,38400 debug " \ "root=/dev/ram rw ramdisk_size=4096 " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm fe000000 fe100000" #endif @@ -67,8 +67,8 @@ #define CONFIG_BOOTCOMMAND \ "bootp; " \ "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #endif @@ -291,7 +291,7 @@ * Cache configuration * */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 4e5dcfc..09d52de 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -58,7 +58,7 @@ #define CONFIG_BOOTCOMMAND \ "setenv bootargs console=ttyS0,38400 debug " \ "root=/dev/ram rw ramdisk_size=4096 " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm ff800000 ff900000" #endif @@ -67,8 +67,8 @@ #define CONFIG_BOOTCOMMAND \ "bootp; " \ "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #endif @@ -291,7 +291,7 @@ * Cache configuration * */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 diff --git a/include/configs/csb637.h b/include/configs/csb637.h new file mode 100644 index 0000000..071d5b7 --- /dev/null +++ b/include/configs/csb637.h @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de> + * Anders Larsen <alarsen@rea.de> + * + * Configuation settings for the Cogent CSB637 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */ +#define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ +#define CONFIG_CSB637 1 /* on a CSB637 board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define USE_920T_MMU 1 + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define CFG_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define MC_PUIA_VAL 0x00000000 +#define MC_PUP_VAL 0x00000000 +#define MC_PUER_VAL 0x00000000 +#define MC_ASR_VAL 0x00000000 +#define MC_AASR_VAL 0x00000000 +#define EBI_CFGR_VAL 0x00000000 +#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */ +#define PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */ +#define MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */ + +/* sdram */ +#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define PIOC_BSR_VAL 0x00000000 +#define PIOC_PDR_VAL 0xFFFF0000 +#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define SDRC_CR_VAL 0x21914159 /* set up the SDRAM */ +#define SDRAM 0x20000000 /* address of the SDRAM */ +#define SDRAM1 0x20000080 /* address of the SDRAM */ +#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define SDRC_MR_VAL1 0x00000004 /* refresh */ +#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_BAUDRATE 115200 + +#define CFG_AT91C_BRGR_DIVISOR 75 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */ + +/* + * Hardware drivers + */ + +/* define one of these to choose the DBGU, USART0 or USART1 as console */ +#define CONFIG_DBGU +#undef CONFIG_USART0 +#undef CONFIG_USART1 + +#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ + +#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ + +#define CONFIG_BOOTDELAY 3 +/* #define CONFIG_ENV_OVERWRITE 1 */ + +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING ) & \ + ~(CFG_CMD_BDI | \ + CFG_CMD_IMI | \ + CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_FPGA | \ + CFG_CMD_MISC | \ + CFG_CMD_LOADS )) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ +#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ + +#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) +#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) + +#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +/* the following are NOP's in our implementation */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4 +#define CFG_ALT_MEMTEST 1 +#define CFG_MEMTEST_SCRATCH CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 4 + +#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_RETRY_COUNT 20 +#undef CONFIG_AT91C_USE_RMII + +#undef CONFIG_HAS_DATAFLASH +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_BANKS 0 +#define CFG_MAX_DATAFLASH_PAGES 16384 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ +#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ + +/* + * FLASH Device configuration + */ +#define PHYS_FLASH_1 0x10000000 +#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ +#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ +#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ +#define CFG_MAX_FLASH_SECT 64 + +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_FIRST_SECTOR 3 +#define CFG_JFFS2_NUM_BANKS 1 + +#undef CFG_ENV_IS_IN_DATAFLASH + +#ifdef CFG_ENV_IS_IN_DATAFLASH +#define CFG_ENV_OFFSET 0x20000 +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ +#else +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */ +#define CFG_ENV_SIZE 0x20000 /* sectors are 128K here */ +#endif /* CFG_ENV_IS_IN_DATAFLASH */ + + +#define CFG_LOAD_ADDR 0x21000000 /* default load address */ + +#define CFG_BAUDRATE_TABLE {115200, 57600, 38400, 19200, 9600 } + +#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ + +#ifndef __ASSEMBLY__ +/*----------------------------------------------------------------------- + * Board specific extension for bd_info + * + * This structure is embedded in the global bd_info (bd_t) structure + * and can be used by the board specific code (eg board/...) + */ + +struct bd_info_ext { + /* helper variable for board environment handling + * + * env_crc_valid == 0 => uninitialised + * env_crc_valid > 0 => environment crc in flash is valid + * env_crc_valid < 0 => environment crc in flash is invalid + */ + int env_crc_valid; +}; +#endif + +#define CFG_HZ 1000 +#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ + /* AT91C_TC_TIMER_DIV1_CLOCK */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index 984115a..0a10e3c 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -65,11 +65,11 @@ #undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ - "addmisc=setenv bootargs $(bootargs) " \ - "console=ttyS0,$(baudrate) " \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ "panic=1\0" \ "bootfile=/tftpboot/vmlinux.srec\0" \ - "load=tftp 80500000 $(u-boot)\0" \ + "load=tftp 80500000 ${u-boot}\0" \ "" #ifdef CONFIG_DBAU1550 diff --git a/include/configs/debris.h b/include/configs/debris.h index b483f40..8ff963f 100644 --- a/include/configs/debris.h +++ b/include/configs/debris.h @@ -45,9 +45,9 @@ #define CONFIG_BOOTCOMMAND \ "tftp 800000 pImage; " \ "setenv bootargs console=ttyS0,9600 init=/linuxrc " \ - "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):eth0:none " \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:eth0:none " \ "mtdparts=phys:12m(root),-(kernel); " \ "bootm 800000" diff --git a/include/configs/ebony.h b/include/configs/ebony.h index ebd0b53..a26af69 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -21,7 +21,7 @@ */ /************************************************************************ - * board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony) + * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) ***********************************************************************/ #ifndef __CONFIG_H @@ -31,6 +31,7 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_EBONY 1 /* Board is ebony */ +#define CONFIG_440GP 1 /* Specifc GP support */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #undef CFG_DRAM_TEST /* Disable-takes long time! */ @@ -154,17 +155,17 @@ "netdev=eth0\0" \ "hostname=ebony\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ "flash_nfs=run nfsargs addip addtty;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=/tftpboot/ebony/uImage\0" \ @@ -191,6 +192,12 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 8 /* PHY address */ +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ @@ -241,8 +248,6 @@ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -269,7 +274,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h index 8b0afd5..6862519 100644 --- a/include/configs/ep8260.h +++ b/include/configs/ep8260.h @@ -299,6 +299,7 @@ CFG_CMD_BSP | \ CFG_CMD_DCR | \ CFG_CMD_DHCP | \ + CFG_CMD_DISPLAY | \ CFG_CMD_DOC | \ CFG_CMD_DTT | \ CFG_CMD_EEPROM | \ @@ -465,8 +466,13 @@ #define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ #endif +#ifdef CFG_EP8260_H2 +#define CFG_FLASH_ERASE_TOUT 240000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#else #define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ +#endif #ifndef CFG_RAMBOOT # define CFG_ENV_IS_IN_FLASH 1 @@ -606,7 +612,11 @@ * SCCR - System Clock Control 9-8 *----------------------------------------------------------------------- */ +#ifdef CFG_EP8260_H2 +#define CFG_SCCR (SCCR_DFBRG00) +#else #define CFG_SCCR (SCCR_DFBRG01) +#endif /*----------------------------------------------------------------------- * RCCR - RISC Controller Configuration 13-7 diff --git a/include/configs/hermes.h b/include/configs/hermes.h index 1486377..91117ba 100644 --- a/include/configs/hermes.h +++ b/include/configs/hermes.h @@ -55,8 +55,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index 9da15ed..cfaf153 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -60,13 +60,14 @@ */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_DATE | \ + CFG_CMD_DISPLAY | \ CFG_CMD_DHCP | \ CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IDE | \ CFG_CMD_NFS | \ CFG_CMD_PCI | \ - CFG_CMD_SNTP) + CFG_CMD_SNTP ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -91,19 +92,21 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_82xx\0" \ "" #define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_MISC_INIT_R 1 + /* * IPB Bus clocking configuration. */ @@ -166,6 +169,9 @@ #define CFG_MBAR 0xF0000000 #define CFG_SDRAM_BASE 0x00000000 #define CFG_DEFAULT_MBAR 0x80000000 +#define CFG_DISPLAY_BASE 0x80600000 +#define CFG_STATUS1_BASE 0x80600200 +#define CFG_STATUS2_BASE 0x80600300 /* Settings for XLB = 132 MHz */ #define SDRAM_DDR 1 @@ -269,8 +275,8 @@ /* Display H1, Status Inputs, EPLD @0x80600000 */ #define CFG_CS3_START 0x80600000 -#define CFG_CS3_SIZE 0x00000210 -#define CFG_CS3_CFG 0x9800 +#define CFG_CS3_SIZE 0x00100000 +#define CFG_CS3_CFG 0x00019800 #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x33333333 @@ -308,6 +314,11 @@ #define CONFIG_ATAPI 1 +#define CONFIG_VIDEO_SMI_LYNXEM +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO + /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -325,4 +336,13 @@ #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0x01000000 +#define CFG_ISA_IO CONFIG_PCI_IO_BUS + +/*---------------------------------------------------------------------*/ +/* Display addresses */ +/*---------------------------------------------------------------------*/ + +#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38) +#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30) + #endif /* __CONFIG_H */ diff --git a/include/configs/hymod.h b/include/configs/hymod.h index aadb59f..8cad98d 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -177,6 +177,7 @@ #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ CFG_CMD_BEDBUG | \ CFG_CMD_BMP | \ + CFG_CMD_DISPLAY | \ CFG_CMD_DOC | \ CFG_CMD_EXT2 | \ CFG_CMD_FDC | \ diff --git a/include/configs/incaip.h b/include/configs/incaip.h index 0f548a5..1c6216b 100644 --- a/include/configs/incaip.h +++ b/include/configs/incaip.h @@ -55,29 +55,29 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off\0" \ - "addmisc=setenv bootargs $(bootargs) " \ - "console=ttyS0,$(baudrate) " \ - "ethaddr=$(ethaddr) " \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off\0" \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ + "ethaddr=${ethaddr} " \ "panic=1\0" \ "flash_nfs=run nfsargs addip addmisc;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addmisc;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 80500000 $(bootfile);" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 80500000 ${bootfile};" \ "run nfsargs addip addmisc;bootm\0" \ "rootpath=/opt/eldk/mips_4KC\0" \ "bootfile=/tftpboot/INCA/uImage\0" \ "kernel_addr=B0040000\0" \ "ramdisk_addr=B0100000\0" \ "u-boot=/tftpboot/INCA/u-boot.bin\0" \ - "load=tftp 80500000 $(u-boot)\0" \ + "load=tftp 80500000 ${u-boot}\0" \ "update=protect off 1:0-2;era 1:0-2;" \ - "cp.b 80500000 B0000000 $(filesize)\0" \ + "cp.b 80500000 B0000000 ${filesize}\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 5cbb0c3..773d5d2 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -101,7 +101,7 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ @@ -109,21 +109,40 @@ #undef CONFIG_BOOTARGS +#define CONFIG_ETHADDR 00:a0:a4:03:00:00 +#define CONFIG_OVERWRITE_ETHADDR_ONCE + +#define CONFIG_IPADDR 192.168.100.2 +#define CONFIG_SERVERIP 192.168.100.1 +#define CONFIG_NETMASK 255.255.255.0 +#define HOSTNAME inka4x0 +#define CONFIG_BOOTFILE /tftpboot/inka4x0/uImage +#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx + #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addcons=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate}\0" \ + "flash_nfs=run nfsargs addip addcons;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};" \ + "run nfsargs addip addcons;bootm\0" \ + "enable_disp=mw.l 100000 04000000 1;" \ + "cp.l 100000 f0000b20 1;" \ + "cp.l 100000 f0000b28 1\0" \ + "ideargs=setenv bootargs root=/dev/hda1 rw\0" \ + "ide_boot=ext2load ide 0:1 200000 uImage;" \ + "run ideargs addip addcons enable_disp;bootm" \ + "brightness=255\0" \ "" -#define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_BOOTCOMMAND "run ide_boot" /* * IPB Bus clocking configuration. @@ -193,6 +212,7 @@ */ /* #define CONFIG_FEC_10MBIT 1 */ #define CONFIG_PHY_ADDR 0x00 +#define CONFIG_MII /* * GPIO configuration @@ -305,22 +325,14 @@ #define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ #define CFG_ATA_IDE0_OFFSET 0x0000 - #define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 +#define CFG_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */ +#define CFG_ATA_STRIDE 4 /* Interval between registers */ #define CONFIG_ATAPI 1 -#define CFG_BRIGHTNESS 0x20 + +#define CFG_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */ #endif /* __CONFIG_H */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 2674b52..2f6e399 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -30,24 +30,25 @@ #ifndef __CONFIG_H #define __CONFIG_H - /* * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_INTEGRATOR 1 /* in an Integrator board */ -#define CONFIG_ARCH_CINTEGRATOR 1 /* Specifically, a CP */ - - -#define CFG_MEMTEST_START 0x100000 -#define CFG_MEMTEST_END 0x10000000 -#define CFG_HZ (1000000 / 256) /* Timer 1 is clocked at 1Mhz, with 256 divider */ -#define CFG_TIMERBASE 0x13000100 +#define CFG_MEMTEST_START 0x100000 +#define CFG_MEMTEST_END 0x10000000 +#define CFG_HZ 1000 +#define CFG_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ +#define CFG_TIMERBASE 0x13000100 /* Timer1 */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ + +#undef CONFIG_INIT_CRITICAL +#define CONFIG_CM_INIT 1 +#define CONFIG_CM_REMAP 1 +#undef CONFIG_CM_SPD_DETECT + /* * Size of malloc() pool */ @@ -59,36 +60,36 @@ */ #define CFG_PL010_SERIAL #define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 38400 +#define CONFIG_BAUDRATE 38400 #define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) } -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CFG_SERIAL0 0x16000000 #define CFG_SERIAL1 0x17000000 /*#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */ /*#define CONFIG_NET_MULTI */ -/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ +/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ -#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) +#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> -#define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" -#define CONFIG_BOOTCOMMAND "" +#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" +#define CONFIG_BOOTCOMMAND "" /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CFG_LOAD_ADDR 0x7fc0 /* default load address */ @@ -107,11 +108,11 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ -#define CFG_FLASH_BASE 0x24000000 +#define CFG_FLASH_BASE 0x24000000 /*----------------------------------------------------------------------- * FLASH and environment organization @@ -120,10 +121,10 @@ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ /* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ -#define CFG_MAX_FLASH_SECT 128 -#define CFG_ENV_SIZE 32768 +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ +#define CFG_MAX_FLASH_SECT 128 +#define CFG_ENV_SIZE 32768 #define PHYS_FLASH_1 (CFG_FLASH_BASE) @@ -131,37 +132,37 @@ * PCI definitions */ -/*#define CONFIG_PCI /--* include pci support */ +/*#define CONFIG_PCI /--* include pci support */ #undef CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ #define DEBUG #define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define INTEGRATOR_BOOT_ROM_BASE 0x20000000 -#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 +#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 /* PCI Base area */ #define INTEGRATOR_PCI_BASE 0x40000000 #define INTEGRATOR_PCI_SIZE 0x3FFFFFFF /* memory map as seen by the CPU on the local bus */ -#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */ +#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */ #define CPU_PCI_IO_SIZE 0x10000 #define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */ #define CPU_PCI_CNFG_SIZE 0x1000000 -#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */ +#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */ /* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */ -#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */ +#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */ /* unused (128-16)M from B1000000-B7FFFFFF */ -#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ +#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ /* unused ((128-16)M - 64K) from XXX */ -#define PCI_V3_BASE 0x62000000 +#define PCI_V3_BASE 0x62000000 /* V3 PCI bridge controller */ #define V3_BASE 0x62000000 /* V360EPC registers */ @@ -170,102 +171,110 @@ #define PCI_ENET0_MEMADDR (PCI_MEM_BASE) -#define V3_PCI_VENDOR 0x00000000 -#define V3_PCI_DEVICE 0x00000002 -#define V3_PCI_CMD 0x00000004 -#define V3_PCI_STAT 0x00000006 -#define V3_PCI_CC_REV 0x00000008 -#define V3_PCI_HDR_CF 0x0000000C -#define V3_PCI_IO_BASE 0x00000010 -#define V3_PCI_BASE0 0x00000014 -#define V3_PCI_BASE1 0x00000018 -#define V3_PCI_SUB_VENDOR 0x0000002C -#define V3_PCI_SUB_ID 0x0000002E -#define V3_PCI_ROM 0x00000030 -#define V3_PCI_BPARAM 0x0000003C -#define V3_PCI_MAP0 0x00000040 -#define V3_PCI_MAP1 0x00000044 -#define V3_PCI_INT_STAT 0x00000048 -#define V3_PCI_INT_CFG 0x0000004C -#define V3_LB_BASE0 0x00000054 -#define V3_LB_BASE1 0x00000058 -#define V3_LB_MAP0 0x0000005E -#define V3_LB_MAP1 0x00000062 -#define V3_LB_BASE2 0x00000064 -#define V3_LB_MAP2 0x00000066 -#define V3_LB_SIZE 0x00000068 -#define V3_LB_IO_BASE 0x0000006E -#define V3_FIFO_CFG 0x00000070 -#define V3_FIFO_PRIORITY 0x00000072 -#define V3_FIFO_STAT 0x00000074 -#define V3_LB_ISTAT 0x00000076 -#define V3_LB_IMASK 0x00000077 -#define V3_SYSTEM 0x00000078 -#define V3_LB_CFG 0x0000007A -#define V3_PCI_CFG 0x0000007C -#define V3_DMA_PCI_ADR0 0x00000080 -#define V3_DMA_PCI_ADR1 0x00000090 -#define V3_DMA_LOCAL_ADR0 0x00000084 -#define V3_DMA_LOCAL_ADR1 0x00000094 -#define V3_DMA_LENGTH0 0x00000088 -#define V3_DMA_LENGTH1 0x00000098 -#define V3_DMA_CSR0 0x0000008B -#define V3_DMA_CSR1 0x0000009B -#define V3_DMA_CTLB_ADR0 0x0000008C -#define V3_DMA_CTLB_ADR1 0x0000009C -#define V3_DMA_DELAY 0x000000E0 -#define V3_MAIL_DATA 0x000000C0 -#define V3_PCI_MAIL_IEWR 0x000000D0 -#define V3_PCI_MAIL_IERD 0x000000D2 -#define V3_LB_MAIL_IEWR 0x000000D4 -#define V3_LB_MAIL_IERD 0x000000D6 -#define V3_MAIL_WR_STAT 0x000000D8 -#define V3_MAIL_RD_STAT 0x000000DA -#define V3_QBA_MAP 0x000000DC +#define V3_PCI_VENDOR 0x00000000 +#define V3_PCI_DEVICE 0x00000002 +#define V3_PCI_CMD 0x00000004 +#define V3_PCI_STAT 0x00000006 +#define V3_PCI_CC_REV 0x00000008 +#define V3_PCI_HDR_CF 0x0000000C +#define V3_PCI_IO_BASE 0x00000010 +#define V3_PCI_BASE0 0x00000014 +#define V3_PCI_BASE1 0x00000018 +#define V3_PCI_SUB_VENDOR 0x0000002C +#define V3_PCI_SUB_ID 0x0000002E +#define V3_PCI_ROM 0x00000030 +#define V3_PCI_BPARAM 0x0000003C +#define V3_PCI_MAP0 0x00000040 +#define V3_PCI_MAP1 0x00000044 +#define V3_PCI_INT_STAT 0x00000048 +#define V3_PCI_INT_CFG 0x0000004C +#define V3_LB_BASE0 0x00000054 +#define V3_LB_BASE1 0x00000058 +#define V3_LB_MAP0 0x0000005E +#define V3_LB_MAP1 0x00000062 +#define V3_LB_BASE2 0x00000064 +#define V3_LB_MAP2 0x00000066 +#define V3_LB_SIZE 0x00000068 +#define V3_LB_IO_BASE 0x0000006E +#define V3_FIFO_CFG 0x00000070 +#define V3_FIFO_PRIORITY 0x00000072 +#define V3_FIFO_STAT 0x00000074 +#define V3_LB_ISTAT 0x00000076 +#define V3_LB_IMASK 0x00000077 +#define V3_SYSTEM 0x00000078 +#define V3_LB_CFG 0x0000007A +#define V3_PCI_CFG 0x0000007C +#define V3_DMA_PCI_ADR0 0x00000080 +#define V3_DMA_PCI_ADR1 0x00000090 +#define V3_DMA_LOCAL_ADR0 0x00000084 +#define V3_DMA_LOCAL_ADR1 0x00000094 +#define V3_DMA_LENGTH0 0x00000088 +#define V3_DMA_LENGTH1 0x00000098 +#define V3_DMA_CSR0 0x0000008B +#define V3_DMA_CSR1 0x0000009B +#define V3_DMA_CTLB_ADR0 0x0000008C +#define V3_DMA_CTLB_ADR1 0x0000009C +#define V3_DMA_DELAY 0x000000E0 +#define V3_MAIL_DATA 0x000000C0 +#define V3_PCI_MAIL_IEWR 0x000000D0 +#define V3_PCI_MAIL_IERD 0x000000D2 +#define V3_LB_MAIL_IEWR 0x000000D4 +#define V3_LB_MAIL_IERD 0x000000D6 +#define V3_MAIL_WR_STAT 0x000000D8 +#define V3_MAIL_RD_STAT 0x000000DA +#define V3_QBA_MAP 0x000000DC /* SYSTEM register bits */ -#define V3_SYSTEM_M_RST_OUT (1 << 15) -#define V3_SYSTEM_M_LOCK (1 << 14) +#define V3_SYSTEM_M_RST_OUT (1 << 15) +#define V3_SYSTEM_M_LOCK (1 << 14) /* PCI_CFG bits */ -#define V3_PCI_CFG_M_RETRY_EN (1 << 10) -#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) -#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) +#define V3_PCI_CFG_M_RETRY_EN (1 << 10) +#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) +#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) /* PCI MAP register bits (PCI -> Local bus) */ -#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 -#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) -#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10) -#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8) -#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 -#define V3_PCI_MAP_M_REG_EN (1 << 1) -#define V3_PCI_MAP_M_ENABLE (1 << 0) +#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 +#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) +#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10) +#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8) +#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 +#define V3_PCI_MAP_M_REG_EN (1 << 1) +#define V3_PCI_MAP_M_ENABLE (1 << 0) /* 9 => 512M window size */ -#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 +#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 /* A => 1024M window size */ -#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 +#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 /* LB_BASE register bits (Local bus -> PCI) */ -#define V3_LB_BASE_M_MAP_ADR 0xFFF00000 -#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9) -#define V3_LB_BASE_M_ADR_SIZE 0x000000F0 -#define V3_LB_BASE_M_PREFETCH (1 << 3) -#define V3_LB_BASE_M_ENABLE (1 << 0) +#define V3_LB_BASE_M_MAP_ADR 0xFFF00000 +#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9) +#define V3_LB_BASE_M_ADR_SIZE 0x000000F0 +#define V3_LB_BASE_M_PREFETCH (1 << 3) +#define V3_LB_BASE_M_ENABLE (1 << 0) /* PCI COMMAND REGISTER bits */ -#define V3_COMMAND_M_FBB_EN (1 << 9) -#define V3_COMMAND_M_SERR_EN (1 << 8) -#define V3_COMMAND_M_PAR_EN (1 << 6) -#define V3_COMMAND_M_MASTER_EN (1 << 2) -#define V3_COMMAND_M_MEM_EN (1 << 1) -#define V3_COMMAND_M_IO_EN (1 << 0) +#define V3_COMMAND_M_FBB_EN (1 << 9) +#define V3_COMMAND_M_SERR_EN (1 << 8) +#define V3_COMMAND_M_PAR_EN (1 << 6) +#define V3_COMMAND_M_MASTER_EN (1 << 2) +#define V3_COMMAND_M_MEM_EN (1 << 1) +#define V3_COMMAND_M_IO_EN (1 << 0) #define INTEGRATOR_SC_BASE 0x11000000 #define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 #define INTEGRATOR_SC_PCIENABLE \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) +/*----------------------------------------------------------------------- + * There are various dependencies on the core module (CM) fitted + * Users should refer to their CM user guide + * - when porting adjust u-boot/Makefile accordingly + * to define the necessary CONFIG_ s for the CM involved + * see e.g. integratorcp_CM926EJ-S_config + */ +#include "armcoremodule.h" -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 0b0ffd4..4189f9c 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -35,23 +35,15 @@ * High Level Configuration Options * (easy to change) */ -#if 1 -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#else -#define CONFIG_ARM946ES 1 /* This is an arm946es CPU core */ -#endif -#define CONFIG_INTEGRATOR 1 /* in an Integrator board */ -#define CONFIG_ARCH_CINTEGRATOR 1 /* Specifically, a CP */ - +#define CFG_MEMTEST_START 0x100000 +#define CFG_MEMTEST_END 0x10000000 +#define CFG_HZ 1000 +#define CFG_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ +#define CFG_TIMERBASE 0x13000100 -#define CFG_MEMTEST_START 0x100000 -#define CFG_MEMTEST_END 0x10000000 -#define CFG_HZ (1000000 / 256) /* Timer 1 is clocked at 1Mhz, with 256 divider */ -#define CFG_TIMERBASE 0x13000100 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ /* * Size of malloc() pool */ @@ -74,7 +66,7 @@ #define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 } #define CONFIG_CONS_INDEX 0 #define CONFIG_BAUDRATE 38400 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CFG_SERIAL0 0x16000000 #define CFG_SERIAL1 0x17000000 @@ -92,20 +84,31 @@ #if 0 #define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0" +#define CONFIG_BOOTARGS "root=/dev/nfs nfsroot=<IP address>:/<exported rootfs> mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" #define CONFIG_BOOTCOMMAND "bootp ; bootm" #endif +/* The kernel command line & boot command below are for a platform flashed with afu.axf + +Image 666 Block 0 End Block 0 address 0x24000000 exec 0x24000000- name u-boot +Image 667 Block 1 End Block 13 address 0x24040000 exec 0x24040000- name u-linux +Image 668 Block 14 End Block 33 address 0x24380000 exec 0x24380000- name rootfs +SIB at Block62 End Block62 address 0x24f80000 + +*/ +#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0 console=ttyAMA0" +#define CONFIG_BOOTCOMMAND "cp 0x24080000 0x7fc0 0x100000; bootm" /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size*/ /* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size*/ #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CFG_LOAD_ADDR 0x7fc0 /* default load address */ @@ -124,24 +127,117 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ /*----------------------------------------------------------------------- * FLASH and environment organization + + * Top varies according to amount fitted + * Reserve top 4 blocks of flash + * - ARM Boot Monitor + * - Unused + * - SIB block + * - U-Boot environment + * + * Base is always 0x24000000 + */ -#define CFG_FLASH_BASE 0x24000000 +#define CFG_FLASH_BASE 0x24000000 #define CFG_MAX_FLASH_SECT 64 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ -#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_MONITOR_LEN 0x00100000 +#define CFG_ENV_IS_IN_FLASH (1) + +/* + * Move up the U-Boot & monitor area if more flash is fitted. + * If this U-Boot is to be run on Integrators with varying flash sizes, + * drivers/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG + * register and dynamically assign CFG_ENV_ADDR & CFG_MONITOR_BASE + * - CFG_MONITOR_BASE is set to indicate that the environment is not + * embedded in the boot monitor(s) area + */ +#if ( PHYS_FLASH_SIZE == 0x04000000 ) + +#define CFG_ENV_ADDR 0x27F00000 +#define CFG_MONITOR_BASE 0x27F40000 + +#elif (PHYS_FLASH_SIZE == 0x02000000 ) + +#define CFG_ENV_ADDR 0x25F00000 +#define CFG_MONITOR_BASE 0x25F40000 + +#else -#define CFG_MONITOR_BASE 0x24F40000 -#define CFG_ENV_IS_IN_FLASH #define CFG_ENV_ADDR 0x24F00000 +#define CFG_MONITOR_BASE 0x27F40000 + +#endif + #define CFG_ENV_SECT_SIZE 0x40000 /* 256KB */ #define CFG_ENV_SIZE 8192 /* 8KB */ +/*----------------------------------------------------------------------- + * CP control registers + */ +#define CPCR_BASE 0xCB000000 /* CP Registers*/ +#define OS_FLASHPROG 0x00000004 /* Flash register*/ +#define CPMASK_EXTRABANK 0x8 +#define CPMASK_FLASHSIZE 0x4 +#define CPMASK_FLWREN 0x2 +#define CPMASK_FLVPPEN 0x1 + +/* + * The ARM boot monitor initializes the board. + * However, the default U-Boot code also performs the initialization. + * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT + * - see documentation supplied with board for details of how to choose the + * image to run at reset/power up + * e.g. whether the ARM Boot Monitor runs before U-Boot + +#define CONFIG_SKIP_LOWLEVEL_INIT + + */ + +/* + * The ARM boot monitor does not relocate U-Boot. + * However, the default U-Boot code performs the relocation check, + * and may relocate the code if the memory map is changed. + * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT + +#define SKIP_CONFIG_RELOCATE_UBOOT + + */ +/*----------------------------------------------------------------------- + * There are various dependencies on the core module (CM) fitted + * Users should refer to their CM user guide + * - when porting adjust u-boot/Makefile accordingly + * to define the necessary CONFIG_ s for the CM involved + * see e.g. cp_926ejs_config + */ + +#include "armcoremodule.h" + +/* + * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & + * the core module has a CM_INIT register + * then the U-Boot initialisation code will + * e.g. ARM Boot Monitor or pre-loader is repeated once + * (to re-initialise any existing CM_INIT settings to safe values). + * + * This is usually not the desired behaviour since the platform + * will either reboot into the ARM monitor (or pre-loader) + * or continuously cycle thru it without U-Boot running, + * depending upon the setting of Integrator/CP switch S2-4. + * + * However it may be needed if Integrator/CP switch S2-1 + * is set OFF to boot direct into U-Boot. + * In that case comment out the line below. +#undef CONFIG_CM_INIT + */ #endif /* __CONFIG_H */ diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h new file mode 100644 index 0000000..6590f6f --- /dev/null +++ b/include/configs/kb9202.h @@ -0,0 +1,173 @@ +/* + * Rick Bronson <rick@efn.org> + * + * Configuation settings for the AT91RM9200DK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Adatped for KwikByte KB920x board from at91rm9200dk.h: 22APR2005 + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91C_MAIN_CLOCK 180000000 /* from 10 MHz crystal */ +#define AT91C_MASTER_CLOCK 60000000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ +/* Only define one of the following, based on board type */ +/* #define CONFIG_KB9200 1 KwikByte KB9202 board */ +/* #define CONFIG_KB9201 1 KwikByte KB9202 board */ +#define CONFIG_KB9202 1 /* KwikByte KB9202 board */ + +#define CONFIG_KB920x 1 /* Any KB920x board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define USE_920T_MMU 1 + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CFG_LONGHELP + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_BAUDRATE 115200 + +/* + * Hardware drivers + */ + +/* define one of these to choose the DBGU, USART0 or USART1 as console */ +#define CONFIG_DBGU +#undef CONFIG_USART0 +#undef CONFIG_USART1 + +#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ + +#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ENV_OVERWRITE 1 + +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_I2C | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP ) & \ + ~(CFG_CMD_BDI | \ + CFG_CMD_FPGA | \ + CFG_CMD_MISC)) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - (512*1024) + +#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_RETRY_COUNT 20 + +#define CFG_FLASH_BASE 0x10000000 + +#ifdef CONFIG_KB9202 +#define PHYS_FLASH_SIZE 0x1000000 +#else +#define PHYS_FLASH_SIZE 0x200000 +#endif + +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 256 + +#define CONFIG_HARD_I2C + +#define CFG_ENV_IS_IN_EEPROM + +#ifdef CONFIG_KB9202 +#define CFG_ENV_OFFSET 0x3E00 +#define CFG_ENV_SIZE 0x0200 +#else +#define CFG_ENV_OFFSET 0x1000 +#define CFG_ENV_SIZE 0x1000 +#endif +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_EEPROM_PAGE_WRITE_BITS 6 +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0 /* not used */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#define CFG_LOAD_ADDR 0x21000000 /* default load address */ + +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI + +#ifndef __ASSEMBLY__ +/*----------------------------------------------------------------------- + * Board specific extension for bd_info + * + * This structure is embedded in the global bd_info (bd_t) structure + * and can be used by the board specific code (eg board/...) + */ + +struct bd_info_ext { + /* helper variable for board environment handling + * + * env_crc_valid == 0 => uninitialised + * env_crc_valid > 0 => environment crc in flash is valid + * env_crc_valid < 0 => environment crc in flash is invalid + */ + int env_crc_valid; +}; +#endif + +#define CFG_HZ 1000 +#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ + /* AT91C_TC_TIMER_DIV1_CLOCK */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/include/configs/luan.h b/include/configs/luan.h new file mode 100644 index 0000000..0335a00 --- /dev/null +++ b/include/configs/luan.h @@ -0,0 +1,306 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * John Otken, jotken@softadvances.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * luan.h - configuration for LUAN board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_LUAN 1 /* Board is Luan */ +#define CONFIG_440SP 1 /* Specific PPC440SP support */ +#define CONFIG_4xx 1 /* PPC4xx family */ +#define CONFIG_440 1 +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) +#define CFG_SDRAM_BASE 0x00000000 /* MUST be zero */ + +#define CFG_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */ +#define CFG_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */ +#define CFG_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */ +#define CFG_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */ + +#define CFG_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */ + +#define CFG_PERIPHERAL_BASE 0xf0000000 /* internal peripherals */ + +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ + +#if CFG_LARGE_FLASH == 0xffc00000 +#define CFG_FLASH_BASE CFG_LARGE_FLASH +#else +#define CFG_FLASH_BASE CFG_SMALL_FLASH +#endif + +#undef CFG_DRAM_TEST +#if CFG_SRAM_BASE +#define CFG_KBYTES_SDRAM 1024*2 +#else +#define CFG_KBYTES_SDRAM 1024 +#endif + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in SDRAM) + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_END (8 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CFG_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#undef CONFIG_SERIAL_MULTI +#undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */ + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +/* + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_FLASH_ADDR0 0x555 +#define CFG_FLASH_ADDR1 0x2aa +#define CFG_FLASH_WORD_SIZE unsigned char + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#undef CONFIG_SPD_EEPROM /* SPD EEPROM init doesn't support DDR2 */ +#define SPD_EEPROM_ADDRESS {0x52,0x53} /* I2C SPD addresses */ +#define IIC0_DIMM0_ADDR 0x52 +#define IIC0_DIMM1_ADDR 0x53 + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=luan\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):$(netdev):off panic=1\0" \ + "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/luan/uImage\0" \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc100000\0" \ + "load=tftp 100000 /tftpboot/luan/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 +#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* needed for NetConsole */ + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#ifdef DEBUG +#define CONFIG_PANIC_HANG +#else +#define CONFIG_HW_WATCHDOG /* watchdog */ +#endif + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_CACHE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SETGETDCR | \ + CFG_CMD_SDRAM | \ + 0) + +/* this must be included AFTER the definition of CONFIG_COMMANDS */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#undef CONFIG_LYNXKDI /* support kdi files */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#if (CONFIG_COMMANDS & CFG_CMD_PCI) + +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT +#undef CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */ + +#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 9ac62c7..ad1035b 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -77,9 +77,10 @@ #define CONFIG_NETMASK 255.255.0.0 #define CONFIG_IPADDR 192.168.0.21 #define CONFIG_SERVERIP 192.168.0.250 -#define CONFIG_BOOTCOMMAND "bootm 40000" +#define CONFIG_BOOTCOMMAND "bootm 80000" #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" #define CONFIG_CMDLINE_TAG +#define CONFIG_TIMESTAMP #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ @@ -109,7 +110,7 @@ #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR 0xa8000000 /* default load address */ +#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ #define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ @@ -211,10 +212,14 @@ #define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ -/* FIXME */ +/* NOTE: many default partitioning schemes assume the kernel starts at the + * second sector, not an environment. You have been warned! + */ +#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) +#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE +#define CFG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16) /* diff --git a/include/configs/ml300.h b/include/configs/ml300.h index abad059..6762cd6 100644 --- a/include/configs/ml300.h +++ b/include/configs/ml300.h @@ -147,7 +147,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ /*----------------------------------------------------------------------- diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h new file mode 100644 index 0000000..04f1f24 --- /dev/null +++ b/include/configs/mp2usb.h @@ -0,0 +1,236 @@ +/* + * 2004-2005 Gary Jennejohn <garyj@denx.de> + * + * Modified for the MP2USB by (C) Copyright 2005 Eric Benard + * ebenard@eukrea.com + * + * Configuration settings for the MP2USB board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */ +#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ +#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ +#define CONFIG_MP2USB 1 /* on an MP2USB Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define USE_920T_MMU 1 + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CFG_ATMEL_PLL_INIT_BUG 1 +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define CFG_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define MC_PUIA_VAL 0x00000000 +#define MC_PUP_VAL 0x00000000 +#define MC_PUER_VAL 0x00000000 +#define MC_ASR_VAL 0x00000000 +#define MC_AASR_VAL 0x00000000 +#define EBI_CFGR_VAL 0x00000000 +#define SMC2_CSR_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */ +#define PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */ +#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */ + +/* sdram */ +#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define PIOC_BSR_VAL 0x00000000 +#define PIOC_PDR_VAL 0xFFFF0000 +#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define SDRC_CR_VAL 0x3211295A /* set up the SDRAM */ +#define SDRAM 0x20000000 /* address of the SDRAM */ +#define SDRAM1 0x20000020 /* address of the SDRAM */ +#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define SDRC_MR_VAL1 0x00000004 /* refresh */ +#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_BAUDRATE 115200 + +#define CFG_AT91C_BRGR_DIVISOR 33 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */ + +/* + * Hardware drivers + */ + +/* define one of these to choose the DBGU, USART0 or USART1 as console */ +#define CONFIG_DBGU +#undef CONFIG_USART0 +#undef CONFIG_USART1 + +#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ + +#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ + +#define CONFIG_USB_OHCI 1 +#define CONFIG_USB_KEYBOARD 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_AT91C_PQFP_UHPBUG 1 + +#undef CONFIG_HARD_I2C + +#ifdef CONFIG_HARD_I2C +#define CFG_I2C_SPEED 0 /* not used */ +#define CFG_I2C_SLAVE 0 /* not used */ +#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ +#define CFG_I2C_RTC_ADDR 0x32 +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW +#endif +/* still about 20 kB free with this defined */ +#define CFG_LONGHELP + +#define CONFIG_BOOTDELAY 3 + +#ifdef CONFIG_HARD_I2C +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP | \ + CFG_CMD_MISC)) +#else +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP | \ + CFG_CMD_USB | \ + CFG_CMD_CACHE) & \ + ~(CFG_CMD_BDI | \ + CFG_CMD_IMI | \ + CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_FPGA | \ + CFG_CMD_MISC | \ + CFG_CMD_LOADS )) +#define CONFIG_TIMESTAMP +#endif +#define CFG_LONGHELP + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 + +#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_RETRY_COUNT 20 +#undef CONFIG_AT91C_USE_RMII + +#define PHYS_FLASH_1 0x10000000 +#define PHYS_FLASH_SIZE 0x1000000 /* 16 megs main flash */ +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 256 +#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ +#define CFG_FLASH_LOCK_TOUT (10*CFG_HZ) /* Timeout for Flash Set Lock Bit */ +#define CFG_FLASH_UNLOCK_TOUT (10*CFG_HZ) /* Timeout for Flash Clear Lock Bits */ +#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x20000 /* after u-boot.bin */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x20000 + +#define CFG_LOAD_ADDR 0x21000000 /* default load address */ + +#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } + +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_MAXARGS 32 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ + +#define CFG_DEVICE_DEREGISTER /* needs device_deregister */ +#define LITTLEENDIAN 1 /* used by usb_ohci.c */ + +#ifndef __ASSEMBLY__ +/*----------------------------------------------------------------------- + * Board specific extension for bd_info + * + * This structure is embedded in the global bd_info (bd_t) structure + * and can be used by the board specific code (eg board/...) + */ + +struct bd_info_ext { + /* helper variable for board environment handling + * + * env_crc_valid == 0 => uninitialised + * env_crc_valid > 0 => environment crc in flash is valid + * env_crc_valid < 0 => environment crc in flash is invalid + */ + int env_crc_valid; +}; +#endif /* __ASSEMBLY__ */ + +#define CFG_HZ 1000 +#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ + /* AT91C_TC_TIMER_DIV1_CLOCK */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#define CFG_DEVICE_NULLDEV 1 /* enble null device */ +#undef CONFIG_SILENT_CONSOLE /* enable silent startup */ + +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_STOP_STR " " +#define CONFIG_AUTOBOOT_DELAY_STR "d" + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h new file mode 100644 index 0000000..5c05a74 --- /dev/null +++ b/include/configs/o2dnt.h @@ -0,0 +1,296 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 +#define CONFIG_O2DNT 1 /* ... on O2DNT board */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +/* #define CONFIG_PCI_SCAN_SHOW 1 */ + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CFG_XLB_PIPELINING 1 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_NS8382X 1 + +#define ADD_PCI_CMD CFG_CMD_PCI + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + ADD_PCI_CMD ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ +# define CFG_LOWBOOT 1 +#else +# error "TEXT_BASE must be 0xFF000000" +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "bootfile=/tftpboot/MPC5200/uImage\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if defined(CONFIG_MPC5200) +/* + * IPB Bus clocking configuration. + */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ + +#if defined(CFG_IPBSPEED_133) +/* + * PCI Bus clocking configuration + * + * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if + * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't + * been tested with a IPB Bus Clock of 66 MHz. + */ +#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#endif +#endif + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration: + * + * O2DNT board is equiped with Ramtron FRAM device FM24CL16 + * 16 Kib Ferroelectric Nonvolatile serial RAM memory + * organized as 2048 x 8 bits and addressable as eight I2C devices + * 0x50 ... 0x57 each 256 bytes in size + * + */ +#define CFG_I2C_FRAM +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +/* + * There is no write delay with FRAM, write operations are performed at bus + * speed. Thus, no status polling or write delay is needed. + */ +/*#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70*/ + + +/* + * Flash configuration + */ +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_FLASH_SIZE 0x01000000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) + +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ +#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x20000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_OVERWRITE 1 + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration + */ +/*#define CFG_GPS_PORT_CONFIG 0x10002004 */ +#define CFG_GPS_PORT_CONFIG 0x00002006 /* no CAN */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE + +#ifdef CFG_PCISPEED_66 +/* + * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash). + */ +#define CFG_BOOTCS_CFG 0x00057801 /* for pci_clk = 66 MHz */ +#else +#define CFG_BOOTCS_CFG 0x00047801 /* for pci_clk = 33 MHz */ +#endif + +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 2b0f687..a13d6a8 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -30,7 +30,7 @@ /************************************************************************ - * OCOTEA.h - configuration for IBM 440GX Ref (Ocotea) + * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea) ***********************************************************************/ #ifndef __CONFIG_H @@ -170,17 +170,17 @@ "netdev=eth0\0" \ "hostname=ocotea\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ "flash_nfs=run nfsargs addip addtty;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=/tftpboot/ocotea/uImage\0" \ @@ -211,8 +211,14 @@ #define CONFIG_PHY1_ADDR 2 #define CONFIG_PHY2_ADDR 0x10 #define CONFIG_PHY3_ADDR 0x18 +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ @@ -256,14 +262,16 @@ #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CFG_HZ 100 /* decrementer freq: 1 ms ticks */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ /*----------------------------------------------------------------------- * PCI stuff @@ -291,7 +299,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */ +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index c791603..12252ac 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -39,11 +39,8 @@ /*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */ /* Clock config to target*/ -#define PRCM_CONFIG_II 1 -/*#define PRCM_CONFIG_III 1 */ - -/* Memory configuration on board */ -/*#define CONFIG_OPTIMIZE_DDR 1 */ +#define PRCM_CONFIG_II 1 +/* #define PRCM_CONFIG_III 1 */ #include <asm/arch/omap2420.h> /* get chip and board defs */ @@ -125,11 +122,8 @@ #ifdef CFG_NAND_BOOT #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2) #else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT) #endif -/* I'd like to get to these. Snap kernel loads if we make MMC go */ - /* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_DHCP | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_I2C) */ - #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -163,7 +157,6 @@ #define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0) #define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0) - #define NAND_CTL_CLRALE(nandptr) #define NAND_CTL_SETALE(nandptr) #define NAND_CTL_CLRCLE(nandptr) @@ -171,7 +164,6 @@ #define NAND_DISABLE_CE(nand) #define NAND_ENABLE_CE(nand) - #define CONFIG_BOOTDELAY 3 #ifdef NFS_BOOT_DEFAULTS @@ -241,17 +233,21 @@ #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ #define PHYS_SDRAM_2 OMAP2420_SDRC_CS1 +#define PHYS_FLASH_SECT_SIZE SZ_128K #define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */ #define PHYS_FLASH_SIZE_1 SZ_32M #define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */ #define PHYS_FLASH_SIZE_2 SZ_32M -#define CFG_FLASH_BASE PHYS_FLASH_1 /*----------------------------------------------------------------------- * FLASH and environment organization */ +#define CFG_FLASH_BASE PHYS_FLASH_1 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ +#define CFG_MONITOR_LEN SZ_128K /* Reserve 1 sector */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE_1 } #ifdef CFG_NAND_BOOT #define CFG_ENV_IS_IN_NAND 1 @@ -259,11 +255,21 @@ #else #define CFG_ENV_ADDR (CFG_FLASH_BASE + SZ_128K) #define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE +#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */ #endif +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ + /* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (30*75*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (30*75*CFG_HZ) /* Timeout for Flash Write */ +#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ #define CFG_JFFS2_MEM_NAND diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h new file mode 100644 index 0000000..831d018 --- /dev/null +++ b/include/configs/p3p440.h @@ -0,0 +1,318 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * board/config_p3p440.h - configuration for Prodrive P3P440 + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_P3P440 1 /* Board is P3P440 */ +#define CONFIG_440GP 1 /* Specifc GP support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ + +#define CFG_USB_BASE (CFG_PERIPHERAL_BASE + 0x00000000) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/ +#define CFG_SDRAM_TABLE { \ + {(256 << 20), 0x000C4001}, /* 256MB mode 3, 13x10(4) */ \ + {(64 << 20), 0x00082001}} /* 64MB mode 2, 12x9(4) */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/*----------------------------------------------------------------------- + * I2C RTC + *----------------------------------------------------------------------*/ +#define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (PCF8594C) for environment + *----------------------------------------------------------------------*/ +#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ + /* 8 byte page write mode using */ + /* last 3 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Default configuration (environment varibles...) + *----------------------------------------------------------------------*/ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=p3p440\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/p3p440/uImage\0" \ + "kernel_addr=ff800000\0" \ + "ramdisk_addr=ff810000\0" \ + "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0x1c /* PHY address */ +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ + +#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH0 0xFF800000 +#define CFG_FLASH1 0xFF000000 +#define CFG_FLASH2 0xFE800000 +#define CFG_FLASH3 0xFE000000 +#define CFG_USB 0xF0000000 + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x03050200 +#define CFG_EBC_PB0CR (CFG_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x03050200 +#define CFG_EBC_PB1CR (CFG_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ + +/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */ +#define CFG_EBC_PB2AP 0x03050200 +#define CFG_EBC_PB2CR (CFG_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ + +/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x03050200 +#define CFG_EBC_PB3CR (CFG_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ + +/* Memory Bank 7 (USB controller) initialization */ +#define CFG_EBC_PB7AP 0x02015000 +#define CFG_EBC_PB7CR (CFG_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH3, CFG_FLASH2, CFG_FLASH1, CFG_FLASH0 } + +#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h new file mode 100644 index 0000000..ed1893f --- /dev/null +++ b/include/configs/pb1x00.h @@ -0,0 +1,189 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file contains the configuration parameters for the dbau1x00 board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ +#define CONFIG_PB1X00 1 +#define CONFIG_AU1X00 1 /* alchemy series cpu */ + +#ifdef CONFIG_PB1000 +#define CONFIG_AU1000 1 +#else +#ifdef CONFIG_PB1100 +#define CONFIG_AU1100 1 +#else +#ifdef CONFIG_PB1500 +#define CONFIG_AU1500 1 +#else +#error "No valid board set" +#endif +#endif +#endif + +#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ + +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ + +#define CONFIG_BAUDRATE 115200 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ + "panic=1\0" \ + "bootfile=/vmlinux.img\0" \ + "load=tftp 80500000 ${u-boot}\0" \ + "" +/* Boot from NFS root */ +#define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm" + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "Pb1x00 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args*/ + +#define CFG_MALLOC_LEN 128*1024 + +#define CFG_BOOTPARAMS_LEN 128*1024 + +#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */ + +#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ + +#define CFG_LOAD_ADDR 0x81000000 /* default load address */ + +#define CFG_MEMTEST_START 0x80100000 +#undef CFG_MEMTEST_START +#define CFG_MEMTEST_START 0x80200000 +#define CFG_MEMTEST_END 0x83800000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ + +#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ + +/* The following #defines are needed to get flash environment right */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) + +#define CFG_INIT_SP_OFFSET 0x4000000 + +/* We boot from this flash, selected with dip switch */ +#define CFG_FLASH_BASE PHYS_FLASH_2 + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_NOWHERE 1 + +/* Address and size of Primary Environment Sector */ +#define CFG_ENV_ADDR 0xB0030000 +#define CFG_ENV_SIZE 0x10000 + +#define CONFIG_FLASH_16BIT + +#define CONFIG_NR_DRAM_BANKS 2 + +#define CONFIG_NET_MULTI + +#define CONFIG_MEMSIZE_IN_BYTES + + +/*---USB -------------------------------------------*/ +#if 0 +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#else +#define ADD_USB_CMD 0 +#endif + +/*---ATA PCMCIA ------------------------------------*/ +#if 0 +#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ +#define CFG_PCMCIA_MEM_ADDR 0x20000000 +#define CONFIG_PCMCIA_SLOT_A + +#define CONFIG_ATAPI 1 +#define CONFIG_MAC_PARTITION 1 + +/* We run CF in "true ide" mode or a harddrive via pcmcia */ +#define CONFIG_IDE_PCMCIA 1 + +/* We only support one slot for now */ +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET 8 + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET 0 + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +#endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_ICACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 + +#define CONFIG_COMMANDS \ + (((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_PING) & \ + ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | CFG_CMD_IDE | \ + CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \ + CFG_CMD_BDI | CFG_CMD_BEDBUG)) | ADD_USB_CMD) +#include <cmd_confdefs.h> + +#endif /* __CONFIG_H */ diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h index e261e53..73aa3a8 100644 --- a/include/configs/pcu_e.h +++ b/include/configs/pcu_e.h @@ -56,8 +56,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h new file mode 100644 index 0000000..fefdb3c --- /dev/null +++ b/include/configs/pf5200.h @@ -0,0 +1,399 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * (c) 2005 esd gmbh Hannover + * + * + * from IceCube.h file + * by Reinhard Arlt reinhard.arlt@esd-electronics.com + * + *************************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_ICECUBE 1 /* ... on IceCube board */ +#define CONFIG_PF5200 1 /* ... on PF5200 board */ +#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#if 0 /* test-only */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#else +#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ +#endif +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +#define CONFIG_PCI_SCAN_SHOW 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CONFIG_MII 1 +#if 0 /* test-only !!! */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_EEPRO100 1 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_NS8382X 1 +#endif + +#define ADD_PCI_CMD CFG_CMD_PCI + +#else /* MPC5100 */ + +#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ + +#endif + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* USB */ +#if 0 +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define CONFIG_USB_STORAGE +#else +#define ADD_USB_CMD 0 +#endif + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_BSP | \ + CFG_CMD_ELF | \ + ADD_PCI_CMD ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT16 1 +#endif +#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT08 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Welcome to ParaFinder pf5200;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ + "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ + "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \ + "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \ + "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \ + "loadaddr=01000000\0" \ + "serverip=192.168.2.99\0" \ + "gatewayip=10.0.0.79\0" \ + "user=mu\0" \ + "target=pf5200.esd\0" \ + "script=pf5200.bat\0" \ + "image=/tftpboot/vxWorks_pf5200\0" \ + "ipaddr=10.0.13.196\0" \ + "netmask=255.255.0.0\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_vxworks0" + +#if defined(CONFIG_MPC5200) +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#endif +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 86000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CFG_I2C_MULTI_EEPROMS 1 +/* + * Flash configuration + */ +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_SIZE 0x02000000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000) +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 512 + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +/* + * Environment settings + */ +#if 1 /* test-only */ +#define CFG_ENV_IS_IN_FLASH 0 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OVERWRITE 1 +#else +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */ + /* total size of a CAT24WC32 is 8192 bytes */ +#define CONFIG_ENV_OVERWRITE 1 +#endif + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_UDP_CHECKSUM 1 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x01052444 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x0004DD00 + +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS1_START 0xfd000000 +#define CFG_CS1_SIZE 0x00010000 +#define CFG_CS1_CFG 0x10101410 + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +/*----------------------------------------------------------------------- + * CPLD stuff + */ +#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ +#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ + +/* CPLD program pin configuration */ +#define CFG_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */ +#define CFG_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */ +#define CFG_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */ +#define CFG_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */ + +#define JTAG_GPIO_ADDR_TMS (CFG_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */ +#define JTAG_GPIO_ADDR_TCK (CFG_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */ +#define JTAG_GPIO_ADDR_TDI (CFG_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */ +#define JTAG_GPIO_ADDR_TDO (CFG_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */ + +#define JTAG_GPIO_ADDR_CFG (CFG_MBAR + 0xB00) +#define JTAG_GPIO_CFG_SET 0x00000000 +#define JTAG_GPIO_CFG_RESET 0x00F00000 + +#define JTAG_GPIO_ADDR_EN_TMS (CFG_MBAR + 0xB04) +#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */ +#define JTAG_GPIO_TMS_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TMS (CFG_MBAR + 0xB0C) +#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */ +#define JTAG_GPIO_TMS_DDR_RESET 0x00000000 + +#define JTAG_GPIO_ADDR_EN_TCK (CFG_MBAR + 0xC00) +#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */ +#define JTAG_GPIO_TCK_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TCK (CFG_MBAR + 0xC08) +#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */ +#define JTAG_GPIO_TCK_DDR_RESET 0x00000000 + +#define JTAG_GPIO_ADDR_EN_TDI (CFG_MBAR + 0xC00) +#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */ +#define JTAG_GPIO_TDI_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TDI (CFG_MBAR + 0xC08) +#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */ +#define JTAG_GPIO_TDI_DDR_RESET 0x00000000 + +#define JTAG_GPIO_ADDR_EN_TDO (CFG_MBAR + 0xB04) +#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */ +#define JTAG_GPIO_TDO_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TDO (CFG_MBAR + 0xB0C) +#define JTAG_GPIO_TDO_DDR_SET 0x00000000 +#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h index 60b0b37..75792221 100644 --- a/include/configs/ppmc8260.h +++ b/include/configs/ppmc8260.h @@ -247,7 +247,7 @@ "echo;" \ "bootp;" \ "setenv bootargs root=/dev/ram0 rw " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" #endif /* CONFIG_BOOT_ROOT_INITRD */ @@ -256,8 +256,8 @@ "version;" \ "echo;" \ "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" #endif /* CONFIG_BOOT_ROOT_NFS */ diff --git a/include/configs/purple.h b/include/configs/purple.h index 7ffd3fd..2ecb7fb 100644 --- a/include/configs/purple.h +++ b/include/configs/purple.h @@ -55,29 +55,29 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off\0" \ - "addmisc=setenv bootargs $(bootargs) " \ - "console=ttyS0,$(baudrate) " \ - "ethaddr=$(ethaddr) " \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off\0" \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ + "ethaddr=${ethaddr} " \ "panic=1\0" \ "flash_nfs=run nfsargs addip addmisc;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addmisc;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 80500000 $(bootfile);" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 80500000 ${bootfile};" \ "run nfsargs addip addmisc;bootm\0" \ "rootpath=/opt/eldk/mips_5KC\0" \ "bootfile=/tftpboot/purple/uImage\0" \ "kernel_addr=B0040000\0" \ "ramdisk_addr=B0100000\0" \ "u-boot=/tftpboot/purple/u-boot.bin\0" \ - "load=tftp 80500000 $(u-boot)\0" \ + "load=tftp 80500000 ${u-boot}\0" \ "update=protect off 1:0-4;era 1:0-4;" \ - "cp.b 80500000 B0000000 $(filesize)\0" \ + "cp.b 80500000 B0000000 ${filesize}\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h new file mode 100644 index 0000000..e5e2772 --- /dev/null +++ b/include/configs/pxa255_idp.h @@ -0,0 +1,338 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * Copied from lubbock.h + * + * (C) Copyright 2004 + * BEC Systems <http://bec-systems.com> + * Cliff Brake <cliff.brake@gmail.com> + * Configuation settings for the Accelent/Vibren PXA255 IDP + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/pxa-regs.h> + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#define CONFIG_INIT_CRITICAL /* undef for developing */ + +/* + * define the following to enable debug blinks. A debug blink function + * must be defined in memsetup.S + */ +#undef DEBUG_BLINK_ENABLE +#undef DEBUG_BLINKC_ENABLE + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ + +#undef CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_SHARP_LM8V31 +#endif + +#define CONFIG_MMC 1 +#define BOARD_LATE_INIT 1 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * PXA250 IDP memory map information + */ + +#define IDP_CS5_ETH_OFFSET 0x03400000 + + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300) +#define CONFIG_SMC_USE_32_BIT 1 +/* #define CONFIG_SMC_USE_IOFUNCS */ + +/* the following has to be set high -- suspect something is wrong with + * with the tftp timeout routines. FIXME!!! + */ +#define CONFIG_NET_RETRY_COUNT 100 + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_DHCP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTCOMMAND "bootm 40000" +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" +#define CONFIG_CMDLINE_TAG + +/* + * Current memory map for Vibren supplied Linux images: + * + * Flash: + * 0 - 0x3ffff (size = 0x40000): bootloader + * 0x40000 - 0x13ffff (size = 0x100000): kernel + * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs + * + * RAM: + * 0xa0008000 - kernel is loaded + * 0xa3000000 - Uboot runs (48MB into RAM) + * + */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "prog_boot_mmc=" \ + "mw.b 0xa0000000 0xff 0x40000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0000000 u-boot.bin; " \ + "then " \ + "protect off 0x0 0x3ffff; " \ + "erase 0x0 0x3ffff; " \ + "cp.b 0xa0000000 0x0 0x40000; " \ + "reset;" \ + "fi\0" \ + "prog_uzImage_mmc=" \ + "mw.b 0xa0000000 0xff 0x100000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0000000 uzImage; " \ + "then " \ + "protect off 0x40000 0xfffff; " \ + "erase 0x40000 0xfffff; " \ + "cp.b 0xa0000000 0x40000 0x100000; " \ + "fi\0" \ + "prog_jffs_mmc=" \ + "mw.b 0xa0000000 0xff 0x1e00000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0000000 root.jffs; " \ + "then " \ + "protect off 0x140000 0x1f3ffff; " \ + "erase 0x140000 0x1f3ffff; " \ + "cp.b 0xa0000000 0x140000 0x1e00000; " \ + "fi\0" \ + "boot_mmc=" \ + "if mmcinit && " \ + "fatload mmc 0 0xa1000000 uzImage && " \ + "then " \ + "bootm 0xa1000000; " \ + "fi\0" \ + "prog_boot_net=" \ + "mw.b 0xa0000000 0xff 0x100000; " \ + "if bootp 0xa0000000 u-boot.bin; " \ + "then " \ + "protect off 0x0 0x3ffff; " \ + "erase 0x0 0x3ffff; " \ + "cp.b 0xa0000000 0x0 0x40000; " \ + "reset; " \ + "fi\0" \ + "prog_uzImage_net=" \ + "mw.b 0xa0000000 0xff 0x100000; " \ + "if bootp 0xa0000000 uzImage; " \ + "then " \ + "protect off 0x40000 0xfffff; " \ + "erase 0x40000 0xfffff; " \ + "cp.b 0xa0000000 0x40000 0x100000; " \ + "fi\0" \ + "prog_jffs_net=" \ + "mw.b 0xa0000000 0xff 0x1e00000; " \ + "if bootp 0xa0000000 root.jffs; " \ + "then " \ + "protect off 0x140000 0x1f3ffff; " \ + "erase 0x140000 0x1f3ffff; " \ + "cp.b 0xa0000000 0x140000 0x1e00000; " \ + "fi\0" + + +/* "erase_env=" */ +/* "protect off" */ + + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa0800000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ + +#define RTC 1 /* enable 32KHz osc */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_MMC_BASE 0xF0000000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ +#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * GPIO settings + */ + +#define CFG_GAFR0_L_VAL 0x80001005 +#define CFG_GAFR0_U_VAL 0xa5128012 +#define CFG_GAFR1_L_VAL 0x699a9558 +#define CFG_GAFR1_U_VAL 0xaaa5aa6a +#define CFG_GAFR2_L_VAL 0xaaaaaaaa +#define CFG_GAFR2_U_VAL 0x2 +#define CFG_GPCR0_VAL 0x1800400 +#define CFG_GPCR1_VAL 0x0 +#define CFG_GPCR2_VAL 0x0 +#define CFG_GPDR0_VAL 0xc1818440 +#define CFG_GPDR1_VAL 0xfcffab82 +#define CFG_GPDR2_VAL 0x1ffff +#define CFG_GPSR0_VAL 0x8000 +#define CFG_GPSR1_VAL 0x3f0002 +#define CFG_GPSR2_VAL 0x1c000 + +#define CFG_PSSR_VAL 0x20 + +/* + * Memory settings + */ +#define CFG_MSC0_VAL 0x29DCA4D2 +#define CFG_MSC1_VAL 0x43AC494C +#define CFG_MSC2_VAL 0x39D449D4 +#define CFG_MDCNFG_VAL 0x090009C9 +#define CFG_MDREFR_VAL 0x0085C017 +#define CFG_MDMRS_VAL 0x00220022 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000003 +#define CFG_MCMEM0_VAL 0x00014405 +#define CFG_MCMEM1_VAL 0x00014405 +#define CFG_MCATT0_VAL 0x00014405 +#define CFG_MCATT1_VAL 0x00014405 +#define CFG_MCIO0_VAL 0x00014405 +#define CFG_MCIO1_VAL 0x00014405 + +/* + * FLASH and environment organization + */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_MONITOR_BASE 0 +#define CFG_MONITOR_LEN 0x40000 + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* put cfg at end of flash for now */ +#define CFG_ENV_IS_IN_FLASH 1 + /* Addr of Environment Sector */ +#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000) +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x40000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/quantum.h b/include/configs/quantum.h index a38ec62..21ec5ac 100644 --- a/include/configs/quantum.h +++ b/include/configs/quantum.h @@ -65,9 +65,9 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "serial#=12345\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" + "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" /* * Select the more full-featured memory test (Barr embedded systems) diff --git a/include/configs/rmu.h b/include/configs/rmu.h index b67c418..b319cf4 100644 --- a/include/configs/rmu.h +++ b/include/configs/rmu.h @@ -52,8 +52,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 031eba5..4e0cfdb 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -329,7 +329,7 @@ "tftpboot 0x140000 /bdi2000/u-boot.bin; " \ "protect off 60000000 6003FFFF; " \ "erase 60000000 6003FFFF; " \ - "cp.b 140000 60000000 $(filesize); " \ + "cp.b 140000 60000000 ${filesize}; " \ "protect on 60000000 6003FFFF\0" \ "copyenv="\ "protect off 60040000 6004FFFF; " \ @@ -355,7 +355,7 @@ "echo\\;" \ "bootp\\;" \ "setenv bootargs root=/dev/ram0 rw quiet " \ - "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \ + "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ "run boot-hook\\;" \ "bootm\0" \ "root-on-initrd-debug="\ @@ -364,7 +364,7 @@ "echo\\;" \ "bootp\\;" \ "setenv bootargs root=/dev/ram0 rw debug " \ - "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \ + "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ "run debug-hook\\;" \ "run boot-hook\\;" \ "bootm\0" \ @@ -374,8 +374,8 @@ "echo\\;" \ "bootp\\;" \ "setenv bootargs root=/dev/nfs rw quiet " \ - "nfsroot=\\$(serverip):\\$(rootpath) " \ - "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \ + "nfsroot=\\${serverip}:\\${rootpath} " \ + "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ "run boot-hook\\;" \ "bootm\0" \ "root-on-nfs-debug="\ @@ -384,8 +384,8 @@ "echo\\;" \ "bootp\\;" \ "setenv bootargs root=/dev/nfs rw debug " \ - "nfsroot=\\$(serverip):\\$(rootpath) " \ - "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \ + "nfsroot=\\${serverip}:\\${rootpath} " \ + "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ "run debug-hook\\;" \ "run boot-hook\\;" \ "bootm\0" \ @@ -393,17 +393,17 @@ "setenv checkhostname;" \ "setenv ethaddr 00:09:70:00:00:01;" \ "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) debug " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "run debug-hook;" \ "run boot-hook;" \ "bootm\0" \ "debug-hook="\ - "echo ipaddr $(ipaddr);" \ - "echo serverip $(serverip);" \ - "echo gatewayip $(gatewayip);" \ - "echo netmask $(netmask);" \ - "echo hostname $(hostname)\0" \ + "echo ipaddr ${ipaddr};" \ + "echo serverip ${serverip};" \ + "echo gatewayip ${gatewayip};" \ + "echo netmask ${netmask};" \ + "echo hostname ${hostname}\0" \ "ana=run adc ; run dac\0" \ "adc=run adc-12 ; run adc-34\0" \ "adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \ @@ -452,7 +452,7 @@ "echo;" \ "bootp;" \ "setenv bootargs root=/dev/ram0 rw quiet " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "run boot-hook;" \ "bootm" #endif /* CONFIG_BOOT_ROOT_INITRD */ @@ -462,8 +462,8 @@ "version;" \ "echo;" \ "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) quiet " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "run boot-hook;" \ "bootm" #endif /* CONFIG_BOOT_ROOT_NFS */ diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index aeb5126..beff28a 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -46,16 +46,16 @@ #define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo" #define CONFIG_RAMBOOT \ - "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm ffc00000 ffca0000" #define CONFIG_NFSBOOT \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm ffc00000" #undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "version;echo;tftpboot $(loadaddr) $(loadfile);bootvx" /* autoboot command */ +#define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */ #define CONFIG_MII 1 /* MII PHY management */ @@ -70,17 +70,17 @@ "env_endaddr=FF03FFFF\0" \ "loadfile=vxWorks.st\0" \ "loadaddr=0x01000000\0" \ - "net_load=tftpboot $(loadaddr) $(loadfile)\0" \ + "net_load=tftpboot ${loadaddr} ${loadfile}\0" \ "uboot_startaddr=FFFC0000\0" \ "uboot_endaddr=FFFFFFFF\0" \ - "update=tftp $(loadaddr) u-boot.bin;" \ - "protect off $(uboot_startaddr) $(uboot_endaddr);" \ - "era $(uboot_startaddr) $(uboot_endaddr);" \ - "cp.b $(loadaddr) $(uboot_startaddr) $(filesize);" \ - "protect on $(uboot_startaddr) $(uboot_endaddr)\0" \ - "zapenv=protect off $(env_startaddr) $(env_endaddr);" \ - "era $(env_startaddr) $(env_endaddr);" \ - "protect on $(env_startaddr) $(env_endaddr)\0" + "update=tftp ${loadaddr} u-boot.bin;" \ + "protect off ${uboot_startaddr} ${uboot_endaddr};" \ + "era ${uboot_startaddr} ${uboot_endaddr};" \ + "cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \ + "protect on ${uboot_startaddr} ${uboot_endaddr}\0" \ + "zapenv=protect off ${env_startaddr} ${env_endaddr};" \ + "era ${env_startaddr} ${env_endaddr};" \ + "protect on ${env_startaddr} ${env_endaddr}\0" #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ @@ -226,7 +226,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h index 45e4494..180ce05 100644 --- a/include/configs/sbc8260.h +++ b/include/configs/sbc8260.h @@ -336,19 +336,19 @@ * * => printenv bootcmd * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw - * nfsroot=$(serverip):$(rootpath) - * ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;run boot-hook;bootm + * nfsroot=${serverip}:${rootpath} + * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm * * => run root-on-initrd * => printenv bootcmd * bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw - * ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;run boot-hook;bootm + * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm * * => run root-on-nfs * => printenv bootcmd * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw - * nfsroot=$(serverip):$(rootpath) - * ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;run boot-hook;bootm + * nfsroot=${serverip}:${rootpath} + * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm * */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -359,7 +359,7 @@ "tftpboot 0x140000 /bdi2000/u-boot.bin;" \ "protect off 1:0;" \ "erase 1:0;" \ - "cp.b 140000 40000000 $(filesize);" \ + "cp.b 140000 40000000 ${filesize};" \ "protect on 1:0\0" \ "zapenv="\ "protect off 1:1;" \ @@ -371,7 +371,7 @@ "echo;" \ "bootp;" \ "setenv bootargs root=/dev/ram0 rw " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "run boot-hook;" \ "bootm\0" \ "root-on-nfs="\ @@ -380,8 +380,8 @@ "echo;" \ "bootp;" \ "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "run boot-hook;" \ "bootm\0" \ "boot-hook=echo\0" @@ -398,7 +398,7 @@ "echo;" \ "bootp;" \ "setenv bootargs root=/dev/ram0 rw " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" #endif /* CONFIG_BOOT_ROOT_INITRD */ @@ -407,8 +407,8 @@ "version;" \ "echo;" \ "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" #endif /* CONFIG_BOOT_ROOT_NFS */ diff --git a/include/configs/spieval.h b/include/configs/spieval.h index 0dab9b0..96cb6e4 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -206,21 +206,21 @@ "rootpath=/opt/eldk/ppc_6xx\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 $(u-boot)\0" \ + "load=tftp 200000 ${u-boot}\0" \ "u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \ "update=protect off FC000000 FC05FFFF;" \ "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 $(filesize);" \ + "cp.b 200000 FC000000 ${filesize};" \ "protect on FC000000 FC05FFFF\0" \ "" diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index a0e1ba7..3ffe6b2 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -42,7 +42,7 @@ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */ #define CONFIG_XIN 10000000 /* 10 MHz input xtal */ @@ -574,19 +574,15 @@ typedef unsigned int led_id_t; #define CONFIG_CRC32_VERIFY 1 #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 -/* Note: change below for your network setting!!! - * This was done just to facilitate manufacturing test and configuration. - */ -#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a +/*****************************************************************************/ + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_SERVERIP 192.168.08.1 -#define CONFIG_IPADDR 192.168.08.85 -#define CONFIG_GATEWAYIP 192.168.08.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME stx_xtc -#define CONFIG_ROOTPATH /xtcroot -#define CONFIG_BOOTFILE uImage -#define CONFIG_LOADADDR 0x1000000 +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 +#define OF_CPU "PowerPC,MPC870@0" +#define OF_TBCLK (MPC8XX_HZ / 16) #endif /* __CONFIG_H */ diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h index 9589050..7118f3f 100644 --- a/include/configs/svm_sc8xx.h +++ b/include/configs/svm_sc8xx.h @@ -93,24 +93,24 @@ #undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 0x210000 $(bootfile);run nfsargs addip;bootm\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \ "bootfile=pImage-sc855t\0" \ "kernel_addr=48000000\0" \ "ramdisk_addr=48100000\0" \ "" #define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "tftpboot 0x210000 pImage-sc855t;bootm 0x210000" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h index 5a20473..dac1eb7 100644 --- a/include/configs/tb0229.h +++ b/include/configs/tb0229.h @@ -55,14 +55,14 @@ "netboot=dhcp;tftp;run netargs; bootm\0" \ "nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0" \ "localargs=setenv bootargs root=1F02 ip=dhcp\0" \ - "addmisc=setenv bootargs $(bootargs) " \ - "console=ttyS0,$(baudrate) " \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ "read-only=readonly\0" \ "netargs=run nfsargs addmisc\0" \ "flash_nfs=run nfsargs addmisc;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_local=run localargs addmisc;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "netboot_initrd=dhcp;tftp;tftp 80600000 initrd;" \ "setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\ "run addmisc;" \ @@ -73,15 +73,15 @@ "ramdisk_addr=B0100000\0" \ "u-boot=u-boot.bin\0" \ "bootfile=uImage\0" \ - "load=dhcp;tftp 80400000 $(u-boot)\0" \ - "load_kernel=dhcp;tftp 80400000 $(bootfile)\0" \ + "load=dhcp;tftp 80400000 ${u-boot}\0" \ + "load_kernel=dhcp;tftp 80400000 ${bootfile}\0" \ "update_uboot=run load;" \ "protect off BFC00000 BFC3FFFF;" \ "erase BFC00000 BFC3FFFF;" \ - "cp.b 80400000 BFC00000 $(filesize)\0" \ + "cp.b 80400000 BFC00000 ${filesize}\0" \ "update_kernel=run load_kernel;" \ "erase BFC60000 BFD5FFFF;" \ - "cp.b 80400000 BFC60000 $(filesize)\0" \ + "cp.b 80400000 BFC60000 ${filesize}\0" \ "initenv=erase bfc40000 bfc5ffff\0" \ "" /*#define CONFIG_BOOTCOMMAND "run flash_local" */ diff --git a/include/configs/trab.h b/include/configs/trab.h index 3ca0049..85ee756 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -159,10 +159,11 @@ CFG_CMD_BSP | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ - CFG_CMD_USB | \ CFG_CMD_FAT | \ + CFG_CMD_JFFS2 | \ CFG_CMD_NFS | \ - CFG_CMD_SNTP ) + CFG_CMD_SNTP | \ + CFG_CMD_USB ) #else #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CONFIG_COMMANDS_ADD_HWFLOW | \ @@ -172,10 +173,11 @@ CFG_CMD_BSP | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ - CFG_CMD_USB | \ CFG_CMD_FAT | \ + CFG_CMD_JFFS2 | \ CFG_CMD_NFS | \ - CFG_CMD_SNTP ) + CFG_CMD_SNTP | \ + CFG_CMD_USB ) #endif /* moved up */ @@ -220,22 +222,22 @@ #else /* !CFG_HUSH_PARSER */ #define CONFIG_EXTRA_ENV_SETTINGS \ "nfs_args=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "rootpath=/opt/eldk/arm_920TDI\0" \ "ram_args=setenv bootargs root=/dev/ram rw\0" \ - "add_net=setenv bootargs $(bootargs) ethaddr=$(ethaddr) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" \ - "add_misc=setenv bootargs $(bootargs) console=ttyS0 panic=1\0" \ + "add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ + "add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \ "u-boot=/tftpboot/TRAB/u-boot.bin\0" \ - "load=tftp C100000 $(u-boot)\0" \ + "load=tftp C100000 ${u-boot}\0" \ "update=protect off 0 5FFFF;era 0 5FFFF;" \ - "cp.b C100000 0 $(filesize)\0" \ + "cp.b C100000 0 ${filesize}\0" \ "loadfile=/tftpboot/TRAB/uImage\0" \ "loadaddr=c400000\0" \ - "net_load=tftpboot $(loadaddr) $(loadfile)\0" \ + "net_load=tftpboot ${loadaddr} ${loadfile}\0" \ "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \ "kernel_addr=000C0000\0" \ - "flash_nfs=run nfs_args add_net add_misc;bootm $(kernel_addr)\0" \ + "flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \ "mdm_init1=ATZ\0" \ "mdm_init2=ATS0=1\0" \ "mdm_flow_control=rts/cts\0" @@ -267,23 +269,23 @@ #else /* !CFG_HUSH_PARSER */ #define CONFIG_EXTRA_ENV_SETTINGS \ "nfs_args=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "rootpath=/opt/eldk/arm_920TDI\0" \ "ram_args=setenv bootargs root=/dev/ram rw\0" \ - "add_net=setenv bootargs $(bootargs) ethaddr=$(ethaddr) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" \ - "add_misc=setenv bootargs $(bootargs) console=ttyS0 panic=1\0" \ + "add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ + "add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \ "u-boot=/tftpboot/TRAB/u-boot.bin\0" \ - "load=tftp C100000 $(u-boot)\0" \ + "load=tftp C100000 ${u-boot}\0" \ "update=protect off 0 3FFFF;era 0 3FFFF;" \ - "cp.b C100000 0 $(filesize);" \ + "cp.b C100000 0 ${filesize};" \ "setenv filesize;saveenv\0" \ "loadfile=/tftpboot/TRAB/uImage\0" \ "loadaddr=C400000\0" \ - "net_load=tftpboot $(loadaddr) $(loadfile)\0" \ + "net_load=tftpboot ${loadaddr} ${loadfile}\0" \ "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \ "kernel_addr=000C0000\0" \ - "flash_nfs=run nfs_args add_net add_misc;bootm $(kernel_addr)\0" \ + "flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \ "mdm_init1=ATZ\0" \ "mdm_init2=ATS0=1\0" \ "mdm_flow_control=rts/cts\0" @@ -377,6 +379,20 @@ #define CFG_MONITOR_BASE CFG_FLASH_BASE #define CFG_MONITOR_LEN (256 << 10) +/* Dynamic MTD partition support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=0" + +/* production flash layout */ +#define MTDPARTS_DEFAULT "mtdparts=0:32k(Firmware1)ro," \ + "16k(Env1)," \ + "16k(Env2)," \ + "320k(Firmware2)ro," \ + "896k(Kernel)," \ + "5376k(Root-FS)," \ + "1408k(JFFS2)," \ + "-(VFD)" + /*----------------------------------------------------------------------- * FLASH and environment organization */ @@ -399,7 +415,7 @@ #define CFG_ENV_SIZE 0x4000 #define CFG_ENV_SECT_SIZE 0x20000 #else -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x8000) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) #define CFG_ENV_SIZE 0x4000 #define CFG_ENV_SECT_SIZE 0x4000 #endif diff --git a/include/configs/uc100.h b/include/configs/uc100.h index 187df71..c4e629a 100644 --- a/include/configs/uc100.h +++ b/include/configs/uc100.h @@ -68,17 +68,17 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ "flash_nfs=run nfsargs addip addtty;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/uc100/uImage\0" \ @@ -86,7 +86,7 @@ "ramdisk_addr=40100000\0" \ "load=tftp 100000 /tftpboot/uc100/u-boot.bin\0" \ "update=protect off 40700000 4073ffff;era 40700000 4073ffff;" \ - "cp.b 100000 40700000 $(filesize);" \ + "cp.b 100000 40700000 ${filesize};" \ "setenv filesize;saveenv\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h index 4c4c279..d312b65 100644 --- a/include/configs/utx8245.h +++ b/include/configs/utx8245.h @@ -70,19 +70,19 @@ "ramdisk_addr=FF800000\0" \ "u-boot_startaddr=FFB00000\0" \ "u-boot_endaddr=FFB2FFFF\0" \ - "nfsargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/nfs rw \ -nfsroot=$(nfsrootip):$(rootpath) ip=dhcp\0" \ - "ramargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/ram0\0" \ - "smargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/mtdblock1 ro\0" \ - "fwargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/sda2 ro\0" \ - "nfsboot=run nfsargs;bootm $(kernel_addr)\0" \ - "ramboot=run ramargs;bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "smboot=run smargs;bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "fwboot=run fwargs;bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "update_u-boot=tftp $(loadaddr) /bdi2000/u-boot.bin;protect off \ -$(u-boot_startaddr) $(u-boot_endaddr);era $(u-boot_startaddr) \ -$(u-boot_endaddr);cp.b $(loadaddr) $(u-boot_startaddr) $(filesize);\ -protect on $(u-boot_startaddr) $(u-boot_endaddr)" + "nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \ +nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \ + "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \ + "smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \ + "fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \ + "nfsboot=run nfsargs;bootm ${kernel_addr}\0" \ + "ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \ +${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \ +${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\ +protect on ${u-boot_startaddr} ${u-boot_endaddr}" #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/v37.h b/include/configs/v37.h index b3c6255..a2e99b5 100644 --- a/include/configs/v37.h +++ b/include/configs/v37.h @@ -65,8 +65,8 @@ #define CONFIG_BOOTCOMMAND \ "tftpboot; " \ "setenv bootargs console=tty0 " \ - "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h index 72b0a4c..c5ee78f 100644 --- a/include/configs/voiceblue.h +++ b/include/configs/voiceblue.h @@ -163,10 +163,10 @@ #define CFG_AUTOLOAD "n" /* no autoload */ #define CONFIG_PREBOOT "run setup" #define CONFIG_EXTRA_ENV_SETTINGS \ - "setup=setenv bootargs console=ttyS0,$(baudrate) " \ + "setup=setenv bootargs console=ttyS0,${baudrate} " \ "root=/dev/nfs ip=dhcp\0" \ "update=erase c000000 c03ffff; " \ - "cp.b 10400000 c000000 $(filesize)\0" + "cp.b 10400000 c000000 ${filesize}\0" #else #define CONFIG_BOOTDELAY 3 #undef CONFIG_BOOTARGS /* boot command will set bootargs */ diff --git a/include/configs/walnut.h b/include/configs/walnut.h index 3a8e61c..1171ee5 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -52,17 +52,17 @@ "netdev=eth0\0" \ "hostname=walnut\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ "flash_nfs=run nfsargs addip addtty;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=/tftpboot/walnut/uImage\0" \ @@ -163,6 +163,9 @@ #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* needed for NetConsole */ + /*----------------------------------------------------------------------- * I2C stuff *----------------------------------------------------------------------- @@ -267,7 +270,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h index 2b86337..d3e9671 100644 --- a/include/configs/yellowstone.h +++ b/include/configs/yellowstone.h @@ -1,4 +1,6 @@ /* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this * project. @@ -28,56 +30,53 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_YELLOWSTONE 1 /* Board is BAMBOO */ -#define CONFIG_440GR 1 /* Specific PPC440GR support */ - -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#undef CFG_DRAM_TEST /* disable - takes long time! */ +#define CONFIG_YOLLOWSTONE 1 /* Board is Yellowstone */ +#define CONFIG_440GR 1 /* Specific PPC440EP support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xf0000000 /* start of FLASH */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ -#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 -#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 -#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 - +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 /*Don't change either of these*/ -#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ -#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ +#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/ /*Don't change either of these*/ -#define CFG_USB_DEVICE 0x50000000 -#define CFG_NVRAM_BASE_ADDR 0x80000000 -#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) +#define CFG_USB_DEVICE 0x50000000 +#define CFG_NVRAM_BASE_ADDR 0x80000000 +#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) +#define CFG_BOOT_BASE_ADDR 0xf0000000 /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */ -#define CFG_INIT_RAM_END 0x2000 -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CFG_INIT_RAM_END (8 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ -#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */ -#define CFG_SDRAM_BANKS (2) /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ -#define CONFIG_BAUDRATE 9600 -#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 /*define this if you want console on UART1*/ #undef CONFIG_UART1_CONSOLE @@ -85,29 +84,50 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} /*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF - * The DS1558 code assumes this condition - * + * Environment *----------------------------------------------------------------------*/ -#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ -#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ +/* + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#if 1 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#endif /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -#undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ +#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */ +#define CFG_SDRAM_BANKS (2) + /*----------------------------------------------------------------------- * I2C @@ -117,44 +137,72 @@ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/ -#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ -#define CFG_ENV_IS_IN_EEPROM 1 - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - #define CFG_I2C_MULTI_EEPROMS -#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ -#define CFG_ENV_OFFSET 0x0 #define CFG_I2C_EEPROM_ADDR (0xa8>>1) #define CFG_I2C_EEPROM_ADDR_LEN 1 #define CFG_EEPROM_PAGE_WRITE_ENABLE #define CFG_EEPROM_PAGE_WRITE_BITS 3 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */ -#define CONFIG_BOOTDELAY 3 /* disable autoboot */ +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x0 +#endif /* CFG_ENV_IS_IN_EEPROM */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=yellowstone\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/yellowstone/uImage\0" \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc100000\0" \ + "load=tftp 100000 /tftpboot/yellowstone/u-boot.bin\0" \ + "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ + "cp.b 100000 fff80000 80000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_BAUDRATE 115200 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 /* required for netconsole */ -#define CONFIG_PHY1_ADDR 3 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 /* required for netconsole */ +#define CONFIG_PHY1_ADDR 3 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.0.4.251 -#define CONFIG_ETHADDR 00:10:EC:00:12:34 -#define CONFIG_ETH1ADDR 00:10:EC:00:12:35 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SERVERIP 10.0.4.115 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ /* Partitions */ #define CONFIG_MAC_PARTITION @@ -176,53 +224,20 @@ #define CONFIG_HW_WATCHDOG /* watchdog */ #endif -#ifdef CONFIG_440EP - /* Need to define POST */ -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - /* CFG_CMD_EXT2 |*/ \ - /* CFG_CMD_FAT |*/ \ - CFG_CMD_I2C | \ - /* CFG_CMD_IDE |*/ \ - CFG_CMD_IRQ | \ - /* CFG_CMD_KGDB |*/ \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_FLASH | \ - /* CFG_CMD_SPI |*/ \ - CFG_CMD_USB | \ - 0 ) & ~CFG_CMD_IMLS) -#else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - /* CFG_CMD_EXT2 |*/ \ - /* CFG_CMD_FAT |*/ \ - CFG_CMD_I2C | \ - /* CFG_CMD_IDE |*/ \ - CFG_CMD_IRQ | \ - /* CFG_CMD_KGDB |*/ \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_FLASH | \ - /* CFG_CMD_SPI |*/ \ - 0 ) & ~CFG_CMD_IMLS) -#endif +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -231,42 +246,42 @@ * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_LYNXKDI 1 /* support kdi files */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CONFIG_LYNXKDI 1 /* support kdi files */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- */ /* General PCI */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT -#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ -#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ /* * For booting Linux, the board info and command line data @@ -274,10 +289,11 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ @@ -295,4 +311,5 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + #endif /* __CONFIG_H */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 4ac930b..a67b834 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -159,17 +159,17 @@ "netdev=eth0\0" \ "hostname=yosemite\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ "flash_nfs=run nfsargs addip addtty;" \ - "bootm $(kernel_addr)\0" \ + "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=/tftpboot/yosemite/uImage\0" \ @@ -200,7 +200,9 @@ #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ /* Partitions */ #define CONFIG_MAC_PARTITION @@ -236,8 +238,12 @@ CFG_CMD_PING | \ CFG_CMD_REGINFO | \ CFG_CMD_SDRAM | \ + CFG_CMD_FAT | \ + CFG_CMD_EXT2 | \ CFG_CMD_USB ) +#define CONFIG_SUPPORT_VFAT + /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -292,7 +298,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |