diff options
Diffstat (limited to 'include/configs/sunxi-common.h')
| -rw-r--r-- | include/configs/sunxi-common.h | 94 |
1 files changed, 67 insertions, 27 deletions
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index d829899..aad22f7 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -13,6 +13,8 @@ #ifndef _SUNXI_COMMON_CONFIG_H #define _SUNXI_COMMON_CONFIG_H +#include <linux/stringify.h> + #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT /* * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the @@ -39,8 +41,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ -#define CONFIG_SYS_TEXT_BASE 0x4a000000 - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL) # define CONFIG_DW_SERIAL #endif @@ -69,10 +69,48 @@ /* CPU */ #define CONFIG_SYS_CACHELINE_SIZE 64 -/* DRAM Base */ +/* + * The DRAM Base differs between some models. We cannot use macros for the + * CONFIG_FOO defines which contain the DRAM base address since they end + * up unexpanded in include/autoconf.mk . + * + * So we have to have this #ifdef #else #endif block for these. + */ +#ifdef CONFIG_MACH_SUN9I +#define SDRAM_OFFSET(x) 0x2##x +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */ +#define CONFIG_SYS_TEXT_BASE 0x2a000000 +#define CONFIG_PRE_CON_BUF_ADDR 0x2f000000 +#define CONFIG_SYS_SPL_MALLOC_START 0x2ff00000 +#define CONFIG_SPL_BSS_START_ADDR 0x2ff80000 +#else +#define SDRAM_OFFSET(x) 0x4##x #define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */ +#define CONFIG_SYS_TEXT_BASE 0x4a000000 +#define CONFIG_PRE_CON_BUF_ADDR 0x4f000000 +#define CONFIG_SYS_SPL_MALLOC_START 0x4ff00000 +#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 +#endif + +#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KiB */ + +#ifdef CONFIG_MACH_SUN9I +/* + * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is + * slightly bigger. Note that it is possible to map the first 32 KiB of the + * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the + * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and + * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x10000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x0a000 /* 40 KiB */ +#else #define CONFIG_SYS_INIT_RAM_ADDR 0x0 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ +#endif #define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) @@ -110,8 +148,10 @@ #define CONFIG_CMD_MMC #define CONFIG_MMC_SUNXI #define CONFIG_MMC_SUNXI_SLOT 0 +#if !defined(CONFIG_SPL_NAND_SUPPORT) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ +#endif /* CONFIG_SPL_NAND_SUPPORT */ #endif /* 4MB of malloc() pool */ @@ -129,10 +169,8 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */ - /* standalone support */ -#define CONFIG_STANDALONE_LOAD_ADDR 0x42000000 +#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR /* baudrate */ #define CONFIG_BAUDRATE 115200 @@ -162,16 +200,6 @@ #define CONFIG_SPL_BOARD_LOAD_IMAGE -#ifdef CONFIG_SPL_FEL - -#define CONFIG_SPL_TEXT_BASE 0x2000 -#define CONFIG_SPL_MAX_SIZE 0x4000 /* 16 KiB */ - -#else /* CONFIG_SPL */ - -#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KiB */ - #define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */ #define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */ @@ -186,13 +214,9 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */ #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ -#endif /* CONFIG_SPL */ - /* end of 32 KiB in sram */ #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK -#define CONFIG_SYS_SPL_MALLOC_START 0x4ff00000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KiB */ /* I2C */ #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER @@ -333,6 +357,24 @@ extern int soft_i2c_gpio_scl; #define CONFIG_ENV_IS_NOWHERE #endif +#ifdef CONFIG_SPL_NAND_SUPPORT +#define CONFIG_NAND +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_NAND_SUNXI +#define CONFIG_CMD_SPL_WRITE_SIZE 0x000400 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x008000 + +/* \todo Make these parameterisable in kernel config ? */ +#define CONFIG_NAND_SUNXI_PAGE_SIZE 8192 +#define CONFIG_NAND_SUNXI_ECC_STEP 1024 +#define CONFIG_NAND_SUNXI_ECC_STRENGTH 40 +#define CONFIG_NAND_SUNXI_ADDR_CYCLES 5 + +#ifndef CONFIG_NAND_SUNXI_GPC_PORTS +#error "No NAND GPC ports defined, NAND unsupported" +#endif +#endif /* CONFIG_SPL_NAND_SUPPORT */ + #define CONFIG_MISC_INIT_R #define CONFIG_SYS_CONSOLE_IS_IN_ENV @@ -342,8 +384,6 @@ extern int soft_i2c_gpio_scl; /* Enable pre-console buffer to get complete log on the VGA console */ #define CONFIG_PRE_CONSOLE_BUFFER #define CONFIG_PRE_CON_BUF_SZ 4096 /* Aprox 2 80*25 screens */ -/* Use the room between the end of bootm_size and the framebuffer */ -#define CONFIG_PRE_CON_BUF_ADDR 0x4f000000 /* * 240M RAM (256M minimum minus space for the framebuffer), @@ -352,11 +392,11 @@ extern int soft_i2c_gpio_scl; */ #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0xf000000\0" \ - "kernel_addr_r=0x42000000\0" \ - "fdt_addr_r=0x43000000\0" \ - "scriptaddr=0x43100000\0" \ - "pxefile_addr_r=0x43200000\0" \ - "ramdisk_addr_r=0x43300000\0" + "kernel_addr_r=" __stringify(SDRAM_OFFSET(2000000)) "\0" \ + "fdt_addr_r=" __stringify(SDRAM_OFFSET(3000000)) "\0" \ + "scriptaddr=" __stringify(SDRAM_OFFSET(3100000)) "\0" \ + "pxefile_addr_r=" __stringify(SDRAM_OFFSET(3200000)) "\0" \ + "ramdisk_addr_r=" __stringify(SDRAM_OFFSET(3300000)) "\0" #ifdef CONFIG_MMC #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) |