diff options
Diffstat (limited to 'include/configs/sbc8260.h')
| -rw-r--r-- | include/configs/sbc8260.h | 280 |
1 files changed, 140 insertions, 140 deletions
diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h index b92344c..26ed557 100644 --- a/include/configs/sbc8260.h +++ b/include/configs/sbc8260.h @@ -73,7 +73,7 @@ * 0x6 0x1 66 133 266 Close Close Open * 0x6 0x2 66 133 300 Close Open Close */ -#define CFG_SBC_MODCK_H 0x05 +#define CONFIG_SYS_SBC_MODCK_H 0x05 /* Define this if you want to boot from 0x00000100. If you don't define * this, you will need to program the bootloader to 0xfff00000, and @@ -81,34 +81,34 @@ * way to do that is to program the bootloader at both addresses. * It is suggested that you just let U-Boot live at 0x00000000. */ -#define CFG_SBC_BOOT_LOW 1 +#define CONFIG_SYS_SBC_BOOT_LOW 1 /* What should the base address of the main FLASH be and how big is * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk * The main FLASH is whichever is connected to *CS0. U-Boot expects * this to be the SIMM. */ -#define CFG_FLASH0_BASE 0x40000000 -#define CFG_FLASH0_SIZE 4 +#define CONFIG_SYS_FLASH0_BASE 0x40000000 +#define CONFIG_SYS_FLASH0_SIZE 4 /* What should the base address of the secondary FLASH be and how big * is it (in Mbytes)? The secondary FLASH is whichever is connected * to *CS6. U-Boot expects this to be the on board FLASH. If you don't * want it enabled, don't define these constants. */ -#define CFG_FLASH1_BASE 0x60000000 -#define CFG_FLASH1_SIZE 2 +#define CONFIG_SYS_FLASH1_BASE 0x60000000 +#define CONFIG_SYS_FLASH1_SIZE 2 /* What should be the base address of SDRAM DIMM and how big is * it (in Mbytes)? */ -#define CFG_SDRAM0_BASE 0x00000000 -#define CFG_SDRAM0_SIZE 64 +#define CONFIG_SYS_SDRAM0_BASE 0x00000000 +#define CONFIG_SYS_SDRAM0_SIZE 64 /* What should be the base address of the LEDs and switch S0? * If you don't want them enabled, don't define this. */ -#define CFG_LED_BASE 0xa0000000 +#define CONFIG_SYS_LED_BASE 0xa0000000 /* @@ -127,11 +127,11 @@ * Monitor Stack Buffer (0x80) * 0x00F5 FFB0 Board Info Data * 0x00F6 0000 Malloc Arena - * : CFG_ENV_SECT_SIZE, 256k - * : CFG_MALLOC_LEN, 128k + * : CONFIG_ENV_SECT_SIZE, 256k + * : CONFIG_SYS_MALLOC_LEN, 128k * 0x00FC 0000 RAM Copy of Monitor Code - * : CFG_MONITOR_LEN, 256k - * 0x00FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1 + * : CONFIG_SYS_MONITOR_LEN, 256k + * 0x00FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 */ /* @@ -150,11 +150,11 @@ * Monitor Stack Buffer (0x80) * 0x03F5 FFB0 Board Info Data * 0x03F6 0000 Malloc Arena - * : CFG_ENV_SECT_SIZE, 256k - * : CFG_MALLOC_LEN, 128k + * : CONFIG_ENV_SECT_SIZE, 256k + * : CONFIG_SYS_MALLOC_LEN, 128k * 0x03FC 0000 RAM Copy of Monitor Code - * : CFG_MONITOR_LEN, 256k - * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1 + * : CONFIG_SYS_MONITOR_LEN, 256k + * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 */ @@ -220,7 +220,7 @@ * - RX clk is CLK11 * - TX clk is CLK12 */ -# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) +# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) @@ -230,10 +230,10 @@ * - Select bus for bd/buffers (see 28-13) * - Enable Full Duplex in FSMR */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) +# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +# define CONFIG_SYS_CPMFCR_RAMTYPE 0 +# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ @@ -251,8 +251,8 @@ */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F /* * Software (bit-bang) I2C driver configuration @@ -275,7 +275,7 @@ * put in the same sector as U-Boot, and changing variables * will erase U-Boot temporarily */ -#define CFG_ENV_IN_OWN_SECT 1 +#define CONFIG_ENV_IN_OWN_SECT 1 /* Define to allow the user to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -425,14 +425,14 @@ /* undef this to save memory */ -#define CFG_LONGHELP +#define CONFIG_SYS_LONGHELP /* Monitor Command Prompt */ -#define CFG_PROMPT "=> " +#define CONFIG_SYS_PROMPT "=> " -#undef CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#undef CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif /* When CONFIG_TIMESTAMP is selected, the timestamp (date and time) @@ -469,7 +469,7 @@ #undef CONFIG_WATCHDOG /* disable the watchdog */ /* Where do the internal registers live? */ -#define CFG_IMMR 0xF0000000 +#define CONFIG_SYS_IMMR 0xF0000000 /***************************************************************************** * @@ -486,37 +486,37 @@ * Miscellaneous configurable options */ #if defined(CONFIG_CMD_KGDB) -# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif /* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) -#define CFG_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x400000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_ALT_MEMTEST /* Select full-featured memory test */ -#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */ +#define CONFIG_SYS_ALT_MEMTEST /* Select full-featured memory test */ +#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */ /* the exception vector table */ /* to the end of the DRAM */ /* less monitor and malloc area */ -#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ -#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ - + CFG_MALLOC_LEN \ - + CFG_ENV_SECT_SIZE \ - + CFG_STACK_USAGE ) +#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ +#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ + + CONFIG_SYS_MALLOC_LEN \ + + CONFIG_ENV_SECT_SIZE \ + + CONFIG_SYS_STACK_USAGE ) -#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \ - - CFG_MEM_END_USAGE ) +#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \ + - CONFIG_SYS_MEM_END_USAGE ) /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* * Low Level Configuration Settings @@ -524,109 +524,109 @@ * You should know what you are doing if you make changes here. */ -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_FLASH_SIZE CFG_FLASH0_SIZE -#define CFG_SDRAM_BASE CFG_SDRAM0_BASE -#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE +#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE +#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE /*----------------------------------------------------------------------- * Hard Reset Configuration Words */ -#if defined(CFG_SBC_BOOT_LOW) -# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) +#if defined(CONFIG_SYS_SBC_BOOT_LOW) +# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) #else -# define CFG_SBC_HRCW_BOOT_FLAGS (0) -#endif /* defined(CFG_SBC_BOOT_LOW) */ +# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0) +#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ -/* get the HRCW ISB field from CFG_IMMR */ -#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \ - ((CFG_IMMR & 0x01000000) >> 7) | \ - ((CFG_IMMR & 0x00100000) >> 4) ) +/* get the HRCW ISB field from CONFIG_SYS_IMMR */ +#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \ + ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \ + ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) -#define CFG_HRCW_MASTER ( HRCW_BPS11 | \ +#define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS11 | \ HRCW_DPPC11 | \ - CFG_SBC_HRCW_IMMR | \ + CONFIG_SYS_SBC_HRCW_IMMR | \ HRCW_MMR00 | \ HRCW_LBPC11 | \ HRCW_APPC10 | \ HRCW_CS10PC00 | \ - (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \ - CFG_SBC_HRCW_BOOT_FLAGS ) + (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \ + CONFIG_SYS_SBC_HRCW_BOOT_FLAGS ) /* no slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CONFIG_SYS_HRCW_SLAVE1 0 +#define CONFIG_SYS_HRCW_SLAVE2 0 +#define CONFIG_SYS_HRCW_SLAVE3 0 +#define CONFIG_SYS_HRCW_SLAVE4 0 +#define CONFIG_SYS_HRCW_SLAVE5 0 +#define CONFIG_SYS_HRCW_SLAVE6 0 +#define CONFIG_SYS_HRCW_SLAVE7 0 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR +#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CFG_RAMBOOT is platform dependent. + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. */ -#define CFG_MONITOR_BASE CFG_FLASH0_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +# define CONFIG_SYS_RAMBOOT #endif -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH and environment organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ -#ifndef CFG_RAMBOOT -# define CFG_ENV_IS_IN_FLASH 1 +#ifndef CONFIG_SYS_RAMBOOT +# define CONFIG_ENV_IS_IN_FLASH 1 -# ifdef CFG_ENV_IN_OWN_SECT -# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) -# define CFG_ENV_SECT_SIZE 0x40000 +# ifdef CONFIG_ENV_IN_OWN_SECT +# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) +# define CONFIG_ENV_SECT_SIZE 0x40000 # else -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE) -# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -# endif /* CFG_ENV_IN_OWN_SECT */ +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) +# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ +# endif /* CONFIG_ENV_IN_OWN_SECT */ #else -# define CFG_ENV_IS_IN_NVRAM 1 -# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) -# define CFG_ENV_SIZE 0x200 -#endif /* CFG_RAMBOOT */ +# define CONFIG_ENV_IS_IN_NVRAM 1 +# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +# define CONFIG_ENV_SIZE 0x200 +#endif /* CONFIG_SYS_RAMBOOT */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ #if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /*----------------------------------------------------------------------- @@ -639,37 +639,37 @@ * * HID1 has only read-only information - nothing to set. */ -#define CFG_HID0_INIT (HID0_ICE |\ +#define CONFIG_SYS_HID0_INIT (HID0_ICE |\ HID0_DCE |\ HID0_ICFI |\ HID0_DCI |\ HID0_IFEM |\ HID0_ABE) -#define CFG_HID0_FINAL (HID0_ICE |\ +#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ HID0_IFEM |\ HID0_ABE |\ HID0_EMCP) -#define CFG_HID2 0 +#define CONFIG_SYS_HID2 0 /*----------------------------------------------------------------------- * RMR - Reset Mode Register *----------------------------------------------------------------------- */ -#define CFG_RMR 0 +#define CONFIG_SYS_RMR 0 /*----------------------------------------------------------------------- * BCR - Bus Configuration 4-25 *----------------------------------------------------------------------- */ -#define CFG_BCR (BCR_ETM) +#define CONFIG_SYS_BCR (BCR_ETM) /*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration 4-31 *----------------------------------------------------------------------- */ -#define CFG_SIUMCR (SIUMCR_DPPC11 |\ +#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\ SIUMCR_L2CPC00 |\ SIUMCR_APPC10 |\ SIUMCR_MMR00) @@ -682,7 +682,7 @@ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable */ #if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC |\ +#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ SYPCR_BMT |\ SYPCR_PBME |\ SYPCR_LBME |\ @@ -690,7 +690,7 @@ SYPCR_SWP |\ SYPCR_SWE) #else -#define CFG_SYPCR (SYPCR_SWTC |\ +#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ SYPCR_BMT |\ SYPCR_PBME |\ SYPCR_LBME |\ @@ -704,7 +704,7 @@ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, * and enable Time Counter */ -#define CFG_TMCNTSC (TMCNTSC_SEC |\ +#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ TMCNTSC_ALR |\ TMCNTSC_TCF |\ TMCNTSC_TCE) @@ -715,7 +715,7 @@ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable * Periodic timer */ -#define CFG_PISCR (PISCR_PS |\ +#define CONFIG_SYS_PISCR (PISCR_PS |\ PISCR_PTF |\ PISCR_PTE) @@ -723,13 +723,13 @@ * SCCR - System Clock Control 9-8 *----------------------------------------------------------------------- */ -#define CFG_SCCR 0 +#define CONFIG_SYS_SCCR 0 /*----------------------------------------------------------------------- * RCCR - RISC Controller Configuration 13-7 *----------------------------------------------------------------------- */ -#define CFG_RCCR 0 +#define CONFIG_SYS_RCCR 0 /* * Initialize Memory Controller: @@ -780,7 +780,7 @@ * - No data pipelining is done * - Valid */ -#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ +#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ BRx_PS_32 |\ BRx_MS_GPCM_P |\ BRx_V) @@ -799,7 +799,7 @@ * - One idle clock is inserted between a read access from the * current bank and the next access. */ -#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ ORxG_CSNT |\ ORxG_ACS_DIV1 |\ ORxG_SCY_5_CLK |\ @@ -834,12 +834,12 @@ * - No data pipelining is done * - Valid */ -#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ +#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ BRx_PS_64 |\ BRx_MS_SDRAM_P |\ BRx_V) -#define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ +#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ BRx_PS_64 |\ BRx_MS_SDRAM_P |\ BRx_V) @@ -853,8 +853,8 @@ * - Back-to-back page mode * - Internal bank interleaving within save device enabled */ -#if (CFG_SDRAM0_SIZE == 16) -#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ +#if (CONFIG_SYS_SDRAM0_SIZE == 16) +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ ORxS_BPD_2 |\ ORxS_ROWST_PBI0_A9 |\ ORxS_NUMR_11) @@ -869,8 +869,8 @@ * - Back-to-back page mode * - Internal bank interleaving within save device enabled */ -#if (CFG_SDRAM0_SIZE == 64) -#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ +#if (CONFIG_SYS_SDRAM0_SIZE == 64) +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ ORxS_BPD_4 |\ ORxS_ROWST_PBI0_A8 |\ ORxS_NUMR_12) @@ -886,7 +886,7 @@ */ #define SDRAM_SPD_ADDR 0x54 -#if (CFG_SDRAM0_SIZE == 16) +#if (CONFIG_SYS_SDRAM0_SIZE == 16) /* With a 16 MB DIMM, the PSDMR is configured as follows: * * - Bank Based Interleaving, @@ -904,7 +904,7 @@ * - earliest timing for PRECHARGE after last data was written is 1 clock, * - CAS Latency is 2. */ -#define CFG_PSDMR (PSDMR_RFEN |\ +#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ PSDMR_SDAM_A14_IS_A5 |\ PSDMR_BSMA_A16_A18 |\ PSDMR_SDA10_PBI0_A9 |\ @@ -916,7 +916,7 @@ PSDMR_CL_2) #endif -#if (CFG_SDRAM0_SIZE == 64) +#if (CONFIG_SYS_SDRAM0_SIZE == 64) /* With a 64 MB DIMM, the PSDMR is configured as follows: * * - Bank Based Interleaving, @@ -934,7 +934,7 @@ * - earliest timing for PRECHARGE after last data was written is 1 clock, * - CAS Latency is 2. */ -#define CFG_PSDMR (PSDMR_RFEN |\ +#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ PSDMR_SDAM_A14_IS_A5 |\ PSDMR_BSMA_A14_A16 |\ PSDMR_SDA10_PBI0_A9 |\ @@ -950,14 +950,14 @@ * Shoot for approximately 1MHz on the prescaler. */ #if (CONFIG_8260_CLKIN == (66 * 1000 * 1000)) -#define CFG_MPTPR MPTPR_PTP_DIV64 +#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV64 #elif (CONFIG_8260_CLKIN == (33 * 1000 * 1000)) -#define CFG_MPTPR MPTPR_PTP_DIV32 +#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 #else -#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK" -#define CFG_MPTPR MPTPR_PTP_DIV32 +#warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK" +#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 #endif -#define CFG_PSRT 14 +#define CONFIG_SYS_PSRT 14 /* Bank 4 - On board SDRAM @@ -978,7 +978,7 @@ * This expects the on board FLASH SIMM to be connected to *CS6 * It consists of 1 AM29F016A part. */ -#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) +#if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) /* BR6 is configured as follows: * @@ -992,7 +992,7 @@ * - No data pipelining is done * - Valid */ -# define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\ +# define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\ BRx_PS_8 |\ BRx_MS_GPCM_P |\ BRx_V) @@ -1011,13 +1011,13 @@ * - One idle clock is inserted between a read access from the * current bank and the next access. */ -# define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\ +# define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE) |\ ORxG_CSNT |\ ORxG_ACS_DIV1 |\ ORxG_SCY_5_CLK |\ ORxG_TRLX |\ ORxG_EHTR) -#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */ +#endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */ /*----------------------------------------------------------------------- * BR7 - Base Register @@ -1032,7 +1032,7 @@ * LEDs are at 0x00001 (write only) * switches are at 0x00001 (read only) */ -#ifdef CFG_LED_BASE +#ifdef CONFIG_SYS_LED_BASE /* BR7 is configured as follows: * @@ -1046,7 +1046,7 @@ * - No data pipelining is done * - Valid */ -# define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\ +# define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_LED_BASE & BRx_BA_MSK) |\ BRx_PS_8 |\ BRx_MS_GPCM_P |\ BRx_V) @@ -1065,13 +1065,13 @@ * - One idle clock is inserted between a read access from the * current bank and the next access. */ -# define CFG_OR7_PRELIM (ORxG_AM_MSK |\ +# define CONFIG_SYS_OR7_PRELIM (ORxG_AM_MSK |\ ORxG_CSNT |\ ORxG_ACS_DIV1 |\ ORxG_SCY_15_CLK |\ ORxG_TRLX |\ ORxG_EHTR) -#endif /* CFG_LED_BASE */ +#endif /* CONFIG_SYS_LED_BASE */ /* * Internal Definitions |