diff options
Diffstat (limited to 'include/configs/pf5200.h')
| -rw-r--r-- | include/configs/pf5200.h | 193 |
1 files changed, 97 insertions, 96 deletions
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index 66ad01f..8ca55d7 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -44,7 +44,7 @@ #define CONFIG_PF5200 1 /* ... on PF5200 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ +#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ @@ -59,7 +59,7 @@ #else #define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ #endif -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* @@ -84,7 +84,7 @@ #if 0 /* test-only !!! */ #define CONFIG_NET_MULTI 1 #define CONFIG_EEPRO100 1 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 #endif #endif @@ -127,12 +127,12 @@ #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CFG_LOWBOOT 1 -# define CFG_LOWBOOT16 1 +# define CONFIG_SYS_LOWBOOT 1 +# define CONFIG_SYS_LOWBOOT16 1 #endif #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ -# define CFG_LOWBOOT 1 -# define CFG_LOWBOOT08 1 +# define CONFIG_SYS_LOWBOOT 1 +# define CONFIG_SYS_LOWBOOT08 1 #endif /* @@ -170,36 +170,36 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif /* * I2C configuration */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ +#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ -#define CFG_I2C_SPEED 86000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F /* * EEPROM configuration */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CFG_I2C_MULTI_EEPROMS 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* * Flash configuration */ -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_SIZE 0x02000000 -#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000) -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 512 +#define CONFIG_SYS_FLASH_BASE 0xFE000000 +#define CONFIG_SYS_FLASH_SIZE 0x02000000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ /* * Environment settings @@ -220,97 +220,98 @@ /* * Memory map */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 +#define CONFIG_SYS_MBAR 0xF0000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 /* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ +#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM +#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +# define CONFIG_SYS_RAMBOOT 1 #endif -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 #define CONFIG_UDP_CHECKSUM 1 /* * GPIO configuration */ -#define CFG_GPS_PORT_CONFIG 0x01052444 +#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444 /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ +#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ #if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /* * Various low-level settings */ #if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI +#define CONFIG_SYS_HID0_FINAL HID0_ICE #else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 +#define CONFIG_SYS_HID0_INIT 0 +#define CONFIG_SYS_HID0_FINAL 0 #endif -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x0004DD00 +#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE +#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00 -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE +#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE -#define CFG_CS1_START 0xfd000000 -#define CFG_CS1_SIZE 0x00010000 -#define CFG_CS1_CFG 0x10101410 +#define CONFIG_SYS_CS1_START 0xfd000000 +#define CONFIG_SYS_CS1_SIZE 0x00010000 +#define CONFIG_SYS_CS1_CFG 0x10101410 -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 +#define CONFIG_SYS_CS_BURST 0x00000000 +#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 -#define CFG_RESET_ADDRESS 0xff000000 +#define CONFIG_SYS_RESET_ADDRESS 0xff000000 /*----------------------------------------------------------------------- * USB stuff @@ -332,71 +333,71 @@ #define CONFIG_IDE_RESET /* reset for ide supported */ #define CONFIG_IDE_PREINIT -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ -#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA +#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA /* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) /* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) +#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) +#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) /* Interval between registers */ -#define CFG_ATA_STRIDE 4 +#define CONFIG_SYS_ATA_STRIDE 4 /*----------------------------------------------------------------------- * CPLD stuff */ -#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ +#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ +#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ /* CPLD program pin configuration */ -#define CFG_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */ -#define CFG_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */ -#define CFG_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */ -#define CFG_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */ +#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */ +#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */ +#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */ +#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */ -#define JTAG_GPIO_ADDR_TMS (CFG_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */ -#define JTAG_GPIO_ADDR_TCK (CFG_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */ -#define JTAG_GPIO_ADDR_TDI (CFG_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */ -#define JTAG_GPIO_ADDR_TDO (CFG_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */ +#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */ +#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */ +#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */ +#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */ -#define JTAG_GPIO_ADDR_CFG (CFG_MBAR + 0xB00) +#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00) #define JTAG_GPIO_CFG_SET 0x00000000 #define JTAG_GPIO_CFG_RESET 0x00F00000 -#define JTAG_GPIO_ADDR_EN_TMS (CFG_MBAR + 0xB04) +#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04) #define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */ #define JTAG_GPIO_TMS_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TMS (CFG_MBAR + 0xB0C) +#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C) #define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */ #define JTAG_GPIO_TMS_DDR_RESET 0x00000000 -#define JTAG_GPIO_ADDR_EN_TCK (CFG_MBAR + 0xC00) +#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00) #define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */ #define JTAG_GPIO_TCK_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TCK (CFG_MBAR + 0xC08) +#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08) #define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */ #define JTAG_GPIO_TCK_DDR_RESET 0x00000000 -#define JTAG_GPIO_ADDR_EN_TDI (CFG_MBAR + 0xC00) +#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00) #define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */ #define JTAG_GPIO_TDI_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TDI (CFG_MBAR + 0xC08) +#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08) #define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */ #define JTAG_GPIO_TDI_DDR_RESET 0x00000000 -#define JTAG_GPIO_ADDR_EN_TDO (CFG_MBAR + 0xB04) +#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04) #define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */ #define JTAG_GPIO_TDO_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TDO (CFG_MBAR + 0xB0C) +#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C) #define JTAG_GPIO_TDO_DDR_SET 0x00000000 #define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */ |