diff options
Diffstat (limited to 'include/configs/pdnb3.h')
| -rw-r--r-- | include/configs/pdnb3.h | 176 |
1 files changed, 88 insertions, 88 deletions
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index 889207a..8b7890e 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -45,7 +45,7 @@ #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */ #define CONFIG_MII 1 /* MII PHY management */ -#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ /* * Misc configuration options @@ -53,7 +53,7 @@ #define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */ #define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ -#define CFG_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ +#define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 @@ -62,14 +62,14 @@ /* * Size of malloc() pool */ -#define CFG_MALLOC_LEN (1 << 20) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_MALLOC_LEN (1 << 20) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_BAUDRATE 115200 -#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ +#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ /* @@ -105,21 +105,21 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00010000 /* default load address */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ +#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* * Stack sizes @@ -188,84 +188,84 @@ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ -#define CFG_FLASH_BASE 0x50000000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CONFIG_SYS_FLASH_BASE 0x50000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #if defined(CONFIG_SCPU) -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */ #else -#define CFG_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */ #endif /* * Expansion bus settings */ #if defined(CONFIG_SCPU) -#define CFG_EXP_CS0 0x94d23C42 /* 8bit, max size */ +#define CONFIG_SYS_EXP_CS0 0x94d23C42 /* 8bit, max size */ #else -#define CFG_EXP_CS0 0x94913C43 /* 8bit, max size */ +#define CONFIG_SYS_EXP_CS0 0x94913C43 /* 8bit, max size */ #endif -#define CFG_EXP_CS1 0x85000043 /* 8bit, 512bytes */ +#define CONFIG_SYS_EXP_CS1 0x85000043 /* 8bit, 512bytes */ /* * SDRAM settings */ -#define CFG_SDR_CONFIG 0x18 -#define CFG_SDR_MODE_CONFIG 0x1 -#define CFG_SDRAM_REFRESH_CNT 0x81a +#define CONFIG_SYS_SDR_CONFIG 0x18 +#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 +#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a /* * FLASH and environment organization */ #if defined(CONFIG_SCPU) -#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ #endif -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ +#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ /* * The following defines are added for buggy IOP480 byte interface. * All other boards should use the standard values (CPCI405 etc.) */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ +#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ +#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ +#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) #if defined(CONFIG_SCPU) /* no redundant environment on SCPU */ -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ #else -#define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */ -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */ +#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif #if !defined(CONFIG_SCPU) /* * NAND-FLASH stuff */ -#define CFG_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 -#define CFG_NAND_BASE 0x51000000 /* NAND FLASH Base Address */ +#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */ #endif /* @@ -273,22 +273,22 @@ */ /* FPGA program pin configuration */ -#define CFG_GPIO_PRG 12 /* FPGA program pin (cpu output)*/ -#define CFG_GPIO_CLK 10 /* FPGA clk pin (cpu output) */ -#define CFG_GPIO_DATA 14 /* FPGA data pin (cpu output) */ -#define CFG_GPIO_INIT 13 /* FPGA init pin (cpu input) */ -#define CFG_GPIO_DONE 11 /* FPGA done pin (cpu input) */ +#define CONFIG_SYS_GPIO_PRG 12 /* FPGA program pin (cpu output)*/ +#define CONFIG_SYS_GPIO_CLK 10 /* FPGA clk pin (cpu output) */ +#define CONFIG_SYS_GPIO_DATA 14 /* FPGA data pin (cpu output) */ +#define CONFIG_SYS_GPIO_INIT 13 /* FPGA init pin (cpu input) */ +#define CONFIG_SYS_GPIO_DONE 11 /* FPGA done pin (cpu input) */ /* other GPIO's */ -#define CFG_GPIO_RESTORE_INT 0 -#define CFG_GPIO_RESTART_INT 1 -#define CFG_GPIO_SYS_RUNNING 2 -#define CFG_GPIO_PCI_INTA 3 -#define CFG_GPIO_PCI_INTB 4 -#define CFG_GPIO_I2C_SCL 6 -#define CFG_GPIO_I2C_SDA 7 -#define CFG_GPIO_FPGA_RESET 9 -#define CFG_GPIO_CLK_33M 15 +#define CONFIG_SYS_GPIO_RESTORE_INT 0 +#define CONFIG_SYS_GPIO_RESTART_INT 1 +#define CONFIG_SYS_GPIO_SYS_RUNNING 2 +#define CONFIG_SYS_GPIO_PCI_INTA 3 +#define CONFIG_SYS_GPIO_PCI_INTB 4 +#define CONFIG_SYS_GPIO_I2C_SCL 6 +#define CONFIG_SYS_GPIO_I2C_SDA 7 +#define CONFIG_SYS_GPIO_FPGA_RESET 9 +#define CONFIG_SYS_GPIO_CLK_33M 15 /* * I2C stuff @@ -298,23 +298,23 @@ #undef CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CFG_I2C_SPEED 83000 /* 83 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_SPEED 83000 /* 83 kHz is supposed to work */ +#define CONFIG_SYS_I2C_SLAVE 0xFE /* * Software (bit-bang) I2C driver configuration */ -#define PB_SCL (1 << CFG_GPIO_I2C_SCL) -#define PB_SDA (1 << CFG_GPIO_I2C_SDA) +#define PB_SCL (1 << CONFIG_SYS_GPIO_I2C_SCL) +#define PB_SDA (1 << CONFIG_SYS_GPIO_I2C_SDA) -#define I2C_INIT GPIO_OUTPUT_ENABLE(CFG_GPIO_I2C_SCL) -#define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CFG_GPIO_I2C_SDA) -#define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CFG_GPIO_I2C_SDA) +#define I2C_INIT GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL) +#define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA) +#define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA) #define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0) -#define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CFG_GPIO_I2C_SDA); \ - else GPIO_OUTPUT_CLEAR(CFG_GPIO_I2C_SDA) -#define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CFG_GPIO_I2C_SCL); \ - else GPIO_OUTPUT_CLEAR(CFG_GPIO_I2C_SCL) +#define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA); \ + else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA) +#define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL); \ + else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL) #define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */ /* @@ -322,28 +322,28 @@ */ #if 0 /* test-only */ #define CONFIG_RTC_DS1340 1 -#define CFG_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 #else /* M41T11 Serial Access Timekeeper(R) SRAM */ #define CONFIG_RTC_M41T11 1 -#define CFG_I2C_RTC_ADDR 0x68 -#define CFG_M41T11_BASE_YEAR 1900 /* play along with the linux driver */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */ #endif /* * Spartan3 FPGA configuration support */ -#define CFG_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */ +#define CONFIG_SYS_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */ -#define CFG_FPGA_PRG (1 << CFG_GPIO_PRG) /* FPGA program pin (cpu output)*/ -#define CFG_FPGA_CLK (1 << CFG_GPIO_CLK) /* FPGA clk pin (cpu output) */ -#define CFG_FPGA_DATA (1 << CFG_GPIO_DATA) /* FPGA data pin (cpu output) */ -#define CFG_FPGA_INIT (1 << CFG_GPIO_INIT) /* FPGA init pin (cpu input) */ -#define CFG_FPGA_DONE (1 << CFG_GPIO_DONE) /* FPGA done pin (cpu input) */ +#define CONFIG_SYS_FPGA_PRG (1 << CONFIG_SYS_GPIO_PRG) /* FPGA program pin (cpu output)*/ +#define CONFIG_SYS_FPGA_CLK (1 << CONFIG_SYS_GPIO_CLK) /* FPGA clk pin (cpu output) */ +#define CONFIG_SYS_FPGA_DATA (1 << CONFIG_SYS_GPIO_DATA) /* FPGA data pin (cpu output) */ +#define CONFIG_SYS_FPGA_INIT (1 << CONFIG_SYS_GPIO_INIT) /* FPGA init pin (cpu input) */ +#define CONFIG_SYS_FPGA_DONE (1 << CONFIG_SYS_GPIO_DONE) /* FPGA done pin (cpu input) */ /* * Cache Configuration */ -#define CFG_CACHELINE_SIZE 32 +#define CONFIG_SYS_CACHELINE_SIZE 32 #endif /* __CONFIG_H */ |