diff options
Diffstat (limited to 'include/configs/mgsuvd.h')
| -rw-r--r-- | include/configs/mgsuvd.h | 185 |
1 files changed, 126 insertions, 59 deletions
diff --git a/include/configs/mgsuvd.h b/include/configs/mgsuvd.h index 36921ed..ff52f84 100644 --- a/include/configs/mgsuvd.h +++ b/include/configs/mgsuvd.h @@ -41,13 +41,15 @@ #define CONFIG_8xx_GCLK_FREQ 66000000 -#define CFG_SMC_UCODE_PATCH 1 /* Relocate SMC1 */ -#define CFG_SMC_DPMEM_OFFSET 0x1fc0 +#define CONFIG_SYS_SMC_UCODE_PATCH 1 /* Relocate SMC1 */ +#define CONFIG_SYS_SMC_DPMEM_OFFSET 0x1fc0 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ #define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_SYS_CPM_BOOTCOUNT_ADDR 0x1eb0 /* In case of SMC relocation, the + * default value is not working */ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ @@ -89,7 +91,7 @@ #define CONFIG_BOOTCOMMAND "run flash_self" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -113,38 +115,42 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C #define CONFIG_CMD_NFS #define CONFIG_CMD_PING /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_HUSH_INIT_VAR 1 #endif #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* * Low Level Configuration Settings @@ -154,47 +160,47 @@ /*----------------------------------------------------------------------- * Internal Memory Mapped Register */ -#define CFG_IMMR 0xFFF00000 +#define CONFIG_SYS_IMMR 0xFFF00000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR +#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xf0000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE 0xf0000000 +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_FLASH_SIZE 32 -#define CFG_FLASH_CFI +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_FLASH_SIZE 32 +#define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER -#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ @@ -208,9 +214,9 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif /*----------------------------------------------------------------------- @@ -219,27 +225,27 @@ *----------------------------------------------------------------------- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze */ -#define CFG_SYPCR 0xffffff89 +#define CONFIG_SYS_SYPCR 0xffffff89 /*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration 11-6 *----------------------------------------------------------------------- */ -#define CFG_SIUMCR 0x00610480 +#define CONFIG_SYS_SIUMCR 0x00610480 /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control 11-26 *----------------------------------------------------------------------- * Clear Reference Interrupt Status, Timebase freezing enabled */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) +#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) +#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -248,9 +254,9 @@ * power management and some other internal clocks */ #define SCCR_MASK 0x01800000 -#define CFG_SCCR 0x01800000 +#define CONFIG_SYS_SCCR 0x01800000 -#define CFG_DER 0 +#define CONFIG_SYS_DER 0 /* * Init Memory Controller: @@ -264,14 +270,14 @@ * restrict access enough to keep SRAM working (if any) * but not too much to meddle with FLASH accesses */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ +#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ /* * FLASH timing: Default value of OR0 after reset */ -#define CFG_OR0_PRELIM 0xfe000954 -#define CFG_BR0_PRELIM 0xf0000401 +#define CONFIG_SYS_OR0_PRELIM 0xfe000954 +#define CONFIG_SYS_BR0_PRELIM 0xf0000401 /* * BR1 and OR1 (SDRAM) @@ -281,16 +287,16 @@ #define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */ /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 +#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 -#define CFG_OR1_PRELIM 0xfc000800 -#define CFG_BR1_PRELIM (0x000000C0 | 0x01) +#define CONFIG_SYS_OR1_PRELIM 0xfc000800 +#define CONFIG_SYS_BR1_PRELIM (0x000000C0 | 0x01) -#define CFG_MPTPR 0x0200 +#define CONFIG_SYS_MPTPR 0x0200 /* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used), 1 Write loop Cycle (not used), 1 Timer Loop Cycle */ -#define CFG_MBMR 0x10964111 -#define CFG_MAR 0x00000088 +#define CONFIG_SYS_MBMR 0x10964111 +#define CONFIG_SYS_MAR 0x00000088 /* * 4096 Rows from SDRAM example configuration @@ -299,13 +305,13 @@ * 4 Number of refresh cycles per period * 64 Refresh cycle in ms per number of rows */ -#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) +#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) /* GPIO/PIGGY on CS3 initialization values */ -#define CFG_PIGGY_BASE (0x30000000) -#define CFG_OR3_PRELIM (0xfe000d24) -#define CFG_BR3_PRELIM (0x30000401) +#define CONFIG_SYS_PIGGY_BASE (0x30000000) +#define CONFIG_SYS_OR3_PRELIM (0xfe000d24) +#define CONFIG_SYS_BR3_PRELIM (0x30000401) /* * Internal Definitions @@ -328,4 +334,65 @@ #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc/cpm/serial@a80" +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define I2C_SOFT_DECLARATIONS + +/* + * Software (bit-bang) I2C driver configuration + */ +#define I2C_BASE_DIR ((u16 *)(CONFIG_SYS_PIGGY_BASE + 0x04)) +#define I2C_BASE_PORT ((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x09)) + +#define SDA_BIT 0x40 +#define SCL_BIT 0x80 +#define SDA_CONF 0x1000 +#define SCL_CONF 0x2000 + +#define I2C_ACTIVE do {} while (0) +#define I2C_TRISTATE do {} while (0) +#define I2C_READ ((in_8(I2C_BASE_PORT) & SDA_BIT) == SDA_BIT) +#define I2C_SDA(bit) if(bit) { \ + clrbits(be16, I2C_BASE_DIR, SDA_CONF); \ + } else { \ + clrbits(8, I2C_BASE_PORT, SDA_BIT); \ + setbits(be16, I2C_BASE_DIR, SDA_CONF); \ + } +#define I2C_SCL(bit) if(bit) { \ + clrbits(be16, I2C_BASE_DIR, SCL_CONF); \ + } else { \ + clrbits(8, I2C_BASE_PORT, SCL_BIT); \ + setbits(be16, I2C_BASE_DIR, SCL_CONF); \ + } +#define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */ + +#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_I2C_CMD_TREE 1 +#define CONFIG_SYS_MAX_I2C_BUS 2 +#define CONFIG_SYS_I2C_INIT_BOARD 1 +#define CONFIG_I2C_MUX 1 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* Support the IVM EEprom */ +#define CONFIG_SYS_IVM_EEPROM_ADR 0x50 +#define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400 +#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0, 2, 4, 6} /* Sensor addresses */ +#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3 +#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) + #endif /* __CONFIG_H */ |