diff options
Diffstat (limited to 'include/configs/delta.h')
| -rw-r--r-- | include/configs/delta.h | 144 |
1 files changed, 44 insertions, 100 deletions
diff --git a/include/configs/delta.h b/include/configs/delta.h index b42a7e2..e4c8cca 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -49,7 +49,6 @@ /* * Hardware drivers */ - #undef TURN_ON_ETHERNET #ifdef TURN_ON_ETHERNET # define CONFIG_DRIVER_SMC91111 1 @@ -59,10 +58,18 @@ # undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */ #endif +#define CONFIG_HARD_I2C 1 /* required for DA9030 access */ +#define CFG_I2C_SPEED 400000 /* I2C speed */ +#define CFG_I2C_SLAVE 1 /* I2C controllers address */ +#define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */ +#define CFG_DA9030_EXTON_DELAY 100000 /* wait x us after DA9030 reset via EXTON */ +#define CFG_I2C_INIT_BOARD 1 +/* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */ + /* * select serial console configuration */ -#define CONFIG_FFUART 1 +#define CONFIG_FFUART 1 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -73,8 +80,13 @@ #ifdef TURN_ON_ETHERNET # define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) #else -# define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_ENV | CFG_CMD_NAND) \ - & ~(CFG_CMD_NET | CFG_CMD_FLASH | CFG_CMD_IMLS)) +# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_ENV \ + | CFG_CMD_NAND \ + | CFG_CMD_I2C) \ + & ~(CFG_CMD_NET \ + | CFG_CMD_FLASH \ + | CFG_CMD_IMLS)) #endif @@ -114,15 +126,19 @@ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_DEVICE_NULLDEV 1 -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ +#define CFG_MEMTEST_START 0x80400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */ #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ +#define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */ + +/* Monahans Core Frequency */ +#define CFG_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */ +#define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */ + /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } @@ -144,16 +160,16 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa1000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2 0x81000000 /* SDRAM Bank #2 */ #define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */ -#define PHYS_SDRAM_3 0xa2000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3 0x82000000 /* SDRAM Bank #3 */ #define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */ -#define PHYS_SDRAM_4 0xa3000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4 0x83000000 /* SDRAM Bank #4 */ #define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */ -#define CFG_DRAM_BASE 0xa0000000 /* at CS0 */ +#define CFG_DRAM_BASE 0x80000000 /* at CS0 */ #define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */ #undef CFG_SKIP_DRAM_SCRUB @@ -162,14 +178,13 @@ * NAND Flash */ /* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */ -#define CONFIG_NEW_NAND_CODE +#undef CFG_NAND_LEGACY + #define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */ #undef CFG_NAND1_BASE #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 -#define NAND_DELAY_US 25 /* mk@tbd: could be 0, I guess */ /* nand timeout values */ #define CFG_NAND_PROG_ERASE_TO 3000 @@ -178,16 +193,15 @@ #undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */ /* NAND Timing Parameters (in ns) */ -#define NAND_TIMING_tCH 10 -#define NAND_TIMING_tCS 0 +#define NAND_TIMING_tCH 10 +#define NAND_TIMING_tCS 0 #define NAND_TIMING_tWH 20 -#define NAND_TIMING_tWP 40 +#define NAND_TIMING_tWP 40 -#define NAND_TIMING_tRH 20 -#define NAND_TIMING_tRP 40 +#define NAND_TIMING_tRH 20 +#define NAND_TIMING_tRP 40 -#define NAND_TIMING_tR 11123 -/* #define NAND_TIMING_tWHR 110 */ +#define NAND_TIMING_tR 11123 #define NAND_TIMING_tWHR 100 #define NAND_TIMING_tAR 10 @@ -199,89 +213,19 @@ #define CONFIG_MTD_DEBUG #define CONFIG_MTD_DEBUG_VERBOSE 1 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NO_FLASH 1 -#ifndef CGF_NO_FLASH -/* these are required by the environment code */ -#define PHYS_FLASH_1 CFG_NAND0_BASE /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x04000000 /* 64 MB */ -#define PHYS_FLASH_BANK_SIZE 0x04000000 /* 64 MB Banks */ -#define PHYS_FLASH_SECT_SIZE (SECTORSIZE*1024) /* KB sectors (x2) */ -#endif - -/* - * GPIO settings - */ -#define CFG_GPSR0_VAL 0x00008000 -#define CFG_GPSR1_VAL 0x00FC0382 -#define CFG_GPSR2_VAL 0x0001FFFF -#define CFG_GPCR0_VAL 0x00000000 -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00000000 -#define CFG_GPDR0_VAL 0x0060A800 -#define CFG_GPDR1_VAL 0x00FF0382 -#define CFG_GPDR2_VAL 0x0001C000 -#define CFG_GAFR0_L_VAL 0x98400000 -#define CFG_GAFR0_U_VAL 0x00002950 -#define CFG_GAFR1_L_VAL 0x000A9558 -#define CFG_GAFR1_U_VAL 0x0005AAAA -#define CFG_GAFR2_L_VAL 0xA0000000 -#define CFG_GAFR2_U_VAL 0x00000002 - -#define CFG_PSSR_VAL 0x20 - -/* - * Memory settings - */ -#define CFG_MSC0_VAL 0x23F223F2 -#define CFG_MSC1_VAL 0x3FF1A441 -#define CFG_MSC2_VAL 0x7FF97FF1 -#define CFG_MDCNFG_VAL 0x00001AC9 -#define CFG_MDREFR_VAL 0x00018018 -#define CFG_MDMRS_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00010504 -#define CFG_MCMEM1_VAL 0x00010504 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00010504 -#define CFG_MCIO0_VAL 0x00004715 -#define CFG_MCIO1_VAL 0x00004715 - -#define _LED 0x08000010 -#define LED_BLANK 0x08000040 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 -/* - * FLASH and environment organization - */ -#ifndef CFG_NO_FLASH -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ - - -/* NOTE: many default partitioning schemes assume the kernel starts at the - * second sector, not an environment. You have been warned! - */ -#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE -#endif /* #ifndef CFG_NO_FLASH */ +#define CFG_NO_FLASH 1 -/* #define CFG_ENV_IS_NOWHERE */ #define CFG_ENV_IS_IN_NAND 1 #define CFG_ENV_OFFSET 0x40000 +#define CFG_ENV_OFFSET_REDUND 0x44000 #define CFG_ENV_SIZE 0x4000 #endif /* __CONFIG_H */ |