diff options
Diffstat (limited to 'include/configs/cradle.h')
| -rw-r--r-- | include/configs/cradle.h | 128 |
1 files changed, 64 insertions, 64 deletions
diff --git a/include/configs/cradle.h b/include/configs/cradle.h index 34a265d..e80504a 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -40,8 +40,8 @@ /* * Size of malloc() pool */ -#define CFG_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ /* * Hardware drivers @@ -89,25 +89,25 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR 0xa2000000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */ -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ +#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* * Stack sizes @@ -137,20 +137,20 @@ #define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */ #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 +#define CONFIG_SYS_DRAM_BASE 0xa0000000 +#define CONFIG_SYS_DRAM_SIZE 0x04000000 -#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* * FLASH and environment organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ /* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR 0x00020000 /* absolute address for now */ @@ -254,38 +254,38 @@ */ /* Pin direction control */ /* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */ -#define CFG_GPDR0_VAL 0xfff3bf02 -#define CFG_GPDR1_VAL 0xfbffbf83 -#define CFG_GPDR2_VAL 0x0001ffff +#define CONFIG_SYS_GPDR0_VAL 0xfff3bf02 +#define CONFIG_SYS_GPDR1_VAL 0xfbffbf83 +#define CONFIG_SYS_GPDR2_VAL 0x0001ffff /* Set and Clear registers */ -#define CFG_GPSR0_VAL 0x00400800 -#define CFG_GPSR1_VAL 0x00000480 -#define CFG_GPSR2_VAL 0x00014000 -#define CFG_GPCR0_VAL 0x00000000 -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00000000 +#define CONFIG_SYS_GPSR0_VAL 0x00400800 +#define CONFIG_SYS_GPSR1_VAL 0x00000480 +#define CONFIG_SYS_GPSR2_VAL 0x00014000 +#define CONFIG_SYS_GPCR0_VAL 0x00000000 +#define CONFIG_SYS_GPCR1_VAL 0x00000000 +#define CONFIG_SYS_GPCR2_VAL 0x00000000 /* Edge detect registers (these are set by the kernel) */ -#define CFG_GRER0_VAL 0x00000000 -#define CFG_GRER1_VAL 0x00000000 -#define CFG_GRER2_VAL 0x00000000 -#define CFG_GFER0_VAL 0x00000000 -#define CFG_GFER1_VAL 0x00000000 -#define CFG_GFER2_VAL 0x00000000 +#define CONFIG_SYS_GRER0_VAL 0x00000000 +#define CONFIG_SYS_GRER1_VAL 0x00000000 +#define CONFIG_SYS_GRER2_VAL 0x00000000 +#define CONFIG_SYS_GFER0_VAL 0x00000000 +#define CONFIG_SYS_GFER1_VAL 0x00000000 +#define CONFIG_SYS_GFER2_VAL 0x00000000 /* Alternate function registers */ -#define CFG_GAFR0_L_VAL 0x00000000 -#define CFG_GAFR0_U_VAL 0x00000010 -#define CFG_GAFR1_L_VAL 0x900a9550 -#define CFG_GAFR1_U_VAL 0x00000008 -#define CFG_GAFR2_L_VAL 0x20000000 -#define CFG_GAFR2_U_VAL 0x00000002 +#define CONFIG_SYS_GAFR0_L_VAL 0x00000000 +#define CONFIG_SYS_GAFR0_U_VAL 0x00000010 +#define CONFIG_SYS_GAFR1_L_VAL 0x900a9550 +#define CONFIG_SYS_GAFR1_U_VAL 0x00000008 +#define CONFIG_SYS_GAFR2_L_VAL 0x20000000 +#define CONFIG_SYS_GAFR2_U_VAL 0x00000002 /* * Clocks, power control and interrupts */ -#define CFG_PSSR_VAL 0x00000020 -#define CFG_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */ -#define CFG_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */ -#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */ +#define CONFIG_SYS_PSSR_VAL 0x00000020 +#define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */ +#define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */ +#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */ /* FIXME * @@ -300,30 +300,30 @@ * FIXME Can ethernet be burst read and/or write?? This is set for lubbock * Verify timings on all */ -#define CFG_MSC0_VAL 0x000023FA /* flash bank (cs0) */ -/*#define CFG_MSC1_VAL 0x00003549 / * SuperIO bank (cs2) */ -#define CFG_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */ -#define CFG_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */ +#define CONFIG_SYS_MSC0_VAL 0x000023FA /* flash bank (cs0) */ +/*#define CONFIG_SYS_MSC1_VAL 0x00003549 / * SuperIO bank (cs2) */ +#define CONFIG_SYS_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */ +#define CONFIG_SYS_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */ #ifdef REDBOOT_WAY -#define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ -#define CFG_MDMRS_VAL 0x00000000 -#define CFG_MDREFR_VAL 0x00018018 +#define CONFIG_SYS_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ +#define CONFIG_SYS_MDMRS_VAL 0x00000000 +#define CONFIG_SYS_MDREFR_VAL 0x00018018 #else -#define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ -#define CFG_MDMRS_VAL 0x00000000 -#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */ +#define CONFIG_SYS_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ +#define CONFIG_SYS_MDMRS_VAL 0x00000000 +#define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */ #endif /* * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init) */ -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00010504 -#define CFG_MCMEM1_VAL 0x00010504 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00010504 -#define CFG_MCIO0_VAL 0x00004715 -#define CFG_MCIO1_VAL 0x00004715 +#define CONFIG_SYS_MECR_VAL 0x00000000 +#define CONFIG_SYS_MCMEM0_VAL 0x00010504 +#define CONFIG_SYS_MCMEM1_VAL 0x00010504 +#define CONFIG_SYS_MCATT0_VAL 0x00010504 +#define CONFIG_SYS_MCATT1_VAL 0x00010504 +#define CONFIG_SYS_MCIO0_VAL 0x00004715 +#define CONFIG_SYS_MCIO1_VAL 0x00004715 /* Board specific defines */ |