diff options
Diffstat (limited to 'include/configs/cmc_pu2.h')
| -rw-r--r-- | include/configs/cmc_pu2.h | 74 |
1 files changed, 38 insertions, 36 deletions
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index bce5fcd..cdd308d 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -42,7 +42,7 @@ #define CONFIG_INITRD_TAG 1 #ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CFG_USE_MAIN_OSCILLATOR 1 +#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ #define MC_PUIA_VAL 0x00000000 #define MC_PUP_VAL 0x00000000 @@ -71,13 +71,15 @@ #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#else +#define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ /* * Size of malloc() pool */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_BAUDRATE 9600 @@ -97,18 +99,18 @@ #define CONFIG_HARD_I2C #ifdef CONFIG_HARD_I2C -#define CFG_I2C_SPEED 0 /* not used */ -#define CFG_I2C_SLAVE 0 /* not used */ +#define CONFIG_SYS_I2C_SPEED 0 /* not used */ +#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ #define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ -#define CFG_I2C_RTC_ADDR 0x32 -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_I2C_EEPROM_ADDR_OVERFLOW +#define CONFIG_SYS_I2C_RTC_ADDR 0x32 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW #else #define CONFIG_TIMESTAMP #endif /* still about 20 kB free with this defined */ -#define CFG_LONGHELP +#define CONFIG_SYS_LONGHELP #define CONFIG_BOOTDELAY 1 @@ -141,7 +143,7 @@ #endif -#define CFG_LONGHELP +#define CONFIG_SYS_LONGHELP #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ @@ -150,44 +152,44 @@ #define PHYS_SDRAM 0x20000000 #define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */ -#define CFG_MEMTEST_START PHYS_SDRAM -#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 #define CONFIG_DRIVER_ETHER #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_AT91C_USE_RMII -#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) -#define CFG_MAX_DATAFLASH_BANKS 2 -#define CFG_MAX_DATAFLASH_PAGES 16384 -#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ -#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ +#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 +#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ #define PHYS_FLASH_1 0x10000000 #define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ -#define CFG_FLASH_BASE PHYS_FLASH_1 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 256 -#define CFG_FLASH_ERASE_TOUT (11 * CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT ( 2 * CFG_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_FLASH_ERASE_TOUT (11 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT ( 2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x20000 /* after u-boot.bin */ -#define CFG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */ -#define CFG_ENV_SIZE (16 << 10) /* Use only 16 kB */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x20000 /* after u-boot.bin */ +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */ +#define CONFIG_ENV_SIZE (16 << 10) /* Use only 16 kB */ -#define CFG_LOAD_ADDR 0x21000000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ -#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_MAXARGS 32 /* max number of command args */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CFG_HZ 1000 -#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ /* AT91C_TC_TIMER_DIV1_CLOCK */ #define CONFIG_STACKSIZE (32*1024) /* regular stack */ |