diff options
Diffstat (limited to 'include/configs/RBC823.h')
| -rw-r--r-- | include/configs/RBC823.h | 172 |
1 files changed, 86 insertions, 86 deletions
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index aec204b..280175a 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -71,7 +71,7 @@ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -95,12 +95,12 @@ #undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */ #define CONFIG_HARD_I2C -#define CFG_I2C_SPEED 40000 -#define CFG_I2C_SLAVE 0xfe -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_WRITE_BITS 4 -#define CFG_EEPROM_WRITE_DELAY_MS 10 +#define CONFIG_SYS_I2C_SPEED 40000 +#define CONFIG_SYS_I2C_SLAVE 0xfe +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_WRITE_BITS 4 +#define CONFIG_SYS_EEPROM_WRITE_DELAY_MS 10 /* * Command line configuration. @@ -133,25 +133,25 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ -#define CFG_LOAD_ADDR 0x0100000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x0100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* * Low Level Configuration Settings @@ -161,47 +161,47 @@ /*----------------------------------------------------------------------- * Internal Memory Mapped Register */ -#define CFG_IMMR 0xFF000000 +#define CONFIG_SYS_IMMR 0xFF000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR +#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF00000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE 0xFFF00000 #if defined(DEBUG) -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */ #else -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ #endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ @@ -210,9 +210,9 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif /*----------------------------------------------------------------------- @@ -222,13 +222,13 @@ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze */ #if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ +#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else /* -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) */ -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP) +#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP) #endif /*----------------------------------------------------------------------- @@ -236,27 +236,27 @@ *----------------------------------------------------------------------- * PCMCIA config., multi-function pin tri-state */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC) +#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC) /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control 11-26 *----------------------------------------------------------------------- * Clear Reference Interrupt Status, Timebase freezing enabled */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) +#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) /*----------------------------------------------------------------------- * RTCSC - Real-Time Clock Status and Control Register 11-27 *----------------------------------------------------------------------- */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) +#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) +#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 @@ -269,7 +269,7 @@ /* * for 48 MHz, we use a 4 MHz clock * 12 */ -#define CFG_PLPRCR \ +#define CONFIG_SYS_PLPRCR \ ( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE ) /*----------------------------------------------------------------------- @@ -279,7 +279,7 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_RTDIV | SCCR_RTSEL | SCCR_CRQEN | \ +#define CONFIG_SYS_SCCR (SCCR_RTDIV | SCCR_RTSEL | SCCR_CRQEN | \ SCCR_PRQEN | SCCR_EBDF00 | \ SCCR_COM01 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD001 | \ @@ -291,14 +291,14 @@ *----------------------------------------------------------------------- * */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) +#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) +#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) +#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) +#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) /*----------------------------------------------------------------------- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) @@ -311,39 +311,39 @@ #undef CONFIG_IDE_LED /* LED for ide not supported */ #undef CONFIG_IDE_RESET /* reset for ide not supported */ -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ -#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR +#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR /* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) +#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) /* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) +#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) /* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 +#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 #endif /************************************************************ * Disk-On-Chip configuration ************************************************************/ -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ -#define CFG_DOC_SHORT_TIMEOUT -#define CFG_DOC_SUPPORT_2000 -#define CFG_DOC_SUPPORT_MILLENNIUM +#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ +#define CONFIG_SYS_DOC_SHORT_TIMEOUT +#define CONFIG_SYS_DOC_SUPPORT_2000 +#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM /*----------------------------------------------------------------------- * *----------------------------------------------------------------------- * */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 +/*#define CONFIG_SYS_DER 0x2002000F*/ +#define CONFIG_SYS_DER 0 /* * Init Memory Controller: @@ -358,18 +358,18 @@ * restrict access enough to keep SRAM working (if any) * but not too much to meddle with FLASH accesses */ -#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ +#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR) +#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR) -#define CFG_OR_TIMING_MSYS (OR_ACS_DIV1 | OR_BI) +#define CONFIG_SYS_OR_TIMING_MSYS (OR_ACS_DIV1 | OR_BI) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) +#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_MSYS) -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \ +#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_MSYS) +#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \ BR_PS_8 | BR_V) /* @@ -382,36 +382,36 @@ /* * SDRAM timing: */ -#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM) +#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM) -#define CFG_OR4_PRELIM (~(SDRAM_MAX_SIZE-1) | CFG_OR_TIMING_SDRAM ) -#define CFG_BR4_PRELIM ((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#define CONFIG_SYS_OR4_PRELIM (~(SDRAM_MAX_SIZE-1) | CONFIG_SYS_OR_TIMING_SDRAM ) +#define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) /* * Memory Periodic Timer Prescaler */ /* periodic timer for refresh */ -#define CFG_MAMR_PTA 187 /* start with divider for 48 MHz */ +#define CONFIG_SYS_MAMR_PTA 187 /* start with divider for 48 MHz */ /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ +#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ +#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ /* * MAMR settings for SDRAM */ /* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ +#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) /* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ +#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |