diff options
Diffstat (limited to 'include/configs/PK1C20.h')
| -rw-r--r-- | include/configs/PK1C20.h | 43 |
1 files changed, 42 insertions, 1 deletions
diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h index 865c69b..91e9518 100644 --- a/include/configs/PK1C20.h +++ b/include/configs/PK1C20.h @@ -52,7 +52,7 @@ #define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ #define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ #define CFG_SRAM_BASE 0x00800000 /* SRAM base addr */ -#define CFG_SRAM_SIZE 0x00200000 /* 2 MByte */ +#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ /*------------------------------------------------------------------------ * MEMORY ORGANIZATION @@ -107,6 +107,14 @@ #define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ /*------------------------------------------------------------------------ + * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for + * epcs device access is enabled. The base address is the epcs + * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. + * The register base is currently at offset 0x400 from the memory base. + *----------------------------------------------------------------------*/ +#define CFG_NIOS_EPCSBASE 0x00900400 /* EPCS register base */ + +/*------------------------------------------------------------------------ * DEBUG *----------------------------------------------------------------------*/ #undef CONFIG_ROM_STUBS /* Stubs not in ROM */ @@ -173,6 +181,36 @@ #include <cmd_confdefs.h> /*------------------------------------------------------------------------ + * COMPACT FLASH + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CONFIG_IDE_PREINIT /* Implement id_preinit */ +#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0x00900800 /* ATA base addr */ +#define CFG_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */ +#define CFG_ATA_DATA_OFFSET 0x0040 /* Data IO offset */ +#define CFG_ATA_REG_OFFSET 0x0040 /* Register offset */ +#define CFG_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */ +#define CFG_ATA_STRIDE 4 /* Width betwix addrs */ +#define CONFIG_DOS_PARTITION + +/* Board-specific cf regs */ +#define CFG_CF_PRESENT 0x00900880 /* CF Present PIO base */ +#define CFG_CF_POWER 0x00900890 /* CF Power FET PIO base*/ +#define CFG_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */ + +#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ + +/*------------------------------------------------------------------------ + * JFFS2 + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#define CFG_JFFS_CUSTOM_PART /* board defined part */ +#endif + +/*------------------------------------------------------------------------ * MISC *----------------------------------------------------------------------*/ #define CFG_LONGHELP /* Provide extended help*/ @@ -185,4 +223,7 @@ #define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ #define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + #endif /* __CONFIG_H */ |