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-rw-r--r--include/configs/PCI405.h208
1 files changed, 104 insertions, 104 deletions
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index 9cd8f5a..49fdfdd 100644
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -34,22 +34,22 @@
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_PCI405 1 /* ...on a PCI405 board */
+#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+#define CONFIG_PCI405 1 /* ...on a PCI405 board */
-#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
-#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
+#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#if 0
-#define CONFIG_PREBOOT \
- "crc32 f0207004 ffc 0;" \
- "if cmp 0 f0207000 1;" \
- "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \
+#define CONFIG_PREBOOT \
+ "crc32 f0207004 ffc 0;" \
+ "if cmp 0 f0207000 1;" \
+ "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \
"else;echo Old CRC is bad;fi"
#endif
@@ -59,8 +59,8 @@
"bootm fffc0000"
#else
#define CONFIG_BOOTCOMMAND \
- "mw.l 0 ffffffff; mw.l 4 ffffffff;" \
- "while cmp 0 4 1; do echo Waiting for Host...;done;" \
+ "mw.l 0 ffffffff; mw.l 4 ffffffff;" \
+ "while cmp 0 4 1; do echo Waiting for Host...;done;" \
"bootm 400000"
#endif
@@ -68,7 +68,7 @@
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
+#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
@@ -79,16 +79,16 @@
CFG_CMD_DATE | \
CFG_CMD_I2C | \
CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
+ CFG_CMD_EEPROM )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
-#undef CONFIG_WATCHDOG /* watchdog disabled */
+#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
+#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
/*
* Miscellaneous configurable options
@@ -96,75 +96,75 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#define CFG_HUSH_PARSER /* use "hush" command parser */
+#define CFG_HUSH_PARSER /* use "hush" command parser */
#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
+#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
-#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
-#define CFG_BASE_BAUD 691200
+#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
+#define CFG_BASE_BAUD 691200
/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE \
+#define CFG_BAUDRATE_TABLE \
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
57600, 115200, 230400, 460800, 921600 }
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#undef CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */
-#undef CONFIG_PCI_PNP /* no pci plug-and-play */
- /* resource configuration */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */
+#undef CONFIG_PCI_PNP /* no pci plug-and-play */
+ /* resource configuration */
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
+#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */
-#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */
+#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#if 0 /* test-only */
-#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
+#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
+#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
#else
-#define CFG_PCI_PTM2LA 0xef600000 /* point to internal regs */
-#define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
-#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0xef600000 /* point to internal regs */
+#define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
+#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
#endif
/*-----------------------------------------------------------------------
@@ -193,18 +193,18 @@
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
+#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
+#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
+#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
/*
* The following defines are added for buggy IOP480 byte interface.
* All other boards should use the standard values (CPCI405 etc.)
*/
-#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
-#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
-#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
+#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
+#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
+#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
-#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
@@ -217,9 +217,9 @@
#else /* Use EEPROM for environment variables */
-#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/
/* total size of a CAT24WC08 is 1024 bytes */
#endif
@@ -234,12 +234,12 @@
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
- /* last 4 bits of the address */
+ /* last 4 bits of the address */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
@@ -264,73 +264,73 @@
* External Bus Controller (EBC) Setup
*/
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CFG_EBC_PB0AP 0x92015480
-#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x92015480
+#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-/* Memory Bank 1 (NVRAM/RTC) initialization */
-#define CFG_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
-#define CFG_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
+/* Memory Bank 1 (NVRAM/RTC) initialization */
+#define CFG_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
+#define CFG_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
-/* Memory Bank 2 (CAN0, 1) initialization */
-#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-/*#define CFG_EBC_PB2AP 0x038056C0 / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+/* Memory Bank 2 (CAN0, 1) initialization */
+#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+/*#define CFG_EBC_PB2AP 0x038056C0 / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-/* Memory Bank 3 (FPGA internal) initialization */
-#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
-#define CFG_FPGA_BASE_ADDR 0xF0400000
+/* Memory Bank 3 (FPGA internal) initialization */
+#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
+#define CFG_FPGA_BASE_ADDR 0xF0400000
/*-----------------------------------------------------------------------
* FPGA stuff
*/
/* FPGA internal regs */
-#define CFG_FPGA_MODE 0x00
-#define CFG_FPGA_STATUS 0x02
-#define CFG_FPGA_TS 0x04
-#define CFG_FPGA_TS_LOW 0x06
-#define CFG_FPGA_TS_CAP0 0x10
-#define CFG_FPGA_TS_CAP0_LOW 0x12
-#define CFG_FPGA_TS_CAP1 0x14
-#define CFG_FPGA_TS_CAP1_LOW 0x16
-#define CFG_FPGA_TS_CAP2 0x18
-#define CFG_FPGA_TS_CAP2_LOW 0x1a
-#define CFG_FPGA_TS_CAP3 0x1c
-#define CFG_FPGA_TS_CAP3_LOW 0x1e
+#define CFG_FPGA_MODE 0x00
+#define CFG_FPGA_STATUS 0x02
+#define CFG_FPGA_TS 0x04
+#define CFG_FPGA_TS_LOW 0x06
+#define CFG_FPGA_TS_CAP0 0x10
+#define CFG_FPGA_TS_CAP0_LOW 0x12
+#define CFG_FPGA_TS_CAP1 0x14
+#define CFG_FPGA_TS_CAP1_LOW 0x16
+#define CFG_FPGA_TS_CAP2 0x18
+#define CFG_FPGA_TS_CAP2_LOW 0x1a
+#define CFG_FPGA_TS_CAP3 0x1c
+#define CFG_FPGA_TS_CAP3_LOW 0x1e
/* FPGA Mode Reg */
-#define CFG_FPGA_MODE_CF_RESET 0x0001
+#define CFG_FPGA_MODE_CF_RESET 0x0001
#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
-#define CFG_FPGA_MODE_TS_CLEAR 0x2000
+#define CFG_FPGA_MODE_TS_CLEAR 0x2000
/* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0 0x0001
-#define CFG_FPGA_STATUS_DIP1 0x0002
-#define CFG_FPGA_STATUS_DIP2 0x0004
-#define CFG_FPGA_STATUS_FLASH 0x0008
-#define CFG_FPGA_STATUS_TS_IRQ 0x1000
+#define CFG_FPGA_STATUS_DIP0 0x0001
+#define CFG_FPGA_STATUS_DIP1 0x0002
+#define CFG_FPGA_STATUS_DIP2 0x0004
+#define CFG_FPGA_STATUS_FLASH 0x0008
+#define CFG_FPGA_STATUS_TS_IRQ 0x1000
-#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
+#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
+#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
/* FPGA program pin configuration */
-#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
-#define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
+#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
+#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
+#define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
+#define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
-#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
-#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
-#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
+#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*
* Internal Definitions