diff options
Diffstat (limited to 'include/configs/PATI.h')
| -rw-r--r-- | include/configs/PATI.h | 114 |
1 files changed, 57 insertions, 57 deletions
diff --git a/include/configs/PATI.h b/include/configs/PATI.h index 42b155e..88e9528 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -57,7 +57,7 @@ #define CONFIG_CMD_REGINFO #define CONFIG_CMD_FLASH #define CONFIG_CMD_LOADS -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_REGINFO #define CONFIG_CMD_BDI #define CONFIG_CMD_CONSOLE @@ -87,28 +87,28 @@ /* * Miscellaneous configurable options */ -#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ #define CONFIG_PREBOOT -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "pati=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "pati=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x00010000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ +#define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } /*********************************************************************** @@ -123,41 +123,41 @@ /* * Internal Memory Mapped (This is not the IMMR content) */ -#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */ +#define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */ /* * Definitions for initial stack pointer and data area */ -#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ -#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ -#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */ -#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */ -#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */ +#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ +#define CONFIG_SYS_INIT_RAM_END (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */ +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_RAM_ADDR) - CONFIG_SYS_GBL_DATA_SIZE) /* Offset from the beginning of ram */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */ /* * Start addresses for the final memory configuration - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ -#define CFG_FLASH_BASE 0xffC00000 /* External flash */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ +#define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */ #define PCI_BASE 0x03000000 /* PCI Base (CS2) */ #define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ #define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ -#define CFG_MONITOR_BASE 0xFFF00000 -/* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */ +#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 +/* CONFIG_SYS_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */ /* This adress is given to the linker with -Ttext to */ /* locate the text section at this adress. */ -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ +#define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- @@ -166,10 +166,10 @@ * */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ #define CONFIG_ENV_IS_IN_EEPROM @@ -181,14 +181,14 @@ #undef CONFIG_ENV_IS_IN_FLASH #ifdef CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */ -#define CONFIG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */ +#define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */ #endif #define CONFIG_SPI 1 -#define CFG_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ -#define CFG_SPI_CS_BASE 0x08 /* CS3 is active low */ -#define CFG_SPI_CS_ACT 0x00 /* CS3 is active low */ +#define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ +#define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */ +#define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */ /*----------------------------------------------------------------------- * SYPCR - System Protection Control * SYPCR can only be written once after reset! @@ -197,10 +197,10 @@ */ #undef CONFIG_WATCHDOG #if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ +#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ +#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWP) #endif /* CONFIG_WATCHDOG */ @@ -209,14 +209,14 @@ *----------------------------------------------------------------------- * Clear Reference Interrupt Status, Timebase freezing enabled */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) +#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) +#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register @@ -225,7 +225,7 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF00 -#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ +#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) /*----------------------------------------------------------------------- @@ -233,7 +233,7 @@ *----------------------------------------------------------------------- * Data show cycle */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ +#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register @@ -241,47 +241,47 @@ * Set all bits to 40 Mhz * */ -#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ +#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ -#define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) +#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) /*----------------------------------------------------------------------- * UMCR - UIMB Module Configuration Register *----------------------------------------------------------------------- * */ -#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ +#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ /*----------------------------------------------------------------------- * ICTRL - I-Bus Support Control Register */ -#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ +#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ /*----------------------------------------------------------------------- * USIU - Memory Controller Register *----------------------------------------------------------------------- */ -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) -#define CFG_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) +#define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ /* SDRAM */ -#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) -#define CFG_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) +#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ /* PCI */ -#define CFG_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) -#define CFG_OR2_PRELIM (OR_ADDR_MK_FF) +#define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) +#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) /* config registers: */ -#define CFG_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) -#define CFG_OR3_PRELIM (0xffff0000) +#define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) +#define CONFIG_SYS_OR3_PRELIM (0xffff0000) -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */ +#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ /*----------------------------------------------------------------------- * DER - Timer Decrementer *----------------------------------------------------------------------- * Initialise to zero */ -#define CFG_DER 0x00000000 +#define CONFIG_SYS_DER 0x00000000 /* |