diff options
Diffstat (limited to 'include/configs/MPC8540ADS.h')
| -rw-r--r-- | include/configs/MPC8540ADS.h | 284 |
1 files changed, 144 insertions, 140 deletions
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 0f5f834..4aaad55 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -46,6 +46,7 @@ #endif #define CONFIG_PCI +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ @@ -78,20 +79,19 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ /* DDR Setup */ #define CONFIG_FSL_DDR1 @@ -101,8 +101,8 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 @@ -112,42 +112,42 @@ #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* These are used when DDR doesn't use SPD. */ -#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ -#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ -#define CFG_DDR_CS0_CONFIG 0x80000002 -#define CFG_DDR_TIMING_1 0x37344321 -#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ -#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ +#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 +#define CONFIG_SYS_DDR_TIMING_1 0x37344321 +#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ +#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ /* * SDRAM on the Local Bus */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ -#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ +#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ -#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT #else -#undef CFG_RAMBOOT +#undef CONFIG_SYS_RAMBOOT #endif #define CONFIG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO #undef CONFIG_CLOCKS_IN_MHZ @@ -158,7 +158,7 @@ /* * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. * * For BR2, need: * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 @@ -170,14 +170,14 @@ * 0 4 8 12 16 20 24 28 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 * - * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into * FIXME: the top 17 bits of BR2. */ -#define CFG_BR2_PRELIM 0xf0001861 +#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /* - * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. * * For OR2, need: * 64MB mask for AM, OR2[0:7] = 1111 1100 @@ -190,103 +190,102 @@ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 */ -#define CFG_OR2_PRELIM 0xfc006901 +#define CONFIG_SYS_OR2_PRELIM 0xfc006901 -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ +#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ /* * LSDMR masks */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR5 \ - | CFG_LBC_LSDMR_PRETOACT3 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC2 \ - | CFG_LBC_LSDMR_CL3 \ - | CFG_LBC_LSDMR_RFEN \ +#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CONFIG_SYS_LBC_LSDMR_RFCR5 (3 << (31 - 16)) +#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CONFIG_SYS_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) +#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CONFIG_SYS_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) +#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CONFIG_SYS_LBC_LSDMR_WRC2 (2 << (31 - 27)) +#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CONFIG_SYS_LBC_LSDMR_BUFCMD (1 << (31 - 29)) +#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_BSMA1516 \ + | CONFIG_SYS_LBC_LSDMR_RFCR5 \ + | CONFIG_SYS_LBC_LSDMR_PRETOACT3 \ + | CONFIG_SYS_LBC_LSDMR_ACTTORW3 \ + | CONFIG_SYS_LBC_LSDMR_BL8 \ + | CONFIG_SYS_LBC_LSDMR_WRC2 \ + | CONFIG_SYS_LBC_LSDMR_CL3 \ + | CONFIG_SYS_LBC_LSDMR_RFEN \ ) /* * SDRAM Controller configuration sequence. */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) +#define CONFIG_SYS_LBC_LSDMR_1 ( CONFIG_SYS_LBC_LSDMR_COMMON \ + | CONFIG_SYS_LBC_LSDMR_OP_PCHALL) +#define CONFIG_SYS_LBC_LSDMR_2 ( CONFIG_SYS_LBC_LSDMR_COMMON \ + | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_3 ( CONFIG_SYS_LBC_LSDMR_COMMON \ + | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_4 ( CONFIG_SYS_LBC_LSDMR_COMMON \ + | CONFIG_SYS_LBC_LSDMR_OP_MRW) +#define CONFIG_SYS_LBC_LSDMR_5 ( CONFIG_SYS_LBC_LSDMR_COMMON \ + | CONFIG_SYS_LBC_LSDMR_OP_NORMAL) /* * 32KB, 8-bit wide for ADS config reg */ -#define CFG_BR4_PRELIM 0xf8000801 -#define CFG_OR4_PRELIM 0xffffe1f1 -#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) +#define CONFIG_SYS_BR4_PRELIM 0xf8000801 +#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 +#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CFG_BAUDRATE_TABLE \ +#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) /* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif /* pass open firmware flat tree */ @@ -294,8 +293,8 @@ #define CONFIG_OF_BOARD_SETUP 1 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 -#define CFG_64BIT_VSPRINTF 1 -#define CFG_64BIT_STRTOUL 1 +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 /* * I2C @@ -303,26 +302,29 @@ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CONFIG_SYS_I2C_OFFSET 0x3000 /* RapidIO MMU */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ +#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ +#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ +#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0x00000000 -#define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) @@ -339,7 +341,7 @@ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #endif /* CONFIG_PCI */ @@ -380,20 +382,20 @@ /* * Environment */ -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #define CONFIG_ENV_SIZE 0x2000 #else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 #endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ /* @@ -413,13 +415,15 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_SETEXPR #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI #endif -#if defined(CFG_RAMBOOT) - #undef CONFIG_CMD_ENV +#if defined(CONFIG_SYS_RAMBOOT) + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif @@ -429,28 +433,28 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ /* * Internal Definitions |