diff options
Diffstat (limited to 'include/configs/MPC8349EMDS.h')
| -rw-r--r-- | include/configs/MPC8349EMDS.h | 327 |
1 files changed, 201 insertions, 126 deletions
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 541d2f4..c76455a 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -66,7 +66,7 @@ #define CONFIG_SYS_IMMR 0xE0000000 -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00100000 @@ -105,11 +105,11 @@ */ #undef CONFIG_DDR_32BIT -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ + | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING /* @@ -129,31 +129,35 @@ #define CONFIG_SYS_DDR_SIZE 256 /* MB */ #if defined(CONFIG_DDR_II) #define CONFIG_SYS_DDRCDR 0x80080001 -#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x38357322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +#define CONFIG_SYS_DDR_TIMING_0 0x00220802 +#define CONFIG_SYS_DDR_TIMING_1 0x38357322 +#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 #define CONFIG_SYS_DDR_MODE 0x47d00432 #define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 +#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 #else -#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) +#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) #define CONFIG_SYS_DDR_TIMING_1 0x36332321 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ #if defined(CONFIG_DDR_32BIT) /* set burst length to 8 for 32-bit data path */ -#define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ + /* DLL,normal,seq,4/2.5, 8 burst len */ +#define CONFIG_SYS_DDR_MODE 0x00000023 #else /* the default burst length is 4 - for 64-bit data path */ -#define CONFIG_SYS_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ + /* DLL,normal,seq,4/2.5, 4 burst len */ +#define CONFIG_SYS_DDR_MODE 0x00000022 #endif #endif #endif @@ -167,24 +171,33 @@ /* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ +#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ - BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + + /* window base at flash base */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ #undef CONFIG_SYS_FLASH_CHECKSUM #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ @@ -201,21 +214,33 @@ /* * BCSR register on local bus 32KB, 8-bit wide for MDS config reg */ -#define CONFIG_SYS_BCSR 0xE2400000 -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ -#define CONFIG_SYS_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ +#define CONFIG_SYS_BCSR 0xE2400000 + /* Access window base at BCSR base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V) + /* 0x00000801 */ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_CLEAR \ + | OR_GPCM_EHTR_CLEAR) + /* 0xFFFFE8F0 */ #define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* * Local Bus LCRR and LBCR regs @@ -223,8 +248,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* @@ -248,14 +273,15 @@ * * 0 4 8 12 16 20 24 28 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. */ -#define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000 -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ + | BR_PS_32 /* 32-bit port */ \ + | BR_MS_SDRAM /* MSEL = SDRAM */ \ + | BR_V) /* Valid */ + /* 0xF0001861 */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) /* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. @@ -271,20 +297,26 @@ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 */ -#define CONFIG_SYS_OR2_PRELIM 0xFC006901 +#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ + | OR_SDRAM_XAM \ + | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ + | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ + | OR_SDRAM_EAD) + /* 0xFC006901 */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ + /* LB sdram refresh timer, about 6us */ +#define CONFIG_SYS_LBC_LSRT 0x32000000 + /* LB refresh timer prescal, 266MHz/32 */ +#define CONFIG_SYS_LBC_MRTPR 0x20000000 -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFEN \ +#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ | LSDMR_BSMA1516 \ | LSDMR_RFCR8 \ | LSDMR_PRETOACT6 \ | LSDMR_ACTTORW3 \ | LSDMR_BL8 \ | LSDMR_WRC3 \ - | LSDMR_CL3 \ - ) + | LSDMR_CL3) /* * SDRAM Controller configuration sequence. @@ -306,7 +338,7 @@ #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) @@ -315,7 +347,7 @@ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif @@ -325,15 +357,15 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 /* SPI */ #define CONFIG_MPC8XXX_SPI @@ -346,9 +378,9 @@ /* TSEC */ #define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) #define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) /* USB */ #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ @@ -363,9 +395,9 @@ #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE @@ -373,9 +405,9 @@ #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) @@ -406,14 +438,14 @@ /* * TSEC configuration */ -#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ #if defined(CONFIG_TSEC_ENET) #define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 @@ -430,15 +462,16 @@ /* * Configure on-board RTC */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ /* * Environment */ #ifndef CONFIG_SYS_RAMBOOT #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + #define CONFIG_ENV_ADDR \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CONFIG_ENV_SIZE 0x2000 @@ -447,7 +480,7 @@ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #else - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ + #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 @@ -496,22 +529,25 @@ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + /* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + /* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ + /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ @@ -564,7 +600,7 @@ HRCWH_SW_WATCHDOG_DISABLE |\ HRCWH_ROM_LOC_LOCAL_16BIT |\ HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII ) + HRCWH_TSEC2M_IN_GMII) #else #if defined(PCI_64BIT) #define CONFIG_SYS_HRCW_HIGH (\ @@ -578,7 +614,7 @@ HRCWH_SW_WATCHDOG_DISABLE |\ HRCWH_ROM_LOC_LOCAL_16BIT |\ HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII ) + HRCWH_TSEC2M_IN_GMII) #else #define CONFIG_SYS_HRCW_HIGH (\ HRCWH_PCI_HOST |\ @@ -591,7 +627,7 @@ HRCWH_SW_WATCHDOG_DISABLE |\ HRCWH_ROM_LOC_LOCAL_16BIT |\ HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII ) + HRCWH_TSEC2M_IN_GMII) #endif /* PCI_64BIT */ #endif /* CONFIG_PCISLAVE */ @@ -599,7 +635,7 @@ * System performance */ #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ @@ -610,28 +646,44 @@ #define CONFIG_SYS_SICRL SICRL_LDP_A #define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ + | HID0_ENABLE_INSTRUCTION_CACHE) -/* #define CONFIG_SYS_HID0_FINAL (\ +/* #define CONFIG_SYS_HID0_FINAL (\ HID0_ENABLE_INSTRUCTION_CACHE |\ HID0_ENABLE_M_BIT |\ - HID0_ENABLE_ADDRESS_BROADCAST ) */ + HID0_ENABLE_ADDRESS_BROADCAST) */ #define CONFIG_SYS_HID2 HID2_HBE #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ + | BATL_PP_RW \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) /* PCI @ 0x80000000 */ #ifdef CONFIG_PCI -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ + | BATL_PP_RW \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ + | BATL_PP_RW \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) #else #define CONFIG_SYS_IBAT1L (0) #define CONFIG_SYS_IBAT1U (0) @@ -640,10 +692,21 @@ #endif #ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ + | BATL_PP_RW \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ + | BATL_PP_RW \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) #else #define CONFIG_SYS_IBAT3L (0) #define CONFIG_SYS_IBAT3U (0) @@ -652,13 +715,24 @@ #endif /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ + | BATL_PP_RW \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT6L (0xF0000000 \ + | BATL_PP_RW \ + | BATL_MEMCOHERENCE \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT6U (0xF0000000 \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) #define CONFIG_SYS_IBAT7L (0) #define CONFIG_SYS_IBAT7U (0) @@ -699,10 +773,10 @@ #define CONFIG_ROOTPATH "/nfsroot/rootfs" #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 @@ -728,28 +802,29 @@ "bootm\0" \ "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ "update=protect off fe000000 fe03ffff; " \ - "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ + "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ "upd=run load update\0" \ "fdtaddr=780000\0" \ "fdtfile=mpc834x_mds.dtb\0" \ "" -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ + "$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #define CONFIG_BOOTCOMMAND "run flash_self" |