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Diffstat (limited to 'include/configs/MPC8266ADS.h')
-rw-r--r--include/configs/MPC8266ADS.h9
1 files changed, 0 insertions, 9 deletions
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index d6dd73b..306ee49 100644
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -141,11 +141,9 @@
*/
#define SPD_EEPROM_ADDRESS 0x50
-
#define CONFIG_8260_CLKIN 66000000 /* in Hz */
#define CONFIG_BAUDRATE 115200
-
/*
* Command line configuration.
*/
@@ -214,8 +212,6 @@
CONFIG_BOOTP_BOOTFILESIZE | \
CONFIG_BOOTP_DNS)
-
-
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#if defined(CONFIG_CMD_KGDB)
@@ -285,7 +281,6 @@
#define SDRAM_SPD_ADDR 0x50
-
/*-----------------------------------------------------------------------
* BR2,BR3 - Base Register
* Ref: Section 10.3.1 on page 10-14
@@ -383,7 +378,6 @@
#error "INVALID SDRAM CONFIGURATION"
#endif
-
#define RS232EN_1 0x02000002
#define RS232EN_2 0x01000001
#define FETHIEN 0x08000008
@@ -395,7 +389,6 @@
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */
/* 0x0EB2B645 */
#define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\
@@ -452,13 +445,11 @@
# define CFG_ENV_SIZE 0x200
#endif /* CFG_RAMBOOT */
-
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-
/*-----------------------------------------------------------------------
* HIDx - Hardware Implementation-dependent Registers 2-11
*-----------------------------------------------------------------------