diff options
Diffstat (limited to 'include/configs/HH405.h')
| -rw-r--r-- | include/configs/HH405.h | 97 |
1 files changed, 44 insertions, 53 deletions
diff --git a/include/configs/HH405.h b/include/configs/HH405.h index dc40ebc..8967b3f 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -98,26 +98,40 @@ #define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */ #define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */ -#define ADD_BMP_CMD CFG_CMD_BMP -#else -#define ADD_BMP_CMD 0 #endif /* CONFIG_VIDEO */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_EXT2 | \ - CFG_CMD_ELF | \ - CFG_CMD_NAND | \ - CFG_CMD_I2C | \ - CFG_CMD_DATE | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - ADD_BMP_CMD | \ - CFG_CMD_EEPROM ) + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_ELF +#define CONFIG_CMD_NAND +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DATE +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_EEPROM + +#ifdef CONFIG_VIDEO +#define CONFIG_CMD_BMP +#endif #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -127,11 +141,6 @@ #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ #undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CFG_NAND_LEGACY - #undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -148,7 +157,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -198,36 +207,18 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff @@ -377,7 +368,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif |