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Diffstat (limited to 'include/configs/CPCI405.h')
-rw-r--r--include/configs/CPCI405.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index b159182..efc3ada 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -151,8 +151,8 @@
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
+#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
@@ -256,7 +256,7 @@
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */