diff options
Diffstat (limited to 'include/asm-ppc')
26 files changed, 936 insertions, 292 deletions
diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index a7cf1e8..a0e88de 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -18,9 +18,9 @@ #define DCRN_SDR0_CFGDATA 0x00f #if defined(CONFIG_440SPE) -#define CFG_PCIE_NR_PORTS 3 +#define CONFIG_SYS_PCIE_NR_PORTS 3 -#define CFG_PCIE_ADDR_HIGH 0x0000000d +#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d #define DCRN_PCIE0_BASE 0x100 #define DCRN_PCIE1_BASE 0x120 @@ -32,9 +32,9 @@ #endif #if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define CFG_PCIE_NR_PORTS 2 +#define CONFIG_SYS_PCIE_NR_PORTS 2 -#define CFG_PCIE_ADDR_HIGH 0x0000000d +#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d #define DCRN_PCIE0_BASE 0x100 #define DCRN_PCIE1_BASE 0x120 @@ -44,9 +44,9 @@ #endif #if defined(CONFIG_405EX) -#define CFG_PCIE_NR_PORTS 2 +#define CONFIG_SYS_PCIE_NR_PORTS 2 -#define CFG_PCIE_ADDR_HIGH 0x00000000 +#define CONFIG_SYS_PCIE_ADDR_HIGH 0x00000000 #define DCRN_PCIE0_BASE 0x040 #define DCRN_PCIE1_BASE 0x060 @@ -406,7 +406,7 @@ static inline u32 sdr_base(int port) return PCIE0_SDR; case 1: return PCIE1_SDR; -#if CFG_PCIE_NR_PORTS > 2 +#if CONFIG_SYS_PCIE_NR_PORTS > 2 case 2: return PCIE2_SDR; #endif diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 9d9b971..53e8d05 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -12,6 +12,8 @@ #define L1_CACHE_SHIFT 4 #elif defined(CONFIG_PPC64BRIDGE) #define L1_CACHE_SHIFT 7 +#elif defined(CONFIG_E500MC) +#define L1_CACHE_SHIFT 6 #else #define L1_CACHE_SHIFT 5 #endif @@ -19,10 +21,10 @@ #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) /* - * For compatibility reasons support the CFG_CACHELINE_SIZE too + * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too */ -#ifndef CFG_CACHELINE_SIZE -#define CFG_CACHELINE_SIZE L1_CACHE_BYTES +#ifndef CONFIG_SYS_CACHELINE_SIZE +#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES #endif #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) @@ -44,9 +46,10 @@ extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void invalidate_dcache_range(unsigned long start, unsigned long stop); extern void flush_dcache(void); extern void invalidate_dcache(void); -#ifdef CFG_INIT_RAM_LOCK +extern void invalidate_icache(void); +#ifdef CONFIG_SYS_INIT_RAM_LOCK extern void unlock_ram_in_cache(void); -#endif /* CFG_INIT_RAM_LOCK */ +#endif /* CONFIG_SYS_INIT_RAM_LOCK */ #endif /* __ASSEMBLY__ */ /* prep registers for L2 */ diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h new file mode 100644 index 0000000..275a7c8 --- /dev/null +++ b/include/asm-ppc/config.h @@ -0,0 +1,32 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#ifndef CONFIG_MAX_MEM_MAPPED +#if defined(CONFIG_4xx) || defined(CONFIG_E500) +#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) +#else +#define CONFIG_MAX_MEM_MAPPED (256 << 20) +#endif +#endif + +#endif diff --git a/include/asm-ppc/cpm_8260.h b/include/asm-ppc/cpm_8260.h index 2a9774a..8302404 100644 --- a/include/asm-ppc/cpm_8260.h +++ b/include/asm-ppc/cpm_8260.h @@ -141,16 +141,16 @@ typedef struct cpm_buf_desc { /* Parameter RAM offsets from the base. */ -#ifndef CFG_CPM_POST_WORD_ADDR +#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR #define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */ #else -#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR +#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR #endif -#ifndef CFG_CPM_BOOTCOUNT_ADDR +#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR #define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) #else -#define CPM_BOOTCOUNT_ADDR CFG_CPM_BOOTCOUNT_ADDR +#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR #endif #define PROFF_SCC1 ((uint)0x8000) @@ -546,6 +546,34 @@ typedef struct scc_trans { #define BD_SCC_TX_LAST ((ushort)0x0800) +/* SCC as HDLC controller - taken from commproc.h + */ +typedef struct scc_hdlc { + sccp_t sh_genscc; + /* + * HDLC specific parameter RAM + */ + uchar res[4]; /* reserved */ + ulong sh_cmask; /* CRC constant */ + ulong sh_cpres; /* CRC preset */ + ushort sh_disfc; /* discarded frame counter */ + ushort sh_crcec; /* CRC error counter */ + ushort sh_abtsc; /* abort sequence counter */ + ushort sh_nmarc; /* nonmatching address rx cnt */ + ushort sh_retrc; /* frame retransmission cnt */ + ushort sh_mflr; /* maximum frame length reg */ + ushort sh_maxcnt; /* maximum length counter */ + ushort sh_rfthr; /* received frames threshold */ + ushort sh_rfcnt; /* received frames count */ + ushort sh_hmask; /* user defined frm addr mask */ + ushort sh_haddr1; /* user defined frm address 1 */ + ushort sh_haddr2; /* user defined frm address 2 */ + ushort sh_haddr3; /* user defined frm address 3 */ + ushort sh_haddr4; /* user defined frm address 4 */ + ushort tmp; /* temp */ + ushort tmp_mb; /* temp */ +} scc_hdlc_t; + /* How about some FCCs..... */ #define FCC_GFMR_DIAG_NORM ((uint)0x00000000) diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h index 05db0de..bfef4df 100644 --- a/include/asm-ppc/e300.h +++ b/include/asm-ppc/e300.h @@ -88,39 +88,4 @@ #define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */ #define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */ - -/* BAT (block address translation */ -#define BATU_BEPI_MSK 0xfffe0000 -#define BATU_BL_MSK 0x00001ffc - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 - -#define BATL_BRPN_MSK 0xfffe0000 -#define BATL_WIMG_MSK 0x00000078 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - #endif /* __E300_H__ */ diff --git a/include/asm-ppc/fsl_ddr_dimm_params.h b/include/asm-ppc/fsl_ddr_dimm_params.h new file mode 100644 index 0000000..c794eed --- /dev/null +++ b/include/asm-ppc/fsl_ddr_dimm_params.h @@ -0,0 +1,84 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef DDR2_DIMM_PARAMS_H +#define DDR2_DIMM_PARAMS_H + +/* Parameters for a DDR2 dimm computed from the SPD */ +typedef struct dimm_params_s { + + /* DIMM organization parameters */ + char mpart[19]; /* guaranteed null terminated */ + + unsigned int n_ranks; + unsigned long long rank_density; + unsigned long long capacity; + unsigned int data_width; + unsigned int primary_sdram_width; + unsigned int ec_sdram_width; + unsigned int registered_dimm; + + /* SDRAM device parameters */ + unsigned int n_row_addr; + unsigned int n_col_addr; + unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ + unsigned int n_banks_per_sdram_device; + unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ + unsigned int row_density; + + /* used in computing base address of DIMMs */ + unsigned long long base_address; + + /* DIMM timing parameters */ + + /* + * SDRAM clock periods + * The range for these are 1000-10000 so a short should be sufficient + */ + unsigned int tCKmin_X_ps; + unsigned int tCKmin_X_minus_1_ps; + unsigned int tCKmin_X_minus_2_ps; + unsigned int tCKmax_ps; + + /* SPD-defined CAS latencies */ + unsigned int caslat_X; + unsigned int caslat_X_minus_1; + unsigned int caslat_X_minus_2; + + unsigned int caslat_lowest_derated; /* Derated CAS latency */ + + /* basic timing parameters */ + unsigned int tRCD_ps; + unsigned int tRP_ps; + unsigned int tRAS_ps; + + unsigned int tWR_ps; /* maximum = 63750 ps */ + unsigned int tWTR_ps; /* maximum = 63750 ps */ + unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns + = 511750 ps */ + + unsigned int tRRD_ps; /* maximum = 63750 ps */ + unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + + unsigned int refresh_rate_ps; + + unsigned int tIS_ps; /* byte 32, spd->ca_setup */ + unsigned int tIH_ps; /* byte 33, spd->ca_hold */ + unsigned int tDS_ps; /* byte 34, spd->data_setup */ + unsigned int tDH_ps; /* byte 35, spd->data_hold */ + unsigned int tRTP_ps; /* byte 38, spd->trtp */ + unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */ + unsigned int tQHS_ps; /* byte 45, spd->tqhs */ +} dimm_params_t; + +extern unsigned int ddr_compute_dimm_parameters( + const generic_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number); + +#endif diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 8adde34..6e3b255 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -34,7 +34,39 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; #elif defined(CONFIG_FSL_DDR3) #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 #endif +#endif /* #if defined(CONFIG_FSL_DDR1) */ + +/* define bank(chip select) interleaving mode */ +#define FSL_DDR_CS0_CS1 0x40 +#define FSL_DDR_CS2_CS3 0x20 +#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) +#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) + +/* define memory controller interleaving mode */ +#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 +#define FSL_DDR_PAGE_INTERLEAVING 0x1 +#define FSL_DDR_BANK_INTERLEAVING 0x2 +#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 + +/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration + */ +#define SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG_SREN 0x40000000 +#define SDRAM_CFG_ECC_EN 0x20000000 +#define SDRAM_CFG_RD_EN 0x10000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 +#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 +#define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_8_BE 0x00040000 +#define SDRAM_CFG_NCAP 0x00020000 +#define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_BI 0x00000001 /* Record of register values computed */ typedef struct fsl_ddr_cfg_regs_s { @@ -131,6 +163,10 @@ typedef struct memctl_options_s { unsigned int bstopre; unsigned int tCKE_clock_pulse_width_ps; /* tCKE */ unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */ + + /* Automatic self refresh */ + unsigned int auto_self_refresh_en; + unsigned int sr_it; } memctl_options_t; extern phys_size_t fsl_ddr_sdram(void); diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h index 5bba08d..e06a1a6 100644 --- a/include/asm-ppc/fsl_law.h +++ b/include/asm-ppc/fsl_law.h @@ -42,7 +42,7 @@ enum law_trgt_if { #ifndef CONFIG_MPC8641 LAW_TRGT_IF_PCIE_1 = 0x02, #endif -#ifndef CONFIG_MPC8572 +#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020) LAW_TRGT_IF_PCIE_3 = 0x03, #endif LAW_TRGT_IF_LBC = 0x04, @@ -61,7 +61,7 @@ enum law_trgt_if { #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI #endif -#ifdef CONFIG_MPC8572 +#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI #endif diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index ea49ddc..9fa0b65 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -28,6 +28,8 @@ #define BR_BA 0xFFFF8000 #define BR_BA_SHIFT 15 +#define BR_XBA 0x00006000 +#define BR_XBA_SHIFT 13 #define BR_PS 0x00001800 #define BR_PS_SHIFT 11 #define BR_PS_8 0x00000800 /* Port Size 8 bit */ @@ -69,6 +71,14 @@ #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) #endif +/* Convert an address into the right format for the BR registers */ +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC) +#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \ + ((x & 0x300000000ULL) >> 19))) +#else +#define BR_PHYS_ADDR(x) (x & 0xffff8000) +#endif + /* OR - Option Registers */ #define OR0 0x5004 /* Register offset to immr */ @@ -82,6 +92,8 @@ #define OR_GPCM_AM 0xFFFF8000 #define OR_GPCM_AM_SHIFT 15 +#define OR_GPCM_XAM 0x00006000 +#define OR_GPCM_XAM_SHIFT 13 #define OR_GPCM_BCTLD 0x00001000 #define OR_GPCM_BCTLD_SHIFT 12 #define OR_GPCM_CSNT 0x00000800 @@ -124,6 +136,8 @@ #define OR_FCM_AM 0xFFFF8000 #define OR_FCM_AM_SHIFT 15 +#define OR_FCM_XAM 0x00006000 +#define OR_FCM_XAM_SHIFT 13 #define OR_FCM_BCTLD 0x00001000 #define OR_FCM_BCTLD_SHIFT 12 #define OR_FCM_PGS 0x00000400 @@ -292,7 +306,10 @@ #define LCRR_EADC_2 0x00020000 #define LCRR_EADC_3 0x00030000 #define LCRR_EADC_4 0x00000000 -#define LCRR_CLKDIV 0x0000000F +/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit + * should always be zero on older parts that have a four bit CLKDIV. + */ +#define LCRR_CLKDIV 0x0000001F #define LCRR_CLKDIV_SHIFT 0 #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 @@ -307,4 +324,134 @@ #define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */ #define LTEDR_CSD 0x00080000 /* Chip select error checking disable */ +/* FMR - Flash Mode Register + */ +#define FMR_CWTO 0x0000F000 +#define FMR_CWTO_SHIFT 12 +#define FMR_BOOT 0x00000800 +#define FMR_ECCM 0x00000100 +#define FMR_AL 0x00000030 +#define FMR_AL_SHIFT 4 +#define FMR_OP 0x00000003 +#define FMR_OP_SHIFT 0 + +/* FIR - Flash Instruction Register + */ +#define FIR_OP0 0xF0000000 +#define FIR_OP0_SHIFT 28 +#define FIR_OP1 0x0F000000 +#define FIR_OP1_SHIFT 24 +#define FIR_OP2 0x00F00000 +#define FIR_OP2_SHIFT 20 +#define FIR_OP3 0x000F0000 +#define FIR_OP3_SHIFT 16 +#define FIR_OP4 0x0000F000 +#define FIR_OP4_SHIFT 12 +#define FIR_OP5 0x00000F00 +#define FIR_OP5_SHIFT 8 +#define FIR_OP6 0x000000F0 +#define FIR_OP6_SHIFT 4 +#define FIR_OP7 0x0000000F +#define FIR_OP7_SHIFT 0 +#define FIR_OP_NOP 0x0 /* No operation and end of sequence */ +#define FIR_OP_CA 0x1 /* Issue current column address */ +#define FIR_OP_PA 0x2 /* Issue current block+page address */ +#define FIR_OP_UA 0x3 /* Issue user defined address */ +#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ +#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ +#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ +#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ +#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ +#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ +#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ +#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ +#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ +#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ +#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ +#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ + +/* FCR - Flash Command Register + */ +#define FCR_CMD0 0xFF000000 +#define FCR_CMD0_SHIFT 24 +#define FCR_CMD1 0x00FF0000 +#define FCR_CMD1_SHIFT 16 +#define FCR_CMD2 0x0000FF00 +#define FCR_CMD2_SHIFT 8 +#define FCR_CMD3 0x000000FF +#define FCR_CMD3_SHIFT 0 +/* FBAR - Flash Block Address Register + */ +#define FBAR_BLK 0x00FFFFFF + +/* FPAR - Flash Page Address Register + */ +#define FPAR_SP_PI 0x00007C00 +#define FPAR_SP_PI_SHIFT 10 +#define FPAR_SP_MS 0x00000200 +#define FPAR_SP_CI 0x000001FF +#define FPAR_SP_CI_SHIFT 0 +#define FPAR_LP_PI 0x0003F000 +#define FPAR_LP_PI_SHIFT 12 +#define FPAR_LP_MS 0x00000800 +#define FPAR_LP_CI 0x000007FF +#define FPAR_LP_CI_SHIFT 0 + +/* LTESR - Transfer Error Status Register + */ +#define LTESR_BM 0x80000000 +#define LTESR_FCT 0x40000000 +#define LTESR_PAR 0x20000000 +#define LTESR_WP 0x04000000 +#define LTESR_ATMW 0x00800000 +#define LTESR_ATMR 0x00400000 +#define LTESR_CS 0x00080000 +#define LTESR_CC 0x00000001 + +#ifndef __ASSEMBLY__ +/* + * Local Bus Controller Registers. + */ +typedef struct lbus_bank { + u32 br; /* Base Register */ + u32 or; /* Option Register */ +} lbus_bank_t; + +typedef struct fsl_lbus { + lbus_bank_t bank[8]; + u8 res0[0x28]; + u32 mar; /* UPM Address Register */ + u8 res1[0x4]; + u32 mamr; /* UPMA Mode Register */ + u32 mbmr; /* UPMB Mode Register */ + u32 mcmr; /* UPMC Mode Register */ + u8 res2[0x8]; + u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ + u32 mdr; /* UPM Data Register */ + u8 res3[0x4]; + u32 lsor; /* Special Operation Initiation Register */ + u32 lsdmr; /* SDRAM Mode Register */ + u8 res4[0x8]; + u32 lurt; /* UPM Refresh Timer */ + u32 lsrt; /* SDRAM Refresh Timer */ + u8 res5[0x8]; + u32 ltesr; /* Transfer Error Status Register */ + u32 ltedr; /* Transfer Error Disable Register */ + u32 lteir; /* Transfer Error Interrupt Register */ + u32 lteatr; /* Transfer Error Attributes Register */ + u32 ltear; /* Transfer Error Address Register */ + u8 res6[0xC]; + u32 lbcr; /* Configuration Register */ + u32 lcrr; /* Clock Ratio Register */ + u8 res7[0x8]; + u32 fmr; /* Flash Mode Register */ + u32 fir; /* Flash Instruction Register */ + u32 fcr; /* Flash Command Register */ + u32 fbar; /* Flash Block Addr Register */ + u32 fpar; /* Flash Page Addr Register */ + u32 fbcr; /* Flash Byte Count Register */ + u8 res8[0xF08]; +} fsl_lbus_t; +#endif /* __ASSEMBLY__ */ + #endif /* __ASM_PPC_FSL_LBC_H */ diff --git a/include/asm-ppc/fsl_serdes.h b/include/asm-ppc/fsl_serdes.h index 733f919..6da4b6f 100644 --- a/include/asm-ppc/fsl_serdes.h +++ b/include/asm-ppc/fsl_serdes.h @@ -3,9 +3,9 @@ #include <config.h> -#define FSL_SERDES_CLK_100 0 -#define FSL_SERDES_CLK_125 1 -#define FSL_SERDES_CLK_150 3 +#define FSL_SERDES_CLK_100 (0 << 28) +#define FSL_SERDES_CLK_125 (1 << 28) +#define FSL_SERDES_CLK_150 (3 << 28) #define FSL_SERDES_PROTO_SATA 0 #define FSL_SERDES_PROTO_PEX 1 #define FSL_SERDES_PROTO_PEX_X2 2 @@ -13,9 +13,9 @@ #define FSL_SERDES_VDD_1V 1 #ifdef CONFIG_FSL_SERDES -extern void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd); +extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd); #else -static void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd) {} +static void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) {} #endif /* CONFIG_FSL_SERDES */ #endif /* __FSL_SERDES_H */ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 4331a15..e5a3b2c 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -33,7 +33,7 @@ * global variables during system initialization (until we have set * up the memory controller so that we can use RAM). * - * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) */ typedef struct global_data { @@ -75,7 +75,7 @@ typedef struct global_data { u32 lbiu_clk; u32 lclk_clk; u32 pci_clk; -#if defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X) u32 pciexp1_clk; u32 pciexp2_clk; #endif @@ -89,6 +89,9 @@ typedef struct global_data { #if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8536) u32 sdhc_clk; #endif +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) + u32 lbc_clk; +#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */ #if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) u32 i2c1_clk; u32 i2c2_clk; @@ -129,14 +132,14 @@ typedef struct global_data { unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long have_console; /* serial_init() was called */ -#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_CPM2) +#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2) unsigned int dp_alloc_base; unsigned int dp_alloc_top; #endif #if defined(CONFIG_4xx) u32 uart_clk; #endif /* CONFIG_4xx */ -#if defined(CFG_GT_6426x) +#if defined(CONFIG_SYS_GT_6426x) unsigned int mirror_hack[16]; #endif #if defined(CONFIG_A3000) || \ diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index cd90945..8087869 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -415,7 +415,25 @@ typedef struct ioctrl512x { * IIM */ typedef struct iim512x { - u8 fixme[0x1000]; + u32 stat; /* IIM status register */ + u32 statm; /* IIM status IRQ mask */ + u32 err; /* IIM errors register */ + u32 emask; /* IIM error IRQ mask */ + u32 fctl; /* IIM fuse control register */ + u32 ua; /* IIM upper address register */ + u32 la; /* IIM lower address register */ + u32 sdat; /* IIM explicit sense data */ + u8 res0[0x08]; + u32 prg_p; /* IIM program protection register */ + u8 res1[0x10]; + u32 divide; /* IIM divide factor register */ + u8 res2[0x7c0]; + u32 fbac0; /* IIM fuse bank 0 prot (for Freescale use) */ + u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */ + u8 res3[0x380]; + u32 fbac1; /* IIM fuse bank 1 protection */ + u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */ + u8 res4[0x380]; } iim512x_t; /* @@ -451,7 +469,34 @@ typedef struct lpc512x { * PATA */ typedef struct pata512x { - u8 fixme[0x100]; + /* LOCAL Registers */ + u32 pata_time1; /* Time register 1: PIO and tx timing parameter */ + u32 pata_time2; /* Time register 2: PIO timing parameter */ + u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */ + u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */ + u32 pata_time5; /* Time register 5: UDMA timing parameter */ + u32 pata_time6; /* Time register 6: UDMA timing parameter */ + u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */ + u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */ + u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/ + u32 pata_ata_control; /* ATA Interface control register */ + u32 pata_irq_pending; /* Interrupt pending register (READONLY) */ + u32 pata_irq_enable; /* Interrupt enable register */ + u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/ + u32 pata_fifo_alarm; /* fifo alarm threshold */ + u32 res1[0x1A]; + /* DRIVE Registers */ + u32 pata_drive_data; /* drive data register*/ + u32 pata_drive_features;/* drive features register */ + u32 pata_drive_sectcnt; /* drive sector count register */ + u32 pata_drive_sectnum; /* drive sector number register */ + u32 pata_drive_cyllow; /* drive cylinder low register */ + u32 pata_drive_cylhigh; /* drive cylinder high register */ + u32 pata_drive_dev_head;/* drive device head register */ + u32 pata_drive_command; /* write = drive command, read = drive status reg */ + u32 res2[0x06]; + u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */ + u32 res3[0x09]; } pata512x_t; /* diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index ff18303..7b847f8 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -31,6 +31,7 @@ #include <asm/types.h> #include <asm/fsl_i2c.h> #include <asm/mpc8xxx_spi.h> +#include <asm/fsl_lbc.h> /* * Local Access Window @@ -51,23 +52,28 @@ typedef struct sysconf83xx { law83xx_t lblaw[4]; /* LBIU local access window */ u8 res2[0x20]; law83xx_t pcilaw[2]; /* PCI local access window */ - u8 res3[0x30]; + u8 res3[0x10]; + law83xx_t pcielaw[2]; /* PCI Express local access window */ + u8 res4[0x10]; law83xx_t ddrlaw[2]; /* DDR local access window */ - u8 res4[0x50]; + u8 res5[0x50]; u32 sgprl; /* System General Purpose Register Low */ u32 sgprh; /* System General Purpose Register High */ u32 spridr; /* System Part and Revision ID Register */ - u8 res5[0x04]; + u8 res6[0x04]; u32 spcr; /* System Priority Configuration Register */ u32 sicrl; /* System I/O Configuration Register Low */ u32 sicrh; /* System I/O Configuration Register High */ - u8 res6[0x04]; + u8 res7[0x04]; u32 sidcr0; /* System I/O Delay Configuration Register 0 */ u32 sidcr1; /* System I/O Delay Configuration Register 1 */ u32 ddrcdr; /* DDR Control Driver Register */ u32 ddrdsr; /* DDR Debug Status Register */ u32 obir; /* Output Buffer Impedance Register */ - u8 res7[0xCC]; + u8 res8[0xC]; + u32 pecr1; /* PCI Express control register 1 */ + u32 pecr2; /* PCI Express control register 2 */ + u8 res9[0xB8]; } sysconf83xx_t; /* @@ -343,50 +349,6 @@ typedef struct duart83xx { } duart83xx_t; /* - * Local Bus Controller Registers - */ -typedef struct lbus_bank { - u32 br; /* Base Register */ - u32 or; /* Option Register */ -} lbus_bank_t; - -typedef struct lbus83xx { - lbus_bank_t bank[8]; - u8 res0[0x28]; - u32 mar; /* UPM Address Register */ - u8 res1[0x4]; - u32 mamr; /* UPMA Mode Register */ - u32 mbmr; /* UPMB Mode Register */ - u32 mcmr; /* UPMC Mode Register */ - u8 res2[0x8]; - u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ - u32 mdr; /* UPM Data Register */ - u8 res3[0x4]; - u32 lsor; /* Special Operation Initiation Register */ - u32 lsdmr; /* SDRAM Mode Register */ - u8 res4[0x8]; - u32 lurt; /* UPM Refresh Timer */ - u32 lsrt; /* SDRAM Refresh Timer */ - u8 res5[0x8]; - u32 ltesr; /* Transfer Error Status Register */ - u32 ltedr; /* Transfer Error Disable Register */ - u32 lteir; /* Transfer Error Interrupt Register */ - u32 lteatr; /* Transfer Error Attributes Register */ - u32 ltear; /* Transfer Error Address Register */ - u8 res6[0xC]; - u32 lbcr; /* Configuration Register */ - u32 lcrr; /* Clock Ratio Register */ - u8 res7[0x8]; - u32 fmr; /* Flash Mode Register */ - u32 fir; /* Flash Instruction Register */ - u32 fcr; /* Flash Command Register */ - u32 fbar; /* Flash Block Addr Register */ - u32 fpar; /* Flash Page Addr Register */ - u32 fbcr; /* Flash Byte Count Register */ - u8 res8[0xF08]; -} lbus83xx_t; - -/* * DMA/Messaging Unit */ typedef struct dma83xx { @@ -546,8 +508,110 @@ typedef struct security83xx { /* * PCI Express */ +struct pex_inbound_window { + u32 ar; + u32 tar; + u32 barl; + u32 barh; +}; + +struct pex_outbound_window { + u32 ar; + u32 bar; + u32 tarl; + u32 tarh; +}; + +struct pex_csb_bridge { + u32 pex_csb_ver; + u32 pex_csb_cab; + u32 pex_csb_ctrl; + u8 res0[8]; + u32 pex_dms_dstmr; + u8 res1[4]; + u32 pex_cbs_stat; + u8 res2[0x20]; + u32 pex_csb_obctrl; + u32 pex_csb_obstat; + u8 res3[0x98]; + u32 pex_csb_ibctrl; + u32 pex_csb_ibstat; + u8 res4[0xb8]; + u32 pex_wdma_ctrl; + u32 pex_wdma_addr; + u32 pex_wdma_stat; + u8 res5[0x94]; + u32 pex_rdma_ctrl; + u32 pex_rdma_addr; + u32 pex_rdma_stat; + u8 res6[0xd4]; + u32 pex_ombcr; + u32 pex_ombdr; + u8 res7[0x38]; + u32 pex_imbcr; + u32 pex_imbdr; + u8 res8[0x38]; + u32 pex_int_enb; + u32 pex_int_stat; + u32 pex_int_apio_vec1; + u32 pex_int_apio_vec2; + u8 res9[0x10]; + u32 pex_int_ppio_vec1; + u32 pex_int_ppio_vec2; + u32 pex_int_wdma_vec1; + u32 pex_int_wdma_vec2; + u32 pex_int_rdma_vec1; + u32 pex_int_rdma_vec2; + u32 pex_int_misc_vec; + u8 res10[4]; + u32 pex_int_axi_pio_enb; + u32 pex_int_axi_wdma_enb; + u32 pex_int_axi_rdma_enb; + u32 pex_int_axi_misc_enb; + u32 pex_int_axi_pio_stat; + u32 pex_int_axi_wdma_stat; + u32 pex_int_axi_rdma_stat; + u32 pex_int_axi_misc_stat; + u8 res11[0xa0]; + struct pex_outbound_window pex_outbound_win[4]; + u8 res12[0x100]; + u32 pex_epiwtar0; + u32 pex_epiwtar1; + u32 pex_epiwtar2; + u32 pex_epiwtar3; + u8 res13[0x70]; + struct pex_inbound_window pex_inbound_win[4]; +}; + typedef struct pex83xx { - u8 fixme[0x1000]; + u8 pex_cfg_header[0x404]; + u32 pex_ltssm_stat; + u8 res0[0x30]; + u32 pex_ack_replay_timeout; + u8 res1[4]; + u32 pex_gclk_ratio; + u8 res2[0xc]; + u32 pex_pm_timer; + u32 pex_pme_timeout; + u8 res3[4]; + u32 pex_aspm_req_timer; + u8 res4[0x18]; + u32 pex_ssvid_update; + u8 res5[0x34]; + u32 pex_cfg_ready; + u8 res6[0x24]; + u32 pex_bar_sizel; + u8 res7[4]; + u32 pex_bar_sel; + u8 res8[0x20]; + u32 pex_bar_pf; + u8 res9[0x88]; + u32 pex_pme_to_ack_tor; + u8 res10[0xc]; + u32 pex_ss_intr_mask; + u8 res11[0x25c]; + struct pex_csb_bridge bridge; + u8 res12[0x160]; } pex83xx_t; /* @@ -614,7 +678,7 @@ typedef struct immap { u8 res2[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res3[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ + fsl_lbus_t lbus; /* Local Bus Controller Registers */ u8 res4[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -648,7 +712,7 @@ typedef struct immap { u8 res1[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res2[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ + fsl_lbus_t lbus; /* Local Bus Controller Registers */ u8 res3[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -683,7 +747,7 @@ typedef struct immap { u8 res1[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res2[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ + fsl_lbus_t lbus; /* Local Bus Controller Registers */ u8 res3[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -728,7 +792,7 @@ typedef struct immap { u8 res1[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res2[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ + fsl_lbus_t lbus; /* Local Bus Controller Registers */ u8 res3[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -778,7 +842,7 @@ typedef struct immap { u8 res4[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res5[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ + fsl_lbus_t lbus; /* Local Bus Controller Registers */ u8 res6[0x2000]; dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ @@ -817,7 +881,7 @@ typedef struct immap { u8 res3[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res4[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ + fsl_lbus_t lbus; /* Local Bus Controller Registers */ u8 res5[0x2000]; dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ @@ -831,4 +895,6 @@ typedef struct immap { } immap_t; #endif +#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000) +#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) #endif /* __IMMAP_83xx__ */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 559d6ea..7b97fe0 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -13,6 +13,7 @@ #include <asm/types.h> #include <asm/fsl_i2c.h> +#include <asm/fsl_lbc.h> /* * Local-Access Registers and ECM Registers(0x0000-0x2000) @@ -57,7 +58,23 @@ typedef struct ccsr_local_ecm { uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ char res19[4]; uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ - char res20[780]; /* XXX: LAW 8, LAW9 for 8572 */ + char res19_8a[20]; + uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ + char res19_8b[4]; + uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ + char res19_9a[20]; + uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ + char res19_9b[4]; + uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ + char res19_10a[20]; + uint lawbar10; /* 0xd48 - Local Access Window 10 Base Address Register */ + char res19_10b[4]; + uint lawar10; /* 0xd50 - Local Access Window 10 Attributes Register */ + char res19_11a[20]; + uint lawbar11; /* 0xd68 - Local Access Window 11 Base Address Register */ + char res19_11b[4]; + uint lawar11; /* 0xd70 - Local Access Window 11 Attributes Register */ + char res20[652]; uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */ char res21[12]; uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */ @@ -118,7 +135,12 @@ typedef struct ccsr_ddr { uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */ uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */ uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */ - char res8_1b[2672]; + char res8_1b[2456]; + uint ddr_dsr1; /* 0x2B20 - DDR Debug Status Register 1 */ + uint ddr_dsr2; /* 0x2B24 - DDR Debug Status Register 2 */ + uint ddr_cdr1; /* 0x2B28 - DDR Control Driver Register 1 */ + uint ddr_cdr2; /* 0x2B2C - DDR Control Driver Register 2 */ + char res8_1c[200]; uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ char res8_2[512]; @@ -1552,6 +1574,13 @@ typedef struct par_io { */ typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ +#ifdef CONFIG_MPC8536 +#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 +#else +#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 +#endif uint porbmsr; /* 0xe0004 - POR boot mode status register */ #define MPC85xx_PORBMSR_HA 0x00070000 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ @@ -1561,7 +1590,8 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 -#define MPC85xx_PORDEVSR_IO_SEL 0x00380000 +#define MPC85xx_PORDEVSR_PCI1 0x00800000 +#define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 @@ -1572,7 +1602,8 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */ -#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000020 +/* The 8544 RM says this is bit 26, but it's really bit 24 */ +#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 char res1[8]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ char res2[12]; @@ -1583,6 +1614,9 @@ typedef struct ccsr_gur { uint gpindr; /* 0xe0050 - General-purpose input data register */ char res5[12]; uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ +#define MPC85xx_PMUXCR_SD_DATA 0x80000000 +#define MPC85xx_PMUXCR_SDHC_CD 0x40000000 +#define MPC85xx_PMUXCR_SDHC_WP 0x20000000 char res6[12]; uint devdisr; /* 0xe0070 - Device disable control */ #define MPC85xx_DEVDISR_PCI1 0x80000000 @@ -1638,39 +1672,37 @@ typedef struct ccsr_gur { char res15[61648]; /* 0xe0f30 to 0xefffff */ } ccsr_gur_t; -#define PORDEVSR_PCI (0x00800000) /* PCI Mode */ - -#define CFG_MPC85xx_GUTS_OFFSET (0xE0000) -#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET) -#define CFG_MPC85xx_ECM_OFFSET (0x0000) -#define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET) -#define CFG_MPC85xx_DDR_OFFSET (0x2000) -#define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET) -#define CFG_MPC85xx_DDR2_OFFSET (0x6000) -#define CFG_MPC85xx_DDR2_ADDR (CFG_IMMR + CFG_MPC85xx_DDR2_OFFSET) -#define CFG_MPC85xx_LBC_OFFSET (0x5000) -#define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET) -#define CFG_MPC85xx_PCIX_OFFSET (0x8000) -#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET) -#define CFG_MPC85xx_PCIX2_OFFSET (0x9000) -#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET) -#define CFG_MPC85xx_SATA1_OFFSET (0x18000) -#define CFG_MPC85xx_SATA1_ADDR (CFG_IMMR + CFG_MPC85xx_SATA1_OFFSET) -#define CFG_MPC85xx_SATA2_OFFSET (0x19000) -#define CFG_MPC85xx_SATA2_ADDR (CFG_IMMR + CFG_MPC85xx_SATA2_OFFSET) -#define CFG_MPC85xx_L2_OFFSET (0x20000) -#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET) -#define CFG_MPC85xx_DMA_OFFSET (0x21000) -#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET) -#define CFG_MPC85xx_ESDHC_OFFSET (0x2e000) -#define CFG_MPC85xx_ESDHC_ADDR (CFG_IMMR + CFG_MPC85xx_ESDHC_OFFSET) -#define CFG_MPC85xx_PIC_OFFSET (0x40000) -#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET) -#define CFG_MPC85xx_CPM_OFFSET (0x80000) -#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET) -#define CFG_MPC85xx_SERDES1_OFFSET (0xE3000) -#define CFG_MPC85xx_SERDES1_ADDR (CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET) -#define CFG_MPC85xx_SERDES2_OFFSET (0xE3100) -#define CFG_MPC85xx_SERDES2_ADDR (CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET) +#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000) +#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) +#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000) +#define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) +#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000) +#define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000) +#define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) +#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000) +#define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) +#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) +#define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) +#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) +#define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) +#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) +#define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) +#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) +#define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) +#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000) +#define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) +#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000) +#define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000) +#define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) +#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000) +#define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) +#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000) +#define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) +#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000) +#define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) +#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100) +#define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #endif /*__IMMAP_85xx__*/ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 03a25c7..470385f 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -1289,22 +1289,35 @@ typedef struct ccsr_gur { uint powmgtcsr; /* 0xe0080 - Power management status and control register */ char res8[12]; uint mcpsumr; /* 0xe0090 - Machine check summary register */ - char res9[12]; + uint rstrscr; /* 0xe0094 - Reset request status and control register */ + char res9[8]; uint pvr; /* 0xe00a0 - Processor version register */ uint svr; /* 0xe00a4 - System version register */ - char res10a[1880]; + char res10a[8]; + uint rstcr; /* 0xe00b0 - Reset control register */ +#define MPC86xx_RSTCR_HRST_REQ 0x00000002 + char res10b[1868]; uint clkdvdr; /* 0xe0800 - Clock Divide register */ - char res10b[1532]; + char res10c[796]; + uint ddr1clkdr; /* 0xe0b20 - DDRC1 Clock Disable register */ + char res10d[4]; + uint ddr2clkdr; /* 0xe0b28 - DDRC2 Clock Disable register */ + char res10e[724]; uint clkocr; /* 0xe0e00 - Clock out select register */ char res11[12]; uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ char res12[12]; uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ - int res13[57]; - uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/ - int res14[6]; - uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ - char res15[216]; + char res13a[224]; + uint srds1cr0; /* 0xe0f04 - SerDes1 control register 0 */ + char res13b[4]; + uint srds1cr1; /* 0xe0f08 - SerDes1 control register 1 */ + char res14[24]; + uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ + char res15a[24]; + uint srds2cr0; /* 0xe0f40 - SerDes2 control register 0 */ + uint srds2cr1; /* 0xe0f44 - SerDes2 control register 1 */ + char res16[184]; } ccsr_gur_t; /* @@ -1348,9 +1361,9 @@ typedef struct immap { extern immap_t *immr; -#define CFG_MPC86xx_DDR_OFFSET (0x2000) -#define CFG_MPC86xx_DDR_ADDR (CFG_IMMR + CFG_MPC86xx_DDR_OFFSET) -#define CFG_MPC86xx_DDR2_OFFSET (0x6000) -#define CFG_MPC86xx_DDR2_ADDR (CFG_IMMR + CFG_MPC86xx_DDR2_OFFSET) +#define CONFIG_SYS_MPC86xx_DDR_OFFSET (0x2000) +#define CONFIG_SYS_MPC86xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET) +#define CONFIG_SYS_MPC86xx_DDR2_OFFSET (0x6000) +#define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET) #endif /*__IMMAP_86xx__*/ diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index c349681..4ddad26 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -10,6 +10,10 @@ #include <linux/config.h> #include <asm/byteorder.h> +#ifdef CONFIG_ADDR_MAP +#include <addr_map.h> +#endif + #define SIO_CONFIG_RA 0x398 #define SIO_CONFIG_RD 0x399 @@ -287,7 +291,11 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val) static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { +#ifdef CONFIG_ADDR_MAP + return (void *)(addrmap_phys_to_virt(paddr)); +#else return (void *)((unsigned long)paddr); +#endif } /* @@ -298,4 +306,13 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) } +static inline phys_addr_t virt_to_phys(void * vaddr) +{ +#ifdef CONFIG_ADDR_MAP + return addrmap_virt_to_phys(vaddr); +#else + return (phys_addr_t)((unsigned long)vaddr); +#endif +} + #endif diff --git a/include/asm-ppc/iopin_8260.h b/include/asm-ppc/iopin_8260.h index 21ed8c2..619f3a8 100644 --- a/include/asm-ppc/iopin_8260.h +++ b/include/asm-ppc/iopin_8260.h @@ -26,140 +26,140 @@ iopin_t; extern __inline__ void iopin_set_high(iopin_t *iopin) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_low(iopin_t *iopin) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_high(iopin_t *iopin) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_low(iopin_t *iopin) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_out(iopin_t *iopin) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_in(iopin_t *iopin) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_out(iopin_t *iopin) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_in(iopin_t *iopin) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_odr(iopin_t *iopin) { - volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra; + volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_act(iopin_t *iopin) { - volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra; + volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_odr(iopin_t *iopin) { - volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra; + volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_act(iopin_t *iopin) { - volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra; + volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_ded(iopin_t *iopin) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_gen(iopin_t *iopin) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_ded(iopin_t *iopin) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_gen(iopin_t *iopin) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_opt2(iopin_t *iopin) { - volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora; + volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_opt1(iopin_t *iopin) { - volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora; + volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_opt2(iopin_t *iopin) { - volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora; + volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_opt1(iopin_t *iopin) { - volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora; + volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } diff --git a/include/asm-ppc/iopin_85xx.h b/include/asm-ppc/iopin_85xx.h index daddb55..0f07ba3 100644 --- a/include/asm-ppc/iopin_85xx.h +++ b/include/asm-ppc/iopin_85xx.h @@ -23,121 +23,121 @@ typedef struct { extern __inline__ void iopin_set_high (iopin_t * iopin) { - volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_low (iopin_t * iopin) { - volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_high (iopin_t * iopin) { - volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_low (iopin_t * iopin) { - volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_out (iopin_t * iopin) { - volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_in (iopin_t * iopin) { - volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_out (iopin_t * iopin) { - volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_in (iopin_t * iopin) { - volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_odr (iopin_t * iopin) { - volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_act (iopin_t * iopin) { - volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_odr (iopin_t * iopin) { - volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_act (iopin_t * iopin) { - volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_ded (iopin_t * iopin) { - volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_gen (iopin_t * iopin) { - volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_ded (iopin_t * iopin) { - volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_gen (iopin_t * iopin) { - volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_opt2 (iopin_t * iopin) { - volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_opt1 (iopin_t * iopin) { - volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_opt2 (iopin_t * iopin) { - volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_opt1 (iopin_t * iopin) { - volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } diff --git a/include/asm-ppc/iopin_8xx.h b/include/asm-ppc/iopin_8xx.h index 1946eb2..3a2a682 100644 --- a/include/asm-ppc/iopin_8xx.h +++ b/include/asm-ppc/iopin_8xx.h @@ -46,16 +46,16 @@ extern __inline__ void iopin_set_high(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; *datp |= (1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; *datp |= (1 << (31 - iopin->pin)); } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; *datp |= (1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; *datp |= (1 << (15 - iopin->pin)); } } @@ -64,16 +64,16 @@ extern __inline__ void iopin_set_low(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; *datp &= ~(1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; *datp &= ~(1 << (31 - iopin->pin)); } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; *datp &= ~(1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; *datp &= ~(1 << (15 - iopin->pin)); } } @@ -82,16 +82,16 @@ extern __inline__ uint iopin_is_high(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; return (*datp >> (15 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; return (*datp >> (31 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; return (*datp >> (15 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; return (*datp >> (15 - iopin->pin)) & 1; } return 0; @@ -101,16 +101,16 @@ extern __inline__ uint iopin_is_low(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; return ((*datp >> (31 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; } return 0; @@ -120,16 +120,16 @@ extern __inline__ void iopin_set_out(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; *dirp |= (1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; *dirp |= (1 << (31 - iopin->pin)); } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; *dirp |= (1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; *dirp |= (1 << (15 - iopin->pin)); } } @@ -138,16 +138,16 @@ extern __inline__ void iopin_set_in(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; *dirp &= ~(1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; *dirp &= ~(1 << (31 - iopin->pin)); } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; *dirp &= ~(1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; *dirp &= ~(1 << (15 - iopin->pin)); } } @@ -156,16 +156,16 @@ extern __inline__ uint iopin_is_out(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; return (*dirp >> (15 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; return (*dirp >> (31 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; return (*dirp >> (15 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; return (*dirp >> (15 - iopin->pin)) & 1; } return 0; @@ -175,16 +175,16 @@ extern __inline__ uint iopin_is_in(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; } return 0; @@ -194,10 +194,10 @@ extern __inline__ void iopin_set_odr(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; *odrp |= (1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; *odrp |= (1 << (31 - iopin->pin)); } } @@ -206,10 +206,10 @@ extern __inline__ void iopin_set_act(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; *odrp &= ~(1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; *odrp &= ~(1 << (31 - iopin->pin)); } } @@ -218,10 +218,10 @@ extern __inline__ uint iopin_is_odr(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; return (*odrp >> (15 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; return (*odrp >> (31 - iopin->pin)) & 1; } return 0; @@ -231,10 +231,10 @@ extern __inline__ uint iopin_is_act(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1; } return 0; @@ -244,16 +244,16 @@ extern __inline__ void iopin_set_ded(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; *parp |= (1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; *parp |= (1 << (31 - iopin->pin)); } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; *parp |= (1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; *parp |= (1 << (15 - iopin->pin)); } } @@ -262,16 +262,16 @@ extern __inline__ void iopin_set_gen(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; *parp &= ~(1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; *parp &= ~(1 << (31 - iopin->pin)); } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; *parp &= ~(1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; *parp &= ~(1 << (15 - iopin->pin)); } } @@ -280,16 +280,16 @@ extern __inline__ uint iopin_is_ded(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; return (*parp >> (15 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; return (*parp >> (31 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; return (*parp >> (15 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; return (*parp >> (15 - iopin->pin)) & 1; } return 0; @@ -299,16 +299,16 @@ extern __inline__ uint iopin_is_gen(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; return ((*parp >> (31 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; } return 0; @@ -318,7 +318,7 @@ extern __inline__ void iopin_set_opt2(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso; + volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; *sorp |= (1 << (15 - iopin->pin)); } } @@ -327,7 +327,7 @@ extern __inline__ void iopin_set_opt1(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso; + volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; *sorp &= ~(1 << (15 - iopin->pin)); } } @@ -336,7 +336,7 @@ extern __inline__ uint iopin_is_opt2(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso; + volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; return (*sorp >> (15 - iopin->pin)) & 1; } return 0; @@ -346,7 +346,7 @@ extern __inline__ uint iopin_is_opt1(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso; + volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1; } return 0; @@ -356,7 +356,7 @@ extern __inline__ void iopin_set_falledge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint; + volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; *intp |= (1 << (15 - iopin->pin)); } } @@ -365,7 +365,7 @@ extern __inline__ void iopin_set_anyedge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint; + volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; *intp &= ~(1 << (15 - iopin->pin)); } } @@ -374,7 +374,7 @@ extern __inline__ uint iopin_is_falledge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint; + volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; return (*intp >> (15 - iopin->pin)) & 1; } return 0; @@ -384,7 +384,7 @@ extern __inline__ uint iopin_is_anyedge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint; + volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; return ((*intp >> (15 - iopin->pin)) & 1) ^ 1; } return 0; diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 8975e6c..fa92b90 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -138,6 +138,10 @@ typedef struct _MMU_context { extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ extern void _tlbia(void); /* invalidate all TLB entries */ +#ifdef CONFIG_ADDR_MAP +extern void init_addr_map(void); +#endif + typedef enum { IBAT0 = 0, IBAT1, IBAT2, IBAT3, DBAT0, DBAT1, DBAT2, DBAT3, @@ -153,25 +157,64 @@ extern void print_bats(void); #endif /* __ASSEMBLY__ */ -/* Block size masks */ -#define BL_128K 0x000 -#define BL_256K 0x001 -#define BL_512K 0x003 -#define BL_1M 0x007 -#define BL_2M 0x00F -#define BL_4M 0x01F -#define BL_8M 0x03F -#define BL_16M 0x07F -#define BL_32M 0x0FF -#define BL_64M 0x1FF -#define BL_128M 0x3FF -#define BL_256M 0x7FF +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 +#define BATU_INVALID 0x00000000 + +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 +#define BATL_NO_ACCESS 0x00000000 + +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 + +#define BATL_PP_NO_ACCESS BATL_PP_00 +#define BATL_PP_RO BATL_PP_01 +#define BATL_PP_RW BATL_PP_10 + +/* BAT Block size values */ +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc + +/* Block lengths for processors that support extended block length */ +#ifdef HID0_XBSEN +#define BATU_BL_512M 0x00003ffc +#define BATU_BL_1G 0x00007ffc +#define BATU_BL_2G 0x0000fffc +#define BATU_BL_4G 0x0001fffc +#define BATU_BL_MAX BATU_BL_4G +#else +#define BATU_BL_MAX BATU_BL_256M +#endif /* BAT Access Protection */ #define BPP_XX 0x00 /* No access */ #define BPP_RX 0x01 /* Read only */ #define BPP_RW 0x02 /* Read/write */ +/* Macros to get values from BATs, once data is in the BAT register format */ +#define BATU_VALID(x) (x & 0x3) +#define BATU_VADDR(x) (x & 0xfffe0000) +#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \ + | ((x & 0x0e00ULL) << 24) \ + | ((x & 0x04ULL) << 30))) +#define BATU_SIZE(x) (1UL << (fls((x & BATU_BL_MAX) >> 2) + 17)) + /* Used to set up SDR1 register */ #define HASH_TABLE_SIZE_64K 0x00010000 #define HASH_TABLE_SIZE_128K 0x00020000 @@ -431,6 +474,7 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn, extern void disable_tlb(u8 esel); extern void invalidate_tlb(u8 tlb); extern void init_tlbs(void); + extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h index d180e04..9680f70 100644 --- a/include/asm-ppc/ppc4xx-ebc.h +++ b/include/asm-ppc/ppc4xx-ebc.h @@ -35,7 +35,38 @@ #define CONFIG_EBC_PPC4xx_IBM_VER1 #endif +/* + * Define the max number of EBC banks (chip selects) + */ +#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \ + defined(CONFIG_405EZ) || \ + defined(CONFIG_440GP) || defined(CONFIG_440GX) +#define EBC_NUM_BANKS 8 +#endif + +#if defined(CONFIG_405EP) +#define EBC_NUM_BANKS 5 +#endif + +#if defined(CONFIG_405EX) || \ + defined(CONFIG_460SX) +#define EBC_NUM_BANKS 4 +#endif + +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define EBC_NUM_BANKS 6 +#endif + +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#define EBC_NUM_BANKS 3 +#endif + /* Bank Configuration Register */ +#define EBC_BXCR(n) (n) +#define EBC_BXCR_BANK_SIZE(n) (0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17)) + #define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) #define EBC_BXCR_BAS_ENCODE(n) (((static_cast(u32, n)) & EBC_BXCR_BAS_MASK)) #define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) diff --git a/include/asm-ppc/ppc4xx-isram.h b/include/asm-ppc/ppc4xx-isram.h new file mode 100644 index 0000000..d6d17ac --- /dev/null +++ b/include/asm-ppc/ppc4xx-isram.h @@ -0,0 +1,75 @@ + +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC4xx_ISRAM_H_ +#define _PPC4xx_ISRAM_H_ + +/* + * Internal SRAM + */ +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define ISRAM0_DCR_BASE 0x380 +#else +#define ISRAM0_DCR_BASE 0x020 +#endif +#define ISRAM0_SB0CR (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ +#define ISRAM0_SB1CR (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/ +#define ISRAM0_SB2CR (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/ +#define ISRAM0_SB3CR (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/ +#define ISRAM0_BEAR (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */ +#define ISRAM0_BESR0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */ +#define ISRAM0_BESR1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */ +#define ISRAM0_PMEG (ISRAM0_DCR_BASE+0x07) /* SRAM power management */ +#define ISRAM0_CID (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */ +#define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ +#define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define ISRAM1_DCR_BASE 0x0B0 +#define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ +#define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ +#define ISRAM1_BESR0 (ISRAM1_DCR_BASE+0x05) /* SRAM1 bus error status reg 0 */ +#define ISRAM1_BESR1 (ISRAM1_DCR_BASE+0x06) /* SRAM1 bus error status reg 1 */ +#define ISRAM1_PMEG (ISRAM1_DCR_BASE+0x07) /* SRAM1 power management */ +#define ISRAM1_CID (ISRAM1_DCR_BASE+0x08) /* SRAM1 bus core id reg */ +#define ISRAM1_REVID (ISRAM1_DCR_BASE+0x09) /* SRAM1 bus revision id reg */ +#define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */ +#endif /* CONFIG_460EX || CONFIG_460GT */ + +/* + * L2 Cache + */ +#if defined (CONFIG_440GX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) +#define L2_CACHE_BASE 0x030 +#define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ +#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ +#define L2_CACHE_ADDR (L2_CACHE_BASE+0x02) /* L2 Cache Address */ +#define L2_CACHE_DATA (L2_CACHE_BASE+0x03) /* L2 Cache Data */ +#define L2_CACHE_STAT (L2_CACHE_BASE+0x04) /* L2 Cache Status */ +#define L2_CACHE_CVER (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */ +#define L2_CACHE_SNP0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */ +#define L2_CACHE_SNP1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */ +#endif /* CONFIG_440GX */ + +#endif /* _PPC4xx_ISRAM_H_ */ diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 8efa557..992a3d2 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -272,8 +272,11 @@ #define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ #define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ #define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1HB_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */ #define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ #define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ +#define SDRAM_CONF1HB_WRCL 0x00000080 /* MCIF Cycle Limit 1 - Bits 22..24 */ +#define SDRAM_CONF1HB_MASK 0x0000F380 /* RPLM & WRCL mask */ #define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ #define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ @@ -284,8 +287,10 @@ #define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ #define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ #define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1LL_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */ #define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ #define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ +#define SDRAM_CONF1LL_MASK 0x0000F000 /* RPLM mask */ #define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ #define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ @@ -561,6 +566,8 @@ #define SDRAM_RDCC_RSAE_MASK 0x00000001 #define SDRAM_RDCC_RSAE_DISABLE 0x00000001 #define SDRAM_RDCC_RSAE_ENABLE 0x00000000 +#define SDRAM_RDCC_RDSS_ENCODE(n) ((((u32)(n))&0x03)<<30) +#define SDRAM_RDCC_RDSS_DECODE(n) ((((u32)(n))>>30)&0x03) /* * SDRAM Read Feedback Delay Control Register diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index e07e5d3..5b29de0 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -451,6 +451,8 @@ #define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ #define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */ +#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ +#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ @@ -777,6 +779,13 @@ #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ +/* e600 core PVR fields */ + +#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ +#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ +#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ +#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ + /* Processor Version Numbers */ #define PVR_403GA 0x00200000 @@ -857,7 +866,6 @@ #define PVR_85xx_REV2 (PVR_85xx | 0x0020) #define PVR_86xx 0x80040000 -#define PVR_86xx_REV1 (PVR_86xx | 0x0010) #define PVR_VIRTEX5 0x7ff21912 @@ -949,6 +957,8 @@ #define SVR_8568_E 0x807D00 #define SVR_8572 0x80E000 #define SVR_8572_E 0x80E800 +#define SVR_P2020 0x80E200 +#define SVR_P2020_E 0x80EA00 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 diff --git a/include/asm-ppc/status_led.h b/include/asm-ppc/status_led.h index eb81f37..0375709 100644 --- a/include/asm-ppc/status_led.h +++ b/include/asm-ppc/status_led.h @@ -24,7 +24,7 @@ typedef unsigned long led_id_t; static inline void __led_init (led_id_t mask, int state) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; #ifdef STATUS_LED_PAR immr->STATUS_LED_PAR &= ~mask; @@ -51,12 +51,12 @@ static inline void __led_init (led_id_t mask, int state) static inline void __led_toggle (led_id_t mask) { - ((immap_t *) CFG_IMMR)->STATUS_LED_DAT ^= mask; + ((immap_t *) CONFIG_SYS_IMMR)->STATUS_LED_DAT ^= mask; } static inline void __led_set (led_id_t mask, int state) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; #if (STATUS_LED_ACTIVE == 0) if (state == STATUS_LED_ON) diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index 54ac01d..7451905 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -111,6 +111,12 @@ typedef struct bd_info { #ifdef CONFIG_HAS_ETH3 unsigned char bi_enet3addr[6]; #endif +#ifdef CONFIG_HAS_ETH4 + unsigned char bi_enet4addr[6]; +#endif +#ifdef CONFIG_HAS_ETH5 + unsigned char bi_enet5addr[6]; +#endif #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ |