diff options
Diffstat (limited to 'include/asm-ppc')
| -rw-r--r-- | include/asm-ppc/immap_85xx.h | 6 | ||||
| -rw-r--r-- | include/asm-ppc/immap_86xx.h | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index dc6e278..2d07625 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -92,7 +92,7 @@ typedef struct ccsr_ddr { uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */ uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */ char res5[48]; - uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */ + uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ @@ -106,8 +106,8 @@ typedef struct ccsr_ddr { char res6[4]; uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ char res7[20]; - uint init_address; /* 0x2148 - DDR training initialization address */ - uint init_ext_address; /* 0x214C - DDR training initialization extended address */ + uint init_addr; /* 0x2148 - DDR training initialization address */ + uint init_ext_addr; /* 0x214C - DDR training initialization extended address */ char res8_1[16]; uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */ uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 7526061..0b78c94 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -109,7 +109,7 @@ typedef struct ccsr_ddr { uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ char res7[104]; - uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ + uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ @@ -126,7 +126,7 @@ typedef struct ccsr_ddr { uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ uint init_addr; /* 0x2148 - DDR training initialzation address */ - uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */ + uint init_ext_addr; /* 0x214C - DDR training initialzation extended address */ char res10[2728]; uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ |