diff options
Diffstat (limited to 'include/asm-ppc')
-rw-r--r-- | include/asm-ppc/e300.h | 16 | ||||
-rw-r--r-- | include/asm-ppc/global_data.h | 6 | ||||
-rw-r--r-- | include/asm-ppc/immap_83xx.h | 56 | ||||
-rw-r--r-- | include/asm-ppc/io.h | 89 | ||||
-rw-r--r-- | include/asm-ppc/mmu.h | 5 | ||||
-rw-r--r-- | include/asm-ppc/processor.h | 20 |
6 files changed, 131 insertions, 61 deletions
diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h index ff9512f..d1bb159 100644 --- a/include/asm-ppc/e300.h +++ b/include/asm-ppc/e300.h @@ -6,19 +6,9 @@ #ifndef __E300_H__ #define __E300_H__ -/* - * e300 Processor Version & Revision Numbers - */ -#define PVR_83xx 0x80830000 -#define PVR_8349_REV10 (PVR_83xx | 0x0010) -#define PVR_8349_REV11 (PVR_83xx | 0x0011) -#define PVR_8360_REV10 (PVR_83xx | 0x0020) -#define PVR_8360_REV11 (PVR_83xx | 0x0020) - -#if defined(CONFIG_MPC832X) -#undef PVR_83xx -#define PVR_83xx 0x80840000 -#endif +#define PVR_E300C1 0x80830000 +#define PVR_E300C2 0x80840000 +#define PVR_E300C3 0x80850000 /* * Hardware Implementation-Dependent Register 0 (HID0) diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 26bc875..cd24636 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -55,11 +55,13 @@ typedef struct global_data { #if defined(CONFIG_MPC83XX) /* There are other clocks in the MPC83XX */ u32 csb_clk; -#if defined (CONFIG_MPC834X) +#if defined (CONFIG_MPC834X) || defined(CONFIG_MPC831X) u32 tsec1_clk; u32 tsec2_clk; - u32 usbmph_clk; u32 usbdr_clk; +#endif +#if defined (CONFIG_MPC834X) + u32 usbmph_clk; #endif /* CONFIG_MPC834X */ u32 core_clk; u32 i2c1_clk; diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 5e088d6..0de9338 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -206,7 +206,9 @@ typedef struct pmc83xx { u32 pmccr; /* PMC Configuration Register */ u32 pmcer; /* PMC Event Register */ u32 pmcmr; /* PMC Mask Register */ - u8 res0[0xF4]; + u32 pmccr1; /* PMC Configuration Register 1 */ + u32 pmccr2; /* PMC Configuration Register 2 */ + u8 res0[0xEC]; } pmc83xx_t; /* @@ -355,7 +357,8 @@ typedef struct lbus83xx { u8 res2[0x8]; u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ u32 mdr; /* UPM Data Register */ - u8 res3[0x8]; + u8 res3[0x4]; + u32 lsor; /* Special Operation Initiation Register */ u32 lsdmr; /* SDRAM Mode Register */ u8 res4[0x8]; u32 lurt; /* UPM Refresh Timer */ @@ -369,8 +372,14 @@ typedef struct lbus83xx { u8 res6[0xC]; u32 lbcr; /* Configuration Register */ u32 lcrr; /* Clock Ratio Register */ - u8 res7[0x28]; - u8 res8[0xF00]; + u8 res7[0x8]; + u32 fmr; /* Flash Mode Register */ + u32 fir; /* Flash Instruction Register */ + u32 fcr; /* Flash Command Register */ + u32 fbar; /* Flash Block Addr Register */ + u32 fpar; /* Flash Page Addr Register */ + u32 fbcr; /* Flash Byte Count Register */ + u8 res8[0xF08]; } lbus83xx_t; /* @@ -527,7 +536,7 @@ typedef struct pcictrl83xx { * USB */ typedef struct usb83xx { - u8 fixme[0x2000]; + u8 fixme[0x1000]; } usb83xx_t; /* @@ -574,7 +583,42 @@ typedef struct immap { ios83xx_t ios; /* Sequencer */ pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ u8 res5[0x19900]; - usb83xx_t usb; + usb83xx_t usb[2]; + tsec83xx_t tsec[2]; + u8 res6[0xA000]; + security83xx_t security; + u8 res7[0xC0000]; +} immap_t; + +#elif defined(CONFIG_MPC831X) +typedef struct immap { + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + gtm83xx_t gtm[2]; /* Global Timers Module */ + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + gpio83xx_t gpio[1]; /* General purpose I/O module */ + u8 res0[0x1300]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res1[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res2[0x900]; + lbus83xx_t lbus; /* Local Bus Controller Registers */ + u8 res3[0x1000]; + spi83xx_t spi; /* Serial Peripheral Interface */ + dma83xx_t dma; /* DMA */ + pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ + u8 res4[0x80]; + ios83xx_t ios; /* Sequencer */ + pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ + u8 res5[0x1aa00]; + usb83xx_t usb[1]; tsec83xx_t tsec[2]; u8 res6[0xA000]; security83xx_t security; diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index bbc9ba0..03289bc 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -105,6 +105,11 @@ static inline void sync(void) __asm__ __volatile__ ("sync" : : : "memory"); } +static inline void isync(void) +{ + __asm__ __volatile__ ("isync" : : : "memory"); +} + /* Enforce in-order execution of data I/O. * No distinction between read/write on PPC; use eieio for all three. */ @@ -114,74 +119,90 @@ static inline void sync(void) /* * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. + * + * Read operations have additional twi & isync to make sure the read + * is actually performed (i.e. the data has come back) before we start + * executing any following instructions. */ -extern inline int in_8(volatile u8 *addr) +#define __iomem +extern inline int in_8(const volatile unsigned char __iomem *addr) { - int ret; + int ret; - __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; + __asm__ __volatile__( + "sync; lbz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; } -extern inline void out_8(volatile u8 *addr, int val) +extern inline void out_8(volatile unsigned char __iomem *addr, int val) { - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); } -extern inline int in_le16(volatile u16 *addr) +extern inline int in_le16(const volatile unsigned short __iomem *addr) { - int ret; + int ret; - __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; + __asm__ __volatile__("sync; lhbrx %0,0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; } -extern inline int in_be16(volatile u16 *addr) +extern inline int in_be16(const volatile unsigned short __iomem *addr) { - int ret; + int ret; - __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; + __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; } -extern inline void out_le16(volatile u16 *addr, int val) +extern inline void out_le16(volatile unsigned short __iomem *addr, int val) { - __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : - "r" (val), "r" (addr)); + __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : + "r" (val), "r" (addr)); } -extern inline void out_be16(volatile u16 *addr, int val) +extern inline void out_be16(volatile unsigned short __iomem *addr, int val) { - __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } -extern inline unsigned in_le32(volatile u32 *addr) +extern inline unsigned in_le32(const volatile unsigned __iomem *addr) { - unsigned ret; + unsigned ret; - __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; + __asm__ __volatile__("sync; lwbrx %0,0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; } -extern inline unsigned in_be32(volatile u32 *addr) +extern inline unsigned in_be32(const volatile unsigned __iomem *addr) { - unsigned ret; + unsigned ret; - __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; + __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; } -extern inline void out_le32(volatile unsigned *addr, int val) +extern inline void out_le32(volatile unsigned __iomem *addr, int val) { - __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : - "r" (val), "r" (addr)); + __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : + "r" (val), "r" (addr)); } -extern inline void out_be32(volatile unsigned *addr, int val) +extern inline void out_be32(volatile unsigned __iomem *addr, int val) { - __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } #endif diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index b226825..48fd982 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -396,8 +396,8 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define BOOKE_PAGESZ_16M 7 #define BOOKE_PAGESZ_64M 8 #define BOOKE_PAGESZ_256M 9 -#define BOOKE_PAGESZ_1GB 10 -#define BOOKE_PAGESZ_4GB 11 +#define BOOKE_PAGESZ_1G 10 +#define BOOKE_PAGESZ_4G 11 #if defined(CONFIG_MPC86xx) #define LAWBAR_BASE_ADDR 0x00FFFFFF @@ -413,6 +413,7 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 +#define LAWAR_TRGT_IF_PEX 0x00200000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 0585962..5efc3ee 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -232,6 +232,9 @@ #define HID0_BHTE (1<<2) /* Branch History Table Enable */ #define HID0_BTCD (1<<1) /* Branch target cache disable */ #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ +#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ +#define HID1_ASTME (1<<13) /* Address bus streaming mode */ +#define HID1_ABE (1<<12) /* Address broadcast enable */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ @@ -415,10 +418,12 @@ #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ /* e500 definitions */ -#define SPRN_L1CSR0 0x3f2 /* L1 Cache Control and Status Register 0 */ +#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ +#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ -#define SPRN_L1CSR1 0x3f3 /* L1 Cache Control and Status Register 1 */ +#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ +#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ @@ -701,8 +706,6 @@ #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ -/* System-On-Chip Version Numbers (version field only) */ -#define SVR_MPC5200 0x8011 /* Processor Version Register */ @@ -813,6 +816,12 @@ #define PVR_8260_HIP7R1 0x80822013 #define PVR_8260_HIP7RA 0x80822014 +/* + * MPC 52xx + */ +#define PVR_5200 0x80822011 +#define PVR_5200B 0x80822014 + /* * System Version Register @@ -840,9 +849,12 @@ #define SVR_8560 0x8070 #define SVR_8555 0x8079 #define SVR_8541 0x807A +#define SVR_8544 0x8034 +#define SVR_8544_E 0x803C #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 #define SVR_8641 0x8090 +#define SVR_8568_E 0x807D /* I am just adding a single entry for 8260 boards. I think we may be |